Metadata-Version: 2.1
Name: manta-fpga
Version: 1.1.0
Summary: A configurable and approachable tool for FPGA debugging and rapid prototyping
Author-email: Fischer Moseley <fischer.moseley@gmail.com>
Project-URL: Homepage, https://github.com/fischermoseley/manta
Project-URL: Documentation, https://fischermoseley.github.io/manta
Project-URL: Issues, https://github.com/fischermoseley/manta/issues
Classifier: License :: OSI Approved :: GNU General Public License v3 (GPLv3)
Requires-Python: >=3.9
Description-Content-Type: text/markdown
License-File: LICENSE.txt
Requires-Dist: amaranth[builtin-yosys]>=0.5.0
Requires-Dist: PyYAML
Requires-Dist: pyserial
Requires-Dist: liteeth==2023.12
Requires-Dist: pyvcd
Provides-Extra: dev
Requires-Dist: pytest; extra == "dev"
Requires-Dist: pytest-cov; extra == "dev"
Requires-Dist: codecov; extra == "dev"
Requires-Dist: pre-commit; extra == "dev"
Requires-Dist: ruff; extra == "dev"
Requires-Dist: mkdocs-material; extra == "dev"
Requires-Dist: mkdocstrings[python]; extra == "dev"
Requires-Dist: mike; extra == "dev"

![](https://raw.githubusercontent.com/fischermoseley/manta/refs/heads/main/doc/assets/logo.png)

## Manta: A Configurable and Approachable Tool for FPGA Debugging and Rapid Prototyping
![run_tests](https://github.com/fischermoseley/manta/actions/workflows/run_tests.yml/badge.svg)
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[![codecov](https://codecov.io/gh/fischermoseley/manta/graph/badge.svg?token=1GGHCICK3Q)](https://codecov.io/gh/fischermoseley/manta)
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Manta is a tool for getting information into and out of FPGAs over an interface like UART or Ethernet. It's primarily intended for debugging, but it's robust enough to be a simple, reliable transport layer between a FPGA and a host machine. It lets you configure a series of cores on a shared bus via a YAML or JSON file, and then provides a Python API to each core, along with vendor-agnostic Verilog HDL to instantiate them on your FPGA.

For more information check out the docs:
[https://fischermoseley.github.io/manta](https://fischermoseley.github.io/manta)
