tb

decida.tb.tb(netlistdir, testbench, check=False, mod_dir=None)

read SmartSpice, Verilog netlist, generate new Verilog netlist.

use to generate a verilog test-bench. requires sspice netlist for correct bus notation. requires verilog for port directions. mod_dir has verilog files that overwrite modules in library.

arguments:

netlistdir (string)

directory where netlists *.nes *.v have been produced

testbench (string)

netlist prefix

check (boolean) (optional, default=False)

if True, produce check files for debugging

mod_dir (string) (optional, default=None)

directory containing behavioral or modified modules to overwrite generated ones

procedure: (% is a note specifically for the wrapper script)

  1. create a top-level schematic in Gateway

  2. simulation->create specific netlist:

    1. Type=SmartSpice, check “Make .SUBCKT”,

      change extension of netlist from .net to .nes (to avoid overwriting non-subckt testbench for python script)

    2. Type=Verilog,

      change extension of netlist from .net to .v

  3. edit wrapper script to point to the netlist directory and testbench prefix

  4. % if there are behavioral verilog modules that replace ones in the schematic, create a directory for them and point to it using the mod_dir parameter to the tb command

  5. % run the wrapper script

    1. creates a new directory with the name ${testbench}_lib, where testbench is the root of the verilog netlist name
    2. every module in the schematic comes out as a separate verilog module file in the *_lib directory.
    3. if mod_lib was specified, files are copied from there to *_lib and if replacing existing modules, the originals are copied to *.orig
    4. the toplevel testbench is a module in *_lib it is moved to the current directory and copied to *.orig
  6. edit the toplevel testbench and put in head.x at the top of the file if available to include the testbench sequence, tasks, etc.

  7. start Silos and create or load existing project add libraries = *_lib directory, standard-cell library add files = top-level testbench

  8. flush out all compilation errors

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