Args: clang (LLVM option parsing) -global-isel=1 -debug -print-after-all -print-before-all 
Clearing AST...
; *** IR Dump Before Annotation2MetadataPass on [module] ***
; ModuleID = 'cecil_test.c'
source_filename = "cecil_test.c"
target datalayout = "e-m:e-p:32:32-i64:64-n32-S128"
target triple = "riscv32-unknown-unknown"

; Function Attrs: nounwind
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) #0 {
entry:
  %acc.addr = alloca i32, align 4
  %x.addr = alloca i32, align 4
  %y.addr = alloca i32, align 4
  store i32 %acc, ptr %acc.addr, align 4, !tbaa !4
  store i32 %x, ptr %x.addr, align 4, !tbaa !4
  store i32 %y, ptr %y.addr, align 4, !tbaa !4
  %0 = load i32, ptr %x.addr, align 4, !tbaa !4
  %and = and i32 %0, 65535
  %conv = trunc i32 %and to i16
  %conv1 = sext i16 %conv to i32
  %1 = load i32, ptr %y.addr, align 4, !tbaa !4
  %and2 = and i32 %1, 65535
  %conv3 = trunc i32 %and2 to i16
  %conv4 = sext i16 %conv3 to i32
  %mul = mul nsw i32 %conv1, %conv4
  %2 = load i32, ptr %acc.addr, align 4, !tbaa !4
  %add = add nsw i32 %2, %mul
  store i32 %add, ptr %acc.addr, align 4, !tbaa !4
  %3 = load i32, ptr %x.addr, align 4, !tbaa !4
  %shr = ashr i32 %3, 16
  %and5 = and i32 %shr, 65535
  %conv6 = trunc i32 %and5 to i16
  %conv7 = sext i16 %conv6 to i32
  %4 = load i32, ptr %y.addr, align 4, !tbaa !4
  %shr8 = ashr i32 %4, 16
  %and9 = and i32 %shr8, 65535
  %conv10 = trunc i32 %and9 to i16
  %conv11 = sext i16 %conv10 to i32
  %mul12 = mul nsw i32 %conv7, %conv11
  %5 = load i32, ptr %acc.addr, align 4, !tbaa !4
  %add13 = add nsw i32 %5, %mul12
  store i32 %add13, ptr %acc.addr, align 4, !tbaa !4
  %6 = load i32, ptr %acc.addr, align 4, !tbaa !4
  ret i32 %6
}

attributes #0 = { nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="generic-rv32" "target-features"="+32bit,+m,+relax,+xseal5testalucvabs16,+xseal5testalucvabs32,+xseal5testalucvabs8,+xseal5testalucvaddnrsi16,+xseal5testalucvaddnrsi32,+xseal5testalucvaddnrui16,+xseal5testalucvaddnrui32,+xseal5testalucvaddns,+xseal5testalucvaddnu,+xseal5testalucvaddrnrsi16,+xseal5testalucvaddrnrsi32,+xseal5testalucvaddrnrui16,+xseal5testalucvaddrnrui32,+xseal5testalucvaddrns,+xseal5testalucvaddrnu,+xseal5testalucvextbs,+xseal5testalucvextbz,+xseal5testalucvexths,+xseal5testalucvexthz,+xseal5testalucvmaxi1216,+xseal5testalucvmaxi1232,+xseal5testalucvmaxi516,+xseal5testalucvmaxi532,+xseal5testalucvmaxs16,+xseal5testalucvmaxs32,+xseal5testalucvmaxs8,+xseal5testalucvmaxu16,+xseal5testalucvmaxu32,+xseal5testalucvmaxu8,+xseal5testalucvmini1216,+xseal5testalucvmini1232,+xseal5testalucvmini516,+xseal5testalucvmini532,+xseal5testalucvmins16,+xseal5testalucvmins32,+xseal5testalucvmins8,+xseal5testalucvminu16,+xseal5testalucvminu32,+xseal5testalucvminu8,+xseal5testalucvsletsi16,+xseal5testalucvsletsi32,+xseal5testalucvsletui16,+xseal5testalucvsletui32,+xseal5testalucvsubnrsi16,+xseal5testalucvsubnrsi32,+xseal5testalucvsubnrui16,+xseal5testalucvsubnrui32,+xseal5testalucvsubns,+xseal5testalucvsubnu,+xseal5testalucvsubrnrsi16,+xseal5testalucvsubrnrsi32,+xseal5testalucvsubrnrui16,+xseal5testalucvsubrnrui32,+xseal5testalucvsubrns,+xseal5testalucvsubrnu,+xseal5testmaccvmachhns,+xseal5testmaccvmachhnu,+xseal5testmaccvmachhrns,+xseal5testmaccvmachhrnu,+xseal5testmaccvmacns,+xseal5testmaccvmacnu,+xseal5testmaccvmacrns,+xseal5testmaccvmacrnu,+xseal5testmaccvmacsi16,+xseal5testmaccvmacsi32,+xseal5testmaccvmacui16,+xseal5testmaccvmacui32,+xseal5testmaccvmsusi16,+xseal5testmaccvmsusi32,+xseal5testmaccvmsuui16,+xseal5testmaccvmsuui32,+xseal5testmaccvmulhhns,+xseal5testmaccvmulhhnu,+xseal5testmaccvmulhhrns,+xseal5testmaccvmulhhrnu,+xseal5testmaccvmulns,+xseal5testmaccvmulnu,+xseal5testmaccvmulrns,+xseal5testmaccvmulrnu,-a,-c,-d,-e,-experimental-zacas,-experimental-zcmop,-experimental-zfbfmin,-experimental-zicfilp,-experimental-zicfiss,-experimental-zimop,-experimental-ztso,-experimental-zvfbfmin,-experimental-zvfbfwma,-f,-h,-smaia,-smepmp,-ssaia,-svinval,-svnapot,-svpbmt,-v,-xcvalu,-xcvbi,-xcvbitmanip,-xcvelw,-xcvmac,-xcvmem,-xcvsimd,-xsfvcp,-xsfvfnrclipxfqf,-xsfvfwmaccqqq,-xsfvqmaccdod,-xsfvqmaccqoq,-xtheadba,-xtheadbb,-xtheadbs,-xtheadcmo,-xtheadcondmov,-xtheadfmemidx,-xtheadmac,-xtheadmemidx,-xtheadmempair,-xtheadsync,-xtheadvdot,-xventanacondops,-za128rs,-za64rs,-zawrs,-zba,-zbb,-zbc,-zbkb,-zbkc,-zbkx,-zbs,-zca,-zcb,-zcd,-zce,-zcf,-zcmp,-zcmt,-zdinx,-zfa,-zfh,-zfhmin,-zfinx,-zhinx,-zhinxmin,-zic64b,-zicbom,-zicbop,-zicboz,-ziccamoa,-ziccif,-zicclsm,-ziccrse,-zicntr,-zicond,-zicsr,-zifencei,-zihintntl,-zihintpause,-zihpm,-zk,-zkn,-zknd,-zkne,-zknh,-zkr,-zks,-zksed,-zksh,-zkt,-zmmul,-zvbb,-zvbc,-zve32f,-zve32x,-zve64d,-zve64f,-zve64x,-zvfh,-zvfhmin,-zvkb,-zvkg,-zvkn,-zvknc,-zvkned,-zvkng,-zvknha,-zvknhb,-zvks,-zvksc,-zvksed,-zvksg,-zvksh,-zvkt,-zvl1024b,-zvl128b,-zvl16384b,-zvl2048b,-zvl256b,-zvl32768b,-zvl32b,-zvl4096b,-zvl512b,-zvl64b,-zvl65536b,-zvl8192b" }

!llvm.module.flags = !{!0, !1, !2}
!llvm.ident = !{!3}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 1, !"target-abi", !"ilp32"}
!2 = !{i32 8, !"SmallDataLimit", i32 8}
!3 = !{!"clang version 18.1.0rc (https://github.com/llvm/llvm-project.git 1acc4e456481e76822c76c850bad3994d4e04b59)"}
!4 = !{!5, !5, i64 0}
!5 = !{!"int", !6, i64 0}
!6 = !{!"omnipotent char", !7, i64 0}
!7 = !{!"Simple C/C++ TBAA"}
; *** IR Dump After Annotation2MetadataPass on [module] ***
; ModuleID = 'cecil_test.c'
source_filename = "cecil_test.c"
target datalayout = "e-m:e-p:32:32-i64:64-n32-S128"
target triple = "riscv32-unknown-unknown"

; Function Attrs: nounwind
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) #0 {
entry:
  %acc.addr = alloca i32, align 4
  %x.addr = alloca i32, align 4
  %y.addr = alloca i32, align 4
  store i32 %acc, ptr %acc.addr, align 4, !tbaa !4
  store i32 %x, ptr %x.addr, align 4, !tbaa !4
  store i32 %y, ptr %y.addr, align 4, !tbaa !4
  %0 = load i32, ptr %x.addr, align 4, !tbaa !4
  %and = and i32 %0, 65535
  %conv = trunc i32 %and to i16
  %conv1 = sext i16 %conv to i32
  %1 = load i32, ptr %y.addr, align 4, !tbaa !4
  %and2 = and i32 %1, 65535
  %conv3 = trunc i32 %and2 to i16
  %conv4 = sext i16 %conv3 to i32
  %mul = mul nsw i32 %conv1, %conv4
  %2 = load i32, ptr %acc.addr, align 4, !tbaa !4
  %add = add nsw i32 %2, %mul
  store i32 %add, ptr %acc.addr, align 4, !tbaa !4
  %3 = load i32, ptr %x.addr, align 4, !tbaa !4
  %shr = ashr i32 %3, 16
  %and5 = and i32 %shr, 65535
  %conv6 = trunc i32 %and5 to i16
  %conv7 = sext i16 %conv6 to i32
  %4 = load i32, ptr %y.addr, align 4, !tbaa !4
  %shr8 = ashr i32 %4, 16
  %and9 = and i32 %shr8, 65535
  %conv10 = trunc i32 %and9 to i16
  %conv11 = sext i16 %conv10 to i32
  %mul12 = mul nsw i32 %conv7, %conv11
  %5 = load i32, ptr %acc.addr, align 4, !tbaa !4
  %add13 = add nsw i32 %5, %mul12
  store i32 %add13, ptr %acc.addr, align 4, !tbaa !4
  %6 = load i32, ptr %acc.addr, align 4, !tbaa !4
  ret i32 %6
}

attributes #0 = { nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="generic-rv32" "target-features"="+32bit,+m,+relax,+xseal5testalucvabs16,+xseal5testalucvabs32,+xseal5testalucvabs8,+xseal5testalucvaddnrsi16,+xseal5testalucvaddnrsi32,+xseal5testalucvaddnrui16,+xseal5testalucvaddnrui32,+xseal5testalucvaddns,+xseal5testalucvaddnu,+xseal5testalucvaddrnrsi16,+xseal5testalucvaddrnrsi32,+xseal5testalucvaddrnrui16,+xseal5testalucvaddrnrui32,+xseal5testalucvaddrns,+xseal5testalucvaddrnu,+xseal5testalucvextbs,+xseal5testalucvextbz,+xseal5testalucvexths,+xseal5testalucvexthz,+xseal5testalucvmaxi1216,+xseal5testalucvmaxi1232,+xseal5testalucvmaxi516,+xseal5testalucvmaxi532,+xseal5testalucvmaxs16,+xseal5testalucvmaxs32,+xseal5testalucvmaxs8,+xseal5testalucvmaxu16,+xseal5testalucvmaxu32,+xseal5testalucvmaxu8,+xseal5testalucvmini1216,+xseal5testalucvmini1232,+xseal5testalucvmini516,+xseal5testalucvmini532,+xseal5testalucvmins16,+xseal5testalucvmins32,+xseal5testalucvmins8,+xseal5testalucvminu16,+xseal5testalucvminu32,+xseal5testalucvminu8,+xseal5testalucvsletsi16,+xseal5testalucvsletsi32,+xseal5testalucvsletui16,+xseal5testalucvsletui32,+xseal5testalucvsubnrsi16,+xseal5testalucvsubnrsi32,+xseal5testalucvsubnrui16,+xseal5testalucvsubnrui32,+xseal5testalucvsubns,+xseal5testalucvsubnu,+xseal5testalucvsubrnrsi16,+xseal5testalucvsubrnrsi32,+xseal5testalucvsubrnrui16,+xseal5testalucvsubrnrui32,+xseal5testalucvsubrns,+xseal5testalucvsubrnu,+xseal5testmaccvmachhns,+xseal5testmaccvmachhnu,+xseal5testmaccvmachhrns,+xseal5testmaccvmachhrnu,+xseal5testmaccvmacns,+xseal5testmaccvmacnu,+xseal5testmaccvmacrns,+xseal5testmaccvmacrnu,+xseal5testmaccvmacsi16,+xseal5testmaccvmacsi32,+xseal5testmaccvmacui16,+xseal5testmaccvmacui32,+xseal5testmaccvmsusi16,+xseal5testmaccvmsusi32,+xseal5testmaccvmsuui16,+xseal5testmaccvmsuui32,+xseal5testmaccvmulhhns,+xseal5testmaccvmulhhnu,+xseal5testmaccvmulhhrns,+xseal5testmaccvmulhhrnu,+xseal5testmaccvmulns,+xseal5testmaccvmulnu,+xseal5testmaccvmulrns,+xseal5testmaccvmulrnu,-a,-c,-d,-e,-experimental-zacas,-experimental-zcmop,-experimental-zfbfmin,-experimental-zicfilp,-experimental-zicfiss,-experimental-zimop,-experimental-ztso,-experimental-zvfbfmin,-experimental-zvfbfwma,-f,-h,-smaia,-smepmp,-ssaia,-svinval,-svnapot,-svpbmt,-v,-xcvalu,-xcvbi,-xcvbitmanip,-xcvelw,-xcvmac,-xcvmem,-xcvsimd,-xsfvcp,-xsfvfnrclipxfqf,-xsfvfwmaccqqq,-xsfvqmaccdod,-xsfvqmaccqoq,-xtheadba,-xtheadbb,-xtheadbs,-xtheadcmo,-xtheadcondmov,-xtheadfmemidx,-xtheadmac,-xtheadmemidx,-xtheadmempair,-xtheadsync,-xtheadvdot,-xventanacondops,-za128rs,-za64rs,-zawrs,-zba,-zbb,-zbc,-zbkb,-zbkc,-zbkx,-zbs,-zca,-zcb,-zcd,-zce,-zcf,-zcmp,-zcmt,-zdinx,-zfa,-zfh,-zfhmin,-zfinx,-zhinx,-zhinxmin,-zic64b,-zicbom,-zicbop,-zicboz,-ziccamoa,-ziccif,-zicclsm,-ziccrse,-zicntr,-zicond,-zicsr,-zifencei,-zihintntl,-zihintpause,-zihpm,-zk,-zkn,-zknd,-zkne,-zknh,-zkr,-zks,-zksed,-zksh,-zkt,-zmmul,-zvbb,-zvbc,-zve32f,-zve32x,-zve64d,-zve64f,-zve64x,-zvfh,-zvfhmin,-zvkb,-zvkg,-zvkn,-zvknc,-zvkned,-zvkng,-zvknha,-zvknhb,-zvks,-zvksc,-zvksed,-zvksg,-zvksh,-zvkt,-zvl1024b,-zvl128b,-zvl16384b,-zvl2048b,-zvl256b,-zvl32768b,-zvl32b,-zvl4096b,-zvl512b,-zvl64b,-zvl65536b,-zvl8192b" }

!llvm.module.flags = !{!0, !1, !2}
!llvm.ident = !{!3}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 1, !"target-abi", !"ilp32"}
!2 = !{i32 8, !"SmallDataLimit", i32 8}
!3 = !{!"clang version 18.1.0rc (https://github.com/llvm/llvm-project.git 1acc4e456481e76822c76c850bad3994d4e04b59)"}
!4 = !{!5, !5, i64 0}
!5 = !{!"int", !6, i64 0}
!6 = !{!"omnipotent char", !7, i64 0}
!7 = !{!"Simple C/C++ TBAA"}
; *** IR Dump Before ForceFunctionAttrsPass on [module] ***
; ModuleID = 'cecil_test.c'
source_filename = "cecil_test.c"
target datalayout = "e-m:e-p:32:32-i64:64-n32-S128"
target triple = "riscv32-unknown-unknown"

; Function Attrs: nounwind
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) #0 {
entry:
  %acc.addr = alloca i32, align 4
  %x.addr = alloca i32, align 4
  %y.addr = alloca i32, align 4
  store i32 %acc, ptr %acc.addr, align 4, !tbaa !4
  store i32 %x, ptr %x.addr, align 4, !tbaa !4
  store i32 %y, ptr %y.addr, align 4, !tbaa !4
  %0 = load i32, ptr %x.addr, align 4, !tbaa !4
  %and = and i32 %0, 65535
  %conv = trunc i32 %and to i16
  %conv1 = sext i16 %conv to i32
  %1 = load i32, ptr %y.addr, align 4, !tbaa !4
  %and2 = and i32 %1, 65535
  %conv3 = trunc i32 %and2 to i16
  %conv4 = sext i16 %conv3 to i32
  %mul = mul nsw i32 %conv1, %conv4
  %2 = load i32, ptr %acc.addr, align 4, !tbaa !4
  %add = add nsw i32 %2, %mul
  store i32 %add, ptr %acc.addr, align 4, !tbaa !4
  %3 = load i32, ptr %x.addr, align 4, !tbaa !4
  %shr = ashr i32 %3, 16
  %and5 = and i32 %shr, 65535
  %conv6 = trunc i32 %and5 to i16
  %conv7 = sext i16 %conv6 to i32
  %4 = load i32, ptr %y.addr, align 4, !tbaa !4
  %shr8 = ashr i32 %4, 16
  %and9 = and i32 %shr8, 65535
  %conv10 = trunc i32 %and9 to i16
  %conv11 = sext i16 %conv10 to i32
  %mul12 = mul nsw i32 %conv7, %conv11
  %5 = load i32, ptr %acc.addr, align 4, !tbaa !4
  %add13 = add nsw i32 %5, %mul12
  store i32 %add13, ptr %acc.addr, align 4, !tbaa !4
  %6 = load i32, ptr %acc.addr, align 4, !tbaa !4
  ret i32 %6
}

attributes #0 = { nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="generic-rv32" "target-features"="+32bit,+m,+relax,+xseal5testalucvabs16,+xseal5testalucvabs32,+xseal5testalucvabs8,+xseal5testalucvaddnrsi16,+xseal5testalucvaddnrsi32,+xseal5testalucvaddnrui16,+xseal5testalucvaddnrui32,+xseal5testalucvaddns,+xseal5testalucvaddnu,+xseal5testalucvaddrnrsi16,+xseal5testalucvaddrnrsi32,+xseal5testalucvaddrnrui16,+xseal5testalucvaddrnrui32,+xseal5testalucvaddrns,+xseal5testalucvaddrnu,+xseal5testalucvextbs,+xseal5testalucvextbz,+xseal5testalucvexths,+xseal5testalucvexthz,+xseal5testalucvmaxi1216,+xseal5testalucvmaxi1232,+xseal5testalucvmaxi516,+xseal5testalucvmaxi532,+xseal5testalucvmaxs16,+xseal5testalucvmaxs32,+xseal5testalucvmaxs8,+xseal5testalucvmaxu16,+xseal5testalucvmaxu32,+xseal5testalucvmaxu8,+xseal5testalucvmini1216,+xseal5testalucvmini1232,+xseal5testalucvmini516,+xseal5testalucvmini532,+xseal5testalucvmins16,+xseal5testalucvmins32,+xseal5testalucvmins8,+xseal5testalucvminu16,+xseal5testalucvminu32,+xseal5testalucvminu8,+xseal5testalucvsletsi16,+xseal5testalucvsletsi32,+xseal5testalucvsletui16,+xseal5testalucvsletui32,+xseal5testalucvsubnrsi16,+xseal5testalucvsubnrsi32,+xseal5testalucvsubnrui16,+xseal5testalucvsubnrui32,+xseal5testalucvsubns,+xseal5testalucvsubnu,+xseal5testalucvsubrnrsi16,+xseal5testalucvsubrnrsi32,+xseal5testalucvsubrnrui16,+xseal5testalucvsubrnrui32,+xseal5testalucvsubrns,+xseal5testalucvsubrnu,+xseal5testmaccvmachhns,+xseal5testmaccvmachhnu,+xseal5testmaccvmachhrns,+xseal5testmaccvmachhrnu,+xseal5testmaccvmacns,+xseal5testmaccvmacnu,+xseal5testmaccvmacrns,+xseal5testmaccvmacrnu,+xseal5testmaccvmacsi16,+xseal5testmaccvmacsi32,+xseal5testmaccvmacui16,+xseal5testmaccvmacui32,+xseal5testmaccvmsusi16,+xseal5testmaccvmsusi32,+xseal5testmaccvmsuui16,+xseal5testmaccvmsuui32,+xseal5testmaccvmulhhns,+xseal5testmaccvmulhhnu,+xseal5testmaccvmulhhrns,+xseal5testmaccvmulhhrnu,+xseal5testmaccvmulns,+xseal5testmaccvmulnu,+xseal5testmaccvmulrns,+xseal5testmaccvmulrnu,-a,-c,-d,-e,-experimental-zacas,-experimental-zcmop,-experimental-zfbfmin,-experimental-zicfilp,-experimental-zicfiss,-experimental-zimop,-experimental-ztso,-experimental-zvfbfmin,-experimental-zvfbfwma,-f,-h,-smaia,-smepmp,-ssaia,-svinval,-svnapot,-svpbmt,-v,-xcvalu,-xcvbi,-xcvbitmanip,-xcvelw,-xcvmac,-xcvmem,-xcvsimd,-xsfvcp,-xsfvfnrclipxfqf,-xsfvfwmaccqqq,-xsfvqmaccdod,-xsfvqmaccqoq,-xtheadba,-xtheadbb,-xtheadbs,-xtheadcmo,-xtheadcondmov,-xtheadfmemidx,-xtheadmac,-xtheadmemidx,-xtheadmempair,-xtheadsync,-xtheadvdot,-xventanacondops,-za128rs,-za64rs,-zawrs,-zba,-zbb,-zbc,-zbkb,-zbkc,-zbkx,-zbs,-zca,-zcb,-zcd,-zce,-zcf,-zcmp,-zcmt,-zdinx,-zfa,-zfh,-zfhmin,-zfinx,-zhinx,-zhinxmin,-zic64b,-zicbom,-zicbop,-zicboz,-ziccamoa,-ziccif,-zicclsm,-ziccrse,-zicntr,-zicond,-zicsr,-zifencei,-zihintntl,-zihintpause,-zihpm,-zk,-zkn,-zknd,-zkne,-zknh,-zkr,-zks,-zksed,-zksh,-zkt,-zmmul,-zvbb,-zvbc,-zve32f,-zve32x,-zve64d,-zve64f,-zve64x,-zvfh,-zvfhmin,-zvkb,-zvkg,-zvkn,-zvknc,-zvkned,-zvkng,-zvknha,-zvknhb,-zvks,-zvksc,-zvksed,-zvksg,-zvksh,-zvkt,-zvl1024b,-zvl128b,-zvl16384b,-zvl2048b,-zvl256b,-zvl32768b,-zvl32b,-zvl4096b,-zvl512b,-zvl64b,-zvl65536b,-zvl8192b" }

!llvm.module.flags = !{!0, !1, !2}
!llvm.ident = !{!3}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 1, !"target-abi", !"ilp32"}
!2 = !{i32 8, !"SmallDataLimit", i32 8}
!3 = !{!"clang version 18.1.0rc (https://github.com/llvm/llvm-project.git 1acc4e456481e76822c76c850bad3994d4e04b59)"}
!4 = !{!5, !5, i64 0}
!5 = !{!"int", !6, i64 0}
!6 = !{!"omnipotent char", !7, i64 0}
!7 = !{!"Simple C/C++ TBAA"}
; *** IR Dump After ForceFunctionAttrsPass on [module] ***
; ModuleID = 'cecil_test.c'
source_filename = "cecil_test.c"
target datalayout = "e-m:e-p:32:32-i64:64-n32-S128"
target triple = "riscv32-unknown-unknown"

; Function Attrs: nounwind
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) #0 {
entry:
  %acc.addr = alloca i32, align 4
  %x.addr = alloca i32, align 4
  %y.addr = alloca i32, align 4
  store i32 %acc, ptr %acc.addr, align 4, !tbaa !4
  store i32 %x, ptr %x.addr, align 4, !tbaa !4
  store i32 %y, ptr %y.addr, align 4, !tbaa !4
  %0 = load i32, ptr %x.addr, align 4, !tbaa !4
  %and = and i32 %0, 65535
  %conv = trunc i32 %and to i16
  %conv1 = sext i16 %conv to i32
  %1 = load i32, ptr %y.addr, align 4, !tbaa !4
  %and2 = and i32 %1, 65535
  %conv3 = trunc i32 %and2 to i16
  %conv4 = sext i16 %conv3 to i32
  %mul = mul nsw i32 %conv1, %conv4
  %2 = load i32, ptr %acc.addr, align 4, !tbaa !4
  %add = add nsw i32 %2, %mul
  store i32 %add, ptr %acc.addr, align 4, !tbaa !4
  %3 = load i32, ptr %x.addr, align 4, !tbaa !4
  %shr = ashr i32 %3, 16
  %and5 = and i32 %shr, 65535
  %conv6 = trunc i32 %and5 to i16
  %conv7 = sext i16 %conv6 to i32
  %4 = load i32, ptr %y.addr, align 4, !tbaa !4
  %shr8 = ashr i32 %4, 16
  %and9 = and i32 %shr8, 65535
  %conv10 = trunc i32 %and9 to i16
  %conv11 = sext i16 %conv10 to i32
  %mul12 = mul nsw i32 %conv7, %conv11
  %5 = load i32, ptr %acc.addr, align 4, !tbaa !4
  %add13 = add nsw i32 %5, %mul12
  store i32 %add13, ptr %acc.addr, align 4, !tbaa !4
  %6 = load i32, ptr %acc.addr, align 4, !tbaa !4
  ret i32 %6
}

attributes #0 = { nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="generic-rv32" "target-features"="+32bit,+m,+relax,+xseal5testalucvabs16,+xseal5testalucvabs32,+xseal5testalucvabs8,+xseal5testalucvaddnrsi16,+xseal5testalucvaddnrsi32,+xseal5testalucvaddnrui16,+xseal5testalucvaddnrui32,+xseal5testalucvaddns,+xseal5testalucvaddnu,+xseal5testalucvaddrnrsi16,+xseal5testalucvaddrnrsi32,+xseal5testalucvaddrnrui16,+xseal5testalucvaddrnrui32,+xseal5testalucvaddrns,+xseal5testalucvaddrnu,+xseal5testalucvextbs,+xseal5testalucvextbz,+xseal5testalucvexths,+xseal5testalucvexthz,+xseal5testalucvmaxi1216,+xseal5testalucvmaxi1232,+xseal5testalucvmaxi516,+xseal5testalucvmaxi532,+xseal5testalucvmaxs16,+xseal5testalucvmaxs32,+xseal5testalucvmaxs8,+xseal5testalucvmaxu16,+xseal5testalucvmaxu32,+xseal5testalucvmaxu8,+xseal5testalucvmini1216,+xseal5testalucvmini1232,+xseal5testalucvmini516,+xseal5testalucvmini532,+xseal5testalucvmins16,+xseal5testalucvmins32,+xseal5testalucvmins8,+xseal5testalucvminu16,+xseal5testalucvminu32,+xseal5testalucvminu8,+xseal5testalucvsletsi16,+xseal5testalucvsletsi32,+xseal5testalucvsletui16,+xseal5testalucvsletui32,+xseal5testalucvsubnrsi16,+xseal5testalucvsubnrsi32,+xseal5testalucvsubnrui16,+xseal5testalucvsubnrui32,+xseal5testalucvsubns,+xseal5testalucvsubnu,+xseal5testalucvsubrnrsi16,+xseal5testalucvsubrnrsi32,+xseal5testalucvsubrnrui16,+xseal5testalucvsubrnrui32,+xseal5testalucvsubrns,+xseal5testalucvsubrnu,+xseal5testmaccvmachhns,+xseal5testmaccvmachhnu,+xseal5testmaccvmachhrns,+xseal5testmaccvmachhrnu,+xseal5testmaccvmacns,+xseal5testmaccvmacnu,+xseal5testmaccvmacrns,+xseal5testmaccvmacrnu,+xseal5testmaccvmacsi16,+xseal5testmaccvmacsi32,+xseal5testmaccvmacui16,+xseal5testmaccvmacui32,+xseal5testmaccvmsusi16,+xseal5testmaccvmsusi32,+xseal5testmaccvmsuui16,+xseal5testmaccvmsuui32,+xseal5testmaccvmulhhns,+xseal5testmaccvmulhhnu,+xseal5testmaccvmulhhrns,+xseal5testmaccvmulhhrnu,+xseal5testmaccvmulns,+xseal5testmaccvmulnu,+xseal5testmaccvmulrns,+xseal5testmaccvmulrnu,-a,-c,-d,-e,-experimental-zacas,-experimental-zcmop,-experimental-zfbfmin,-experimental-zicfilp,-experimental-zicfiss,-experimental-zimop,-experimental-ztso,-experimental-zvfbfmin,-experimental-zvfbfwma,-f,-h,-smaia,-smepmp,-ssaia,-svinval,-svnapot,-svpbmt,-v,-xcvalu,-xcvbi,-xcvbitmanip,-xcvelw,-xcvmac,-xcvmem,-xcvsimd,-xsfvcp,-xsfvfnrclipxfqf,-xsfvfwmaccqqq,-xsfvqmaccdod,-xsfvqmaccqoq,-xtheadba,-xtheadbb,-xtheadbs,-xtheadcmo,-xtheadcondmov,-xtheadfmemidx,-xtheadmac,-xtheadmemidx,-xtheadmempair,-xtheadsync,-xtheadvdot,-xventanacondops,-za128rs,-za64rs,-zawrs,-zba,-zbb,-zbc,-zbkb,-zbkc,-zbkx,-zbs,-zca,-zcb,-zcd,-zce,-zcf,-zcmp,-zcmt,-zdinx,-zfa,-zfh,-zfhmin,-zfinx,-zhinx,-zhinxmin,-zic64b,-zicbom,-zicbop,-zicboz,-ziccamoa,-ziccif,-zicclsm,-ziccrse,-zicntr,-zicond,-zicsr,-zifencei,-zihintntl,-zihintpause,-zihpm,-zk,-zkn,-zknd,-zkne,-zknh,-zkr,-zks,-zksed,-zksh,-zkt,-zmmul,-zvbb,-zvbc,-zve32f,-zve32x,-zve64d,-zve64f,-zve64x,-zvfh,-zvfhmin,-zvkb,-zvkg,-zvkn,-zvknc,-zvkned,-zvkng,-zvknha,-zvknhb,-zvks,-zvksc,-zvksed,-zvksg,-zvksh,-zvkt,-zvl1024b,-zvl128b,-zvl16384b,-zvl2048b,-zvl256b,-zvl32768b,-zvl32b,-zvl4096b,-zvl512b,-zvl64b,-zvl65536b,-zvl8192b" }

!llvm.module.flags = !{!0, !1, !2}
!llvm.ident = !{!3}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 1, !"target-abi", !"ilp32"}
!2 = !{i32 8, !"SmallDataLimit", i32 8}
!3 = !{!"clang version 18.1.0rc (https://github.com/llvm/llvm-project.git 1acc4e456481e76822c76c850bad3994d4e04b59)"}
!4 = !{!5, !5, i64 0}
!5 = !{!"int", !6, i64 0}
!6 = !{!"omnipotent char", !7, i64 0}
!7 = !{!"Simple C/C++ TBAA"}
; *** IR Dump Before AssignmentTrackingPass on [module] ***
; ModuleID = 'cecil_test.c'
source_filename = "cecil_test.c"
target datalayout = "e-m:e-p:32:32-i64:64-n32-S128"
target triple = "riscv32-unknown-unknown"

; Function Attrs: nounwind
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) #0 {
entry:
  %acc.addr = alloca i32, align 4
  %x.addr = alloca i32, align 4
  %y.addr = alloca i32, align 4
  store i32 %acc, ptr %acc.addr, align 4, !tbaa !4
  store i32 %x, ptr %x.addr, align 4, !tbaa !4
  store i32 %y, ptr %y.addr, align 4, !tbaa !4
  %0 = load i32, ptr %x.addr, align 4, !tbaa !4
  %and = and i32 %0, 65535
  %conv = trunc i32 %and to i16
  %conv1 = sext i16 %conv to i32
  %1 = load i32, ptr %y.addr, align 4, !tbaa !4
  %and2 = and i32 %1, 65535
  %conv3 = trunc i32 %and2 to i16
  %conv4 = sext i16 %conv3 to i32
  %mul = mul nsw i32 %conv1, %conv4
  %2 = load i32, ptr %acc.addr, align 4, !tbaa !4
  %add = add nsw i32 %2, %mul
  store i32 %add, ptr %acc.addr, align 4, !tbaa !4
  %3 = load i32, ptr %x.addr, align 4, !tbaa !4
  %shr = ashr i32 %3, 16
  %and5 = and i32 %shr, 65535
  %conv6 = trunc i32 %and5 to i16
  %conv7 = sext i16 %conv6 to i32
  %4 = load i32, ptr %y.addr, align 4, !tbaa !4
  %shr8 = ashr i32 %4, 16
  %and9 = and i32 %shr8, 65535
  %conv10 = trunc i32 %and9 to i16
  %conv11 = sext i16 %conv10 to i32
  %mul12 = mul nsw i32 %conv7, %conv11
  %5 = load i32, ptr %acc.addr, align 4, !tbaa !4
  %add13 = add nsw i32 %5, %mul12
  store i32 %add13, ptr %acc.addr, align 4, !tbaa !4
  %6 = load i32, ptr %acc.addr, align 4, !tbaa !4
  ret i32 %6
}

attributes #0 = { nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="generic-rv32" "target-features"="+32bit,+m,+relax,+xseal5testalucvabs16,+xseal5testalucvabs32,+xseal5testalucvabs8,+xseal5testalucvaddnrsi16,+xseal5testalucvaddnrsi32,+xseal5testalucvaddnrui16,+xseal5testalucvaddnrui32,+xseal5testalucvaddns,+xseal5testalucvaddnu,+xseal5testalucvaddrnrsi16,+xseal5testalucvaddrnrsi32,+xseal5testalucvaddrnrui16,+xseal5testalucvaddrnrui32,+xseal5testalucvaddrns,+xseal5testalucvaddrnu,+xseal5testalucvextbs,+xseal5testalucvextbz,+xseal5testalucvexths,+xseal5testalucvexthz,+xseal5testalucvmaxi1216,+xseal5testalucvmaxi1232,+xseal5testalucvmaxi516,+xseal5testalucvmaxi532,+xseal5testalucvmaxs16,+xseal5testalucvmaxs32,+xseal5testalucvmaxs8,+xseal5testalucvmaxu16,+xseal5testalucvmaxu32,+xseal5testalucvmaxu8,+xseal5testalucvmini1216,+xseal5testalucvmini1232,+xseal5testalucvmini516,+xseal5testalucvmini532,+xseal5testalucvmins16,+xseal5testalucvmins32,+xseal5testalucvmins8,+xseal5testalucvminu16,+xseal5testalucvminu32,+xseal5testalucvminu8,+xseal5testalucvsletsi16,+xseal5testalucvsletsi32,+xseal5testalucvsletui16,+xseal5testalucvsletui32,+xseal5testalucvsubnrsi16,+xseal5testalucvsubnrsi32,+xseal5testalucvsubnrui16,+xseal5testalucvsubnrui32,+xseal5testalucvsubns,+xseal5testalucvsubnu,+xseal5testalucvsubrnrsi16,+xseal5testalucvsubrnrsi32,+xseal5testalucvsubrnrui16,+xseal5testalucvsubrnrui32,+xseal5testalucvsubrns,+xseal5testalucvsubrnu,+xseal5testmaccvmachhns,+xseal5testmaccvmachhnu,+xseal5testmaccvmachhrns,+xseal5testmaccvmachhrnu,+xseal5testmaccvmacns,+xseal5testmaccvmacnu,+xseal5testmaccvmacrns,+xseal5testmaccvmacrnu,+xseal5testmaccvmacsi16,+xseal5testmaccvmacsi32,+xseal5testmaccvmacui16,+xseal5testmaccvmacui32,+xseal5testmaccvmsusi16,+xseal5testmaccvmsusi32,+xseal5testmaccvmsuui16,+xseal5testmaccvmsuui32,+xseal5testmaccvmulhhns,+xseal5testmaccvmulhhnu,+xseal5testmaccvmulhhrns,+xseal5testmaccvmulhhrnu,+xseal5testmaccvmulns,+xseal5testmaccvmulnu,+xseal5testmaccvmulrns,+xseal5testmaccvmulrnu,-a,-c,-d,-e,-experimental-zacas,-experimental-zcmop,-experimental-zfbfmin,-experimental-zicfilp,-experimental-zicfiss,-experimental-zimop,-experimental-ztso,-experimental-zvfbfmin,-experimental-zvfbfwma,-f,-h,-smaia,-smepmp,-ssaia,-svinval,-svnapot,-svpbmt,-v,-xcvalu,-xcvbi,-xcvbitmanip,-xcvelw,-xcvmac,-xcvmem,-xcvsimd,-xsfvcp,-xsfvfnrclipxfqf,-xsfvfwmaccqqq,-xsfvqmaccdod,-xsfvqmaccqoq,-xtheadba,-xtheadbb,-xtheadbs,-xtheadcmo,-xtheadcondmov,-xtheadfmemidx,-xtheadmac,-xtheadmemidx,-xtheadmempair,-xtheadsync,-xtheadvdot,-xventanacondops,-za128rs,-za64rs,-zawrs,-zba,-zbb,-zbc,-zbkb,-zbkc,-zbkx,-zbs,-zca,-zcb,-zcd,-zce,-zcf,-zcmp,-zcmt,-zdinx,-zfa,-zfh,-zfhmin,-zfinx,-zhinx,-zhinxmin,-zic64b,-zicbom,-zicbop,-zicboz,-ziccamoa,-ziccif,-zicclsm,-ziccrse,-zicntr,-zicond,-zicsr,-zifencei,-zihintntl,-zihintpause,-zihpm,-zk,-zkn,-zknd,-zkne,-zknh,-zkr,-zks,-zksed,-zksh,-zkt,-zmmul,-zvbb,-zvbc,-zve32f,-zve32x,-zve64d,-zve64f,-zve64x,-zvfh,-zvfhmin,-zvkb,-zvkg,-zvkn,-zvknc,-zvkned,-zvkng,-zvknha,-zvknhb,-zvks,-zvksc,-zvksed,-zvksg,-zvksh,-zvkt,-zvl1024b,-zvl128b,-zvl16384b,-zvl2048b,-zvl256b,-zvl32768b,-zvl32b,-zvl4096b,-zvl512b,-zvl64b,-zvl65536b,-zvl8192b" }

!llvm.module.flags = !{!0, !1, !2}
!llvm.ident = !{!3}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 1, !"target-abi", !"ilp32"}
!2 = !{i32 8, !"SmallDataLimit", i32 8}
!3 = !{!"clang version 18.1.0rc (https://github.com/llvm/llvm-project.git 1acc4e456481e76822c76c850bad3994d4e04b59)"}
!4 = !{!5, !5, i64 0}
!5 = !{!"int", !6, i64 0}
!6 = !{!"omnipotent char", !7, i64 0}
!7 = !{!"Simple C/C++ TBAA"}
; *** IR Dump After AssignmentTrackingPass on [module] ***
; ModuleID = 'cecil_test.c'
source_filename = "cecil_test.c"
target datalayout = "e-m:e-p:32:32-i64:64-n32-S128"
target triple = "riscv32-unknown-unknown"

; Function Attrs: nounwind
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) #0 {
entry:
  %acc.addr = alloca i32, align 4
  %x.addr = alloca i32, align 4
  %y.addr = alloca i32, align 4
  store i32 %acc, ptr %acc.addr, align 4, !tbaa !4
  store i32 %x, ptr %x.addr, align 4, !tbaa !4
  store i32 %y, ptr %y.addr, align 4, !tbaa !4
  %0 = load i32, ptr %x.addr, align 4, !tbaa !4
  %and = and i32 %0, 65535
  %conv = trunc i32 %and to i16
  %conv1 = sext i16 %conv to i32
  %1 = load i32, ptr %y.addr, align 4, !tbaa !4
  %and2 = and i32 %1, 65535
  %conv3 = trunc i32 %and2 to i16
  %conv4 = sext i16 %conv3 to i32
  %mul = mul nsw i32 %conv1, %conv4
  %2 = load i32, ptr %acc.addr, align 4, !tbaa !4
  %add = add nsw i32 %2, %mul
  store i32 %add, ptr %acc.addr, align 4, !tbaa !4
  %3 = load i32, ptr %x.addr, align 4, !tbaa !4
  %shr = ashr i32 %3, 16
  %and5 = and i32 %shr, 65535
  %conv6 = trunc i32 %and5 to i16
  %conv7 = sext i16 %conv6 to i32
  %4 = load i32, ptr %y.addr, align 4, !tbaa !4
  %shr8 = ashr i32 %4, 16
  %and9 = and i32 %shr8, 65535
  %conv10 = trunc i32 %and9 to i16
  %conv11 = sext i16 %conv10 to i32
  %mul12 = mul nsw i32 %conv7, %conv11
  %5 = load i32, ptr %acc.addr, align 4, !tbaa !4
  %add13 = add nsw i32 %5, %mul12
  store i32 %add13, ptr %acc.addr, align 4, !tbaa !4
  %6 = load i32, ptr %acc.addr, align 4, !tbaa !4
  ret i32 %6
}

attributes #0 = { nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="generic-rv32" "target-features"="+32bit,+m,+relax,+xseal5testalucvabs16,+xseal5testalucvabs32,+xseal5testalucvabs8,+xseal5testalucvaddnrsi16,+xseal5testalucvaddnrsi32,+xseal5testalucvaddnrui16,+xseal5testalucvaddnrui32,+xseal5testalucvaddns,+xseal5testalucvaddnu,+xseal5testalucvaddrnrsi16,+xseal5testalucvaddrnrsi32,+xseal5testalucvaddrnrui16,+xseal5testalucvaddrnrui32,+xseal5testalucvaddrns,+xseal5testalucvaddrnu,+xseal5testalucvextbs,+xseal5testalucvextbz,+xseal5testalucvexths,+xseal5testalucvexthz,+xseal5testalucvmaxi1216,+xseal5testalucvmaxi1232,+xseal5testalucvmaxi516,+xseal5testalucvmaxi532,+xseal5testalucvmaxs16,+xseal5testalucvmaxs32,+xseal5testalucvmaxs8,+xseal5testalucvmaxu16,+xseal5testalucvmaxu32,+xseal5testalucvmaxu8,+xseal5testalucvmini1216,+xseal5testalucvmini1232,+xseal5testalucvmini516,+xseal5testalucvmini532,+xseal5testalucvmins16,+xseal5testalucvmins32,+xseal5testalucvmins8,+xseal5testalucvminu16,+xseal5testalucvminu32,+xseal5testalucvminu8,+xseal5testalucvsletsi16,+xseal5testalucvsletsi32,+xseal5testalucvsletui16,+xseal5testalucvsletui32,+xseal5testalucvsubnrsi16,+xseal5testalucvsubnrsi32,+xseal5testalucvsubnrui16,+xseal5testalucvsubnrui32,+xseal5testalucvsubns,+xseal5testalucvsubnu,+xseal5testalucvsubrnrsi16,+xseal5testalucvsubrnrsi32,+xseal5testalucvsubrnrui16,+xseal5testalucvsubrnrui32,+xseal5testalucvsubrns,+xseal5testalucvsubrnu,+xseal5testmaccvmachhns,+xseal5testmaccvmachhnu,+xseal5testmaccvmachhrns,+xseal5testmaccvmachhrnu,+xseal5testmaccvmacns,+xseal5testmaccvmacnu,+xseal5testmaccvmacrns,+xseal5testmaccvmacrnu,+xseal5testmaccvmacsi16,+xseal5testmaccvmacsi32,+xseal5testmaccvmacui16,+xseal5testmaccvmacui32,+xseal5testmaccvmsusi16,+xseal5testmaccvmsusi32,+xseal5testmaccvmsuui16,+xseal5testmaccvmsuui32,+xseal5testmaccvmulhhns,+xseal5testmaccvmulhhnu,+xseal5testmaccvmulhhrns,+xseal5testmaccvmulhhrnu,+xseal5testmaccvmulns,+xseal5testmaccvmulnu,+xseal5testmaccvmulrns,+xseal5testmaccvmulrnu,-a,-c,-d,-e,-experimental-zacas,-experimental-zcmop,-experimental-zfbfmin,-experimental-zicfilp,-experimental-zicfiss,-experimental-zimop,-experimental-ztso,-experimental-zvfbfmin,-experimental-zvfbfwma,-f,-h,-smaia,-smepmp,-ssaia,-svinval,-svnapot,-svpbmt,-v,-xcvalu,-xcvbi,-xcvbitmanip,-xcvelw,-xcvmac,-xcvmem,-xcvsimd,-xsfvcp,-xsfvfnrclipxfqf,-xsfvfwmaccqqq,-xsfvqmaccdod,-xsfvqmaccqoq,-xtheadba,-xtheadbb,-xtheadbs,-xtheadcmo,-xtheadcondmov,-xtheadfmemidx,-xtheadmac,-xtheadmemidx,-xtheadmempair,-xtheadsync,-xtheadvdot,-xventanacondops,-za128rs,-za64rs,-zawrs,-zba,-zbb,-zbc,-zbkb,-zbkc,-zbkx,-zbs,-zca,-zcb,-zcd,-zce,-zcf,-zcmp,-zcmt,-zdinx,-zfa,-zfh,-zfhmin,-zfinx,-zhinx,-zhinxmin,-zic64b,-zicbom,-zicbop,-zicboz,-ziccamoa,-ziccif,-zicclsm,-ziccrse,-zicntr,-zicond,-zicsr,-zifencei,-zihintntl,-zihintpause,-zihpm,-zk,-zkn,-zknd,-zkne,-zknh,-zkr,-zks,-zksed,-zksh,-zkt,-zmmul,-zvbb,-zvbc,-zve32f,-zve32x,-zve64d,-zve64f,-zve64x,-zvfh,-zvfhmin,-zvkb,-zvkg,-zvkn,-zvknc,-zvkned,-zvkng,-zvknha,-zvknhb,-zvks,-zvksc,-zvksed,-zvksg,-zvksh,-zvkt,-zvl1024b,-zvl128b,-zvl16384b,-zvl2048b,-zvl256b,-zvl32768b,-zvl32b,-zvl4096b,-zvl512b,-zvl64b,-zvl65536b,-zvl8192b" }

!llvm.module.flags = !{!0, !1, !2}
!llvm.ident = !{!3}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 1, !"target-abi", !"ilp32"}
!2 = !{i32 8, !"SmallDataLimit", i32 8}
!3 = !{!"clang version 18.1.0rc (https://github.com/llvm/llvm-project.git 1acc4e456481e76822c76c850bad3994d4e04b59)"}
!4 = !{!5, !5, i64 0}
!5 = !{!"int", !6, i64 0}
!6 = !{!"omnipotent char", !7, i64 0}
!7 = !{!"Simple C/C++ TBAA"}
; *** IR Dump Before InferFunctionAttrsPass on [module] ***
; ModuleID = 'cecil_test.c'
source_filename = "cecil_test.c"
target datalayout = "e-m:e-p:32:32-i64:64-n32-S128"
target triple = "riscv32-unknown-unknown"

; Function Attrs: nounwind
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) #0 {
entry:
  %acc.addr = alloca i32, align 4
  %x.addr = alloca i32, align 4
  %y.addr = alloca i32, align 4
  store i32 %acc, ptr %acc.addr, align 4, !tbaa !4
  store i32 %x, ptr %x.addr, align 4, !tbaa !4
  store i32 %y, ptr %y.addr, align 4, !tbaa !4
  %0 = load i32, ptr %x.addr, align 4, !tbaa !4
  %and = and i32 %0, 65535
  %conv = trunc i32 %and to i16
  %conv1 = sext i16 %conv to i32
  %1 = load i32, ptr %y.addr, align 4, !tbaa !4
  %and2 = and i32 %1, 65535
  %conv3 = trunc i32 %and2 to i16
  %conv4 = sext i16 %conv3 to i32
  %mul = mul nsw i32 %conv1, %conv4
  %2 = load i32, ptr %acc.addr, align 4, !tbaa !4
  %add = add nsw i32 %2, %mul
  store i32 %add, ptr %acc.addr, align 4, !tbaa !4
  %3 = load i32, ptr %x.addr, align 4, !tbaa !4
  %shr = ashr i32 %3, 16
  %and5 = and i32 %shr, 65535
  %conv6 = trunc i32 %and5 to i16
  %conv7 = sext i16 %conv6 to i32
  %4 = load i32, ptr %y.addr, align 4, !tbaa !4
  %shr8 = ashr i32 %4, 16
  %and9 = and i32 %shr8, 65535
  %conv10 = trunc i32 %and9 to i16
  %conv11 = sext i16 %conv10 to i32
  %mul12 = mul nsw i32 %conv7, %conv11
  %5 = load i32, ptr %acc.addr, align 4, !tbaa !4
  %add13 = add nsw i32 %5, %mul12
  store i32 %add13, ptr %acc.addr, align 4, !tbaa !4
  %6 = load i32, ptr %acc.addr, align 4, !tbaa !4
  ret i32 %6
}

attributes #0 = { nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="generic-rv32" "target-features"="+32bit,+m,+relax,+xseal5testalucvabs16,+xseal5testalucvabs32,+xseal5testalucvabs8,+xseal5testalucvaddnrsi16,+xseal5testalucvaddnrsi32,+xseal5testalucvaddnrui16,+xseal5testalucvaddnrui32,+xseal5testalucvaddns,+xseal5testalucvaddnu,+xseal5testalucvaddrnrsi16,+xseal5testalucvaddrnrsi32,+xseal5testalucvaddrnrui16,+xseal5testalucvaddrnrui32,+xseal5testalucvaddrns,+xseal5testalucvaddrnu,+xseal5testalucvextbs,+xseal5testalucvextbz,+xseal5testalucvexths,+xseal5testalucvexthz,+xseal5testalucvmaxi1216,+xseal5testalucvmaxi1232,+xseal5testalucvmaxi516,+xseal5testalucvmaxi532,+xseal5testalucvmaxs16,+xseal5testalucvmaxs32,+xseal5testalucvmaxs8,+xseal5testalucvmaxu16,+xseal5testalucvmaxu32,+xseal5testalucvmaxu8,+xseal5testalucvmini1216,+xseal5testalucvmini1232,+xseal5testalucvmini516,+xseal5testalucvmini532,+xseal5testalucvmins16,+xseal5testalucvmins32,+xseal5testalucvmins8,+xseal5testalucvminu16,+xseal5testalucvminu32,+xseal5testalucvminu8,+xseal5testalucvsletsi16,+xseal5testalucvsletsi32,+xseal5testalucvsletui16,+xseal5testalucvsletui32,+xseal5testalucvsubnrsi16,+xseal5testalucvsubnrsi32,+xseal5testalucvsubnrui16,+xseal5testalucvsubnrui32,+xseal5testalucvsubns,+xseal5testalucvsubnu,+xseal5testalucvsubrnrsi16,+xseal5testalucvsubrnrsi32,+xseal5testalucvsubrnrui16,+xseal5testalucvsubrnrui32,+xseal5testalucvsubrns,+xseal5testalucvsubrnu,+xseal5testmaccvmachhns,+xseal5testmaccvmachhnu,+xseal5testmaccvmachhrns,+xseal5testmaccvmachhrnu,+xseal5testmaccvmacns,+xseal5testmaccvmacnu,+xseal5testmaccvmacrns,+xseal5testmaccvmacrnu,+xseal5testmaccvmacsi16,+xseal5testmaccvmacsi32,+xseal5testmaccvmacui16,+xseal5testmaccvmacui32,+xseal5testmaccvmsusi16,+xseal5testmaccvmsusi32,+xseal5testmaccvmsuui16,+xseal5testmaccvmsuui32,+xseal5testmaccvmulhhns,+xseal5testmaccvmulhhnu,+xseal5testmaccvmulhhrns,+xseal5testmaccvmulhhrnu,+xseal5testmaccvmulns,+xseal5testmaccvmulnu,+xseal5testmaccvmulrns,+xseal5testmaccvmulrnu,-a,-c,-d,-e,-experimental-zacas,-experimental-zcmop,-experimental-zfbfmin,-experimental-zicfilp,-experimental-zicfiss,-experimental-zimop,-experimental-ztso,-experimental-zvfbfmin,-experimental-zvfbfwma,-f,-h,-smaia,-smepmp,-ssaia,-svinval,-svnapot,-svpbmt,-v,-xcvalu,-xcvbi,-xcvbitmanip,-xcvelw,-xcvmac,-xcvmem,-xcvsimd,-xsfvcp,-xsfvfnrclipxfqf,-xsfvfwmaccqqq,-xsfvqmaccdod,-xsfvqmaccqoq,-xtheadba,-xtheadbb,-xtheadbs,-xtheadcmo,-xtheadcondmov,-xtheadfmemidx,-xtheadmac,-xtheadmemidx,-xtheadmempair,-xtheadsync,-xtheadvdot,-xventanacondops,-za128rs,-za64rs,-zawrs,-zba,-zbb,-zbc,-zbkb,-zbkc,-zbkx,-zbs,-zca,-zcb,-zcd,-zce,-zcf,-zcmp,-zcmt,-zdinx,-zfa,-zfh,-zfhmin,-zfinx,-zhinx,-zhinxmin,-zic64b,-zicbom,-zicbop,-zicboz,-ziccamoa,-ziccif,-zicclsm,-ziccrse,-zicntr,-zicond,-zicsr,-zifencei,-zihintntl,-zihintpause,-zihpm,-zk,-zkn,-zknd,-zkne,-zknh,-zkr,-zks,-zksed,-zksh,-zkt,-zmmul,-zvbb,-zvbc,-zve32f,-zve32x,-zve64d,-zve64f,-zve64x,-zvfh,-zvfhmin,-zvkb,-zvkg,-zvkn,-zvknc,-zvkned,-zvkng,-zvknha,-zvknhb,-zvks,-zvksc,-zvksed,-zvksg,-zvksh,-zvkt,-zvl1024b,-zvl128b,-zvl16384b,-zvl2048b,-zvl256b,-zvl32768b,-zvl32b,-zvl4096b,-zvl512b,-zvl64b,-zvl65536b,-zvl8192b" }

!llvm.module.flags = !{!0, !1, !2}
!llvm.ident = !{!3}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 1, !"target-abi", !"ilp32"}
!2 = !{i32 8, !"SmallDataLimit", i32 8}
!3 = !{!"clang version 18.1.0rc (https://github.com/llvm/llvm-project.git 1acc4e456481e76822c76c850bad3994d4e04b59)"}
!4 = !{!5, !5, i64 0}
!5 = !{!"int", !6, i64 0}
!6 = !{!"omnipotent char", !7, i64 0}
!7 = !{!"Simple C/C++ TBAA"}
; *** IR Dump After InferFunctionAttrsPass on [module] ***
; ModuleID = 'cecil_test.c'
source_filename = "cecil_test.c"
target datalayout = "e-m:e-p:32:32-i64:64-n32-S128"
target triple = "riscv32-unknown-unknown"

; Function Attrs: nounwind
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) #0 {
entry:
  %acc.addr = alloca i32, align 4
  %x.addr = alloca i32, align 4
  %y.addr = alloca i32, align 4
  store i32 %acc, ptr %acc.addr, align 4, !tbaa !4
  store i32 %x, ptr %x.addr, align 4, !tbaa !4
  store i32 %y, ptr %y.addr, align 4, !tbaa !4
  %0 = load i32, ptr %x.addr, align 4, !tbaa !4
  %and = and i32 %0, 65535
  %conv = trunc i32 %and to i16
  %conv1 = sext i16 %conv to i32
  %1 = load i32, ptr %y.addr, align 4, !tbaa !4
  %and2 = and i32 %1, 65535
  %conv3 = trunc i32 %and2 to i16
  %conv4 = sext i16 %conv3 to i32
  %mul = mul nsw i32 %conv1, %conv4
  %2 = load i32, ptr %acc.addr, align 4, !tbaa !4
  %add = add nsw i32 %2, %mul
  store i32 %add, ptr %acc.addr, align 4, !tbaa !4
  %3 = load i32, ptr %x.addr, align 4, !tbaa !4
  %shr = ashr i32 %3, 16
  %and5 = and i32 %shr, 65535
  %conv6 = trunc i32 %and5 to i16
  %conv7 = sext i16 %conv6 to i32
  %4 = load i32, ptr %y.addr, align 4, !tbaa !4
  %shr8 = ashr i32 %4, 16
  %and9 = and i32 %shr8, 65535
  %conv10 = trunc i32 %and9 to i16
  %conv11 = sext i16 %conv10 to i32
  %mul12 = mul nsw i32 %conv7, %conv11
  %5 = load i32, ptr %acc.addr, align 4, !tbaa !4
  %add13 = add nsw i32 %5, %mul12
  store i32 %add13, ptr %acc.addr, align 4, !tbaa !4
  %6 = load i32, ptr %acc.addr, align 4, !tbaa !4
  ret i32 %6
}

attributes #0 = { nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="generic-rv32" "target-features"="+32bit,+m,+relax,+xseal5testalucvabs16,+xseal5testalucvabs32,+xseal5testalucvabs8,+xseal5testalucvaddnrsi16,+xseal5testalucvaddnrsi32,+xseal5testalucvaddnrui16,+xseal5testalucvaddnrui32,+xseal5testalucvaddns,+xseal5testalucvaddnu,+xseal5testalucvaddrnrsi16,+xseal5testalucvaddrnrsi32,+xseal5testalucvaddrnrui16,+xseal5testalucvaddrnrui32,+xseal5testalucvaddrns,+xseal5testalucvaddrnu,+xseal5testalucvextbs,+xseal5testalucvextbz,+xseal5testalucvexths,+xseal5testalucvexthz,+xseal5testalucvmaxi1216,+xseal5testalucvmaxi1232,+xseal5testalucvmaxi516,+xseal5testalucvmaxi532,+xseal5testalucvmaxs16,+xseal5testalucvmaxs32,+xseal5testalucvmaxs8,+xseal5testalucvmaxu16,+xseal5testalucvmaxu32,+xseal5testalucvmaxu8,+xseal5testalucvmini1216,+xseal5testalucvmini1232,+xseal5testalucvmini516,+xseal5testalucvmini532,+xseal5testalucvmins16,+xseal5testalucvmins32,+xseal5testalucvmins8,+xseal5testalucvminu16,+xseal5testalucvminu32,+xseal5testalucvminu8,+xseal5testalucvsletsi16,+xseal5testalucvsletsi32,+xseal5testalucvsletui16,+xseal5testalucvsletui32,+xseal5testalucvsubnrsi16,+xseal5testalucvsubnrsi32,+xseal5testalucvsubnrui16,+xseal5testalucvsubnrui32,+xseal5testalucvsubns,+xseal5testalucvsubnu,+xseal5testalucvsubrnrsi16,+xseal5testalucvsubrnrsi32,+xseal5testalucvsubrnrui16,+xseal5testalucvsubrnrui32,+xseal5testalucvsubrns,+xseal5testalucvsubrnu,+xseal5testmaccvmachhns,+xseal5testmaccvmachhnu,+xseal5testmaccvmachhrns,+xseal5testmaccvmachhrnu,+xseal5testmaccvmacns,+xseal5testmaccvmacnu,+xseal5testmaccvmacrns,+xseal5testmaccvmacrnu,+xseal5testmaccvmacsi16,+xseal5testmaccvmacsi32,+xseal5testmaccvmacui16,+xseal5testmaccvmacui32,+xseal5testmaccvmsusi16,+xseal5testmaccvmsusi32,+xseal5testmaccvmsuui16,+xseal5testmaccvmsuui32,+xseal5testmaccvmulhhns,+xseal5testmaccvmulhhnu,+xseal5testmaccvmulhhrns,+xseal5testmaccvmulhhrnu,+xseal5testmaccvmulns,+xseal5testmaccvmulnu,+xseal5testmaccvmulrns,+xseal5testmaccvmulrnu,-a,-c,-d,-e,-experimental-zacas,-experimental-zcmop,-experimental-zfbfmin,-experimental-zicfilp,-experimental-zicfiss,-experimental-zimop,-experimental-ztso,-experimental-zvfbfmin,-experimental-zvfbfwma,-f,-h,-smaia,-smepmp,-ssaia,-svinval,-svnapot,-svpbmt,-v,-xcvalu,-xcvbi,-xcvbitmanip,-xcvelw,-xcvmac,-xcvmem,-xcvsimd,-xsfvcp,-xsfvfnrclipxfqf,-xsfvfwmaccqqq,-xsfvqmaccdod,-xsfvqmaccqoq,-xtheadba,-xtheadbb,-xtheadbs,-xtheadcmo,-xtheadcondmov,-xtheadfmemidx,-xtheadmac,-xtheadmemidx,-xtheadmempair,-xtheadsync,-xtheadvdot,-xventanacondops,-za128rs,-za64rs,-zawrs,-zba,-zbb,-zbc,-zbkb,-zbkc,-zbkx,-zbs,-zca,-zcb,-zcd,-zce,-zcf,-zcmp,-zcmt,-zdinx,-zfa,-zfh,-zfhmin,-zfinx,-zhinx,-zhinxmin,-zic64b,-zicbom,-zicbop,-zicboz,-ziccamoa,-ziccif,-zicclsm,-ziccrse,-zicntr,-zicond,-zicsr,-zifencei,-zihintntl,-zihintpause,-zihpm,-zk,-zkn,-zknd,-zkne,-zknh,-zkr,-zks,-zksed,-zksh,-zkt,-zmmul,-zvbb,-zvbc,-zve32f,-zve32x,-zve64d,-zve64f,-zve64x,-zvfh,-zvfhmin,-zvkb,-zvkg,-zvkn,-zvknc,-zvkned,-zvkng,-zvknha,-zvknhb,-zvks,-zvksc,-zvksed,-zvksg,-zvksh,-zvkt,-zvl1024b,-zvl128b,-zvl16384b,-zvl2048b,-zvl256b,-zvl32768b,-zvl32b,-zvl4096b,-zvl512b,-zvl64b,-zvl65536b,-zvl8192b" }

!llvm.module.flags = !{!0, !1, !2}
!llvm.ident = !{!3}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 1, !"target-abi", !"ilp32"}
!2 = !{i32 8, !"SmallDataLimit", i32 8}
!3 = !{!"clang version 18.1.0rc (https://github.com/llvm/llvm-project.git 1acc4e456481e76822c76c850bad3994d4e04b59)"}
!4 = !{!5, !5, i64 0}
!5 = !{!"int", !6, i64 0}
!6 = !{!"omnipotent char", !7, i64 0}
!7 = !{!"Simple C/C++ TBAA"}
; *** IR Dump Before CoroEarlyPass on [module] ***
; ModuleID = 'cecil_test.c'
source_filename = "cecil_test.c"
target datalayout = "e-m:e-p:32:32-i64:64-n32-S128"
target triple = "riscv32-unknown-unknown"

; Function Attrs: nounwind
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) #0 {
entry:
  %acc.addr = alloca i32, align 4
  %x.addr = alloca i32, align 4
  %y.addr = alloca i32, align 4
  store i32 %acc, ptr %acc.addr, align 4, !tbaa !4
  store i32 %x, ptr %x.addr, align 4, !tbaa !4
  store i32 %y, ptr %y.addr, align 4, !tbaa !4
  %0 = load i32, ptr %x.addr, align 4, !tbaa !4
  %and = and i32 %0, 65535
  %conv = trunc i32 %and to i16
  %conv1 = sext i16 %conv to i32
  %1 = load i32, ptr %y.addr, align 4, !tbaa !4
  %and2 = and i32 %1, 65535
  %conv3 = trunc i32 %and2 to i16
  %conv4 = sext i16 %conv3 to i32
  %mul = mul nsw i32 %conv1, %conv4
  %2 = load i32, ptr %acc.addr, align 4, !tbaa !4
  %add = add nsw i32 %2, %mul
  store i32 %add, ptr %acc.addr, align 4, !tbaa !4
  %3 = load i32, ptr %x.addr, align 4, !tbaa !4
  %shr = ashr i32 %3, 16
  %and5 = and i32 %shr, 65535
  %conv6 = trunc i32 %and5 to i16
  %conv7 = sext i16 %conv6 to i32
  %4 = load i32, ptr %y.addr, align 4, !tbaa !4
  %shr8 = ashr i32 %4, 16
  %and9 = and i32 %shr8, 65535
  %conv10 = trunc i32 %and9 to i16
  %conv11 = sext i16 %conv10 to i32
  %mul12 = mul nsw i32 %conv7, %conv11
  %5 = load i32, ptr %acc.addr, align 4, !tbaa !4
  %add13 = add nsw i32 %5, %mul12
  store i32 %add13, ptr %acc.addr, align 4, !tbaa !4
  %6 = load i32, ptr %acc.addr, align 4, !tbaa !4
  ret i32 %6
}

attributes #0 = { nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="generic-rv32" "target-features"="+32bit,+m,+relax,+xseal5testalucvabs16,+xseal5testalucvabs32,+xseal5testalucvabs8,+xseal5testalucvaddnrsi16,+xseal5testalucvaddnrsi32,+xseal5testalucvaddnrui16,+xseal5testalucvaddnrui32,+xseal5testalucvaddns,+xseal5testalucvaddnu,+xseal5testalucvaddrnrsi16,+xseal5testalucvaddrnrsi32,+xseal5testalucvaddrnrui16,+xseal5testalucvaddrnrui32,+xseal5testalucvaddrns,+xseal5testalucvaddrnu,+xseal5testalucvextbs,+xseal5testalucvextbz,+xseal5testalucvexths,+xseal5testalucvexthz,+xseal5testalucvmaxi1216,+xseal5testalucvmaxi1232,+xseal5testalucvmaxi516,+xseal5testalucvmaxi532,+xseal5testalucvmaxs16,+xseal5testalucvmaxs32,+xseal5testalucvmaxs8,+xseal5testalucvmaxu16,+xseal5testalucvmaxu32,+xseal5testalucvmaxu8,+xseal5testalucvmini1216,+xseal5testalucvmini1232,+xseal5testalucvmini516,+xseal5testalucvmini532,+xseal5testalucvmins16,+xseal5testalucvmins32,+xseal5testalucvmins8,+xseal5testalucvminu16,+xseal5testalucvminu32,+xseal5testalucvminu8,+xseal5testalucvsletsi16,+xseal5testalucvsletsi32,+xseal5testalucvsletui16,+xseal5testalucvsletui32,+xseal5testalucvsubnrsi16,+xseal5testalucvsubnrsi32,+xseal5testalucvsubnrui16,+xseal5testalucvsubnrui32,+xseal5testalucvsubns,+xseal5testalucvsubnu,+xseal5testalucvsubrnrsi16,+xseal5testalucvsubrnrsi32,+xseal5testalucvsubrnrui16,+xseal5testalucvsubrnrui32,+xseal5testalucvsubrns,+xseal5testalucvsubrnu,+xseal5testmaccvmachhns,+xseal5testmaccvmachhnu,+xseal5testmaccvmachhrns,+xseal5testmaccvmachhrnu,+xseal5testmaccvmacns,+xseal5testmaccvmacnu,+xseal5testmaccvmacrns,+xseal5testmaccvmacrnu,+xseal5testmaccvmacsi16,+xseal5testmaccvmacsi32,+xseal5testmaccvmacui16,+xseal5testmaccvmacui32,+xseal5testmaccvmsusi16,+xseal5testmaccvmsusi32,+xseal5testmaccvmsuui16,+xseal5testmaccvmsuui32,+xseal5testmaccvmulhhns,+xseal5testmaccvmulhhnu,+xseal5testmaccvmulhhrns,+xseal5testmaccvmulhhrnu,+xseal5testmaccvmulns,+xseal5testmaccvmulnu,+xseal5testmaccvmulrns,+xseal5testmaccvmulrnu,-a,-c,-d,-e,-experimental-zacas,-experimental-zcmop,-experimental-zfbfmin,-experimental-zicfilp,-experimental-zicfiss,-experimental-zimop,-experimental-ztso,-experimental-zvfbfmin,-experimental-zvfbfwma,-f,-h,-smaia,-smepmp,-ssaia,-svinval,-svnapot,-svpbmt,-v,-xcvalu,-xcvbi,-xcvbitmanip,-xcvelw,-xcvmac,-xcvmem,-xcvsimd,-xsfvcp,-xsfvfnrclipxfqf,-xsfvfwmaccqqq,-xsfvqmaccdod,-xsfvqmaccqoq,-xtheadba,-xtheadbb,-xtheadbs,-xtheadcmo,-xtheadcondmov,-xtheadfmemidx,-xtheadmac,-xtheadmemidx,-xtheadmempair,-xtheadsync,-xtheadvdot,-xventanacondops,-za128rs,-za64rs,-zawrs,-zba,-zbb,-zbc,-zbkb,-zbkc,-zbkx,-zbs,-zca,-zcb,-zcd,-zce,-zcf,-zcmp,-zcmt,-zdinx,-zfa,-zfh,-zfhmin,-zfinx,-zhinx,-zhinxmin,-zic64b,-zicbom,-zicbop,-zicboz,-ziccamoa,-ziccif,-zicclsm,-ziccrse,-zicntr,-zicond,-zicsr,-zifencei,-zihintntl,-zihintpause,-zihpm,-zk,-zkn,-zknd,-zkne,-zknh,-zkr,-zks,-zksed,-zksh,-zkt,-zmmul,-zvbb,-zvbc,-zve32f,-zve32x,-zve64d,-zve64f,-zve64x,-zvfh,-zvfhmin,-zvkb,-zvkg,-zvkn,-zvknc,-zvkned,-zvkng,-zvknha,-zvknhb,-zvks,-zvksc,-zvksed,-zvksg,-zvksh,-zvkt,-zvl1024b,-zvl128b,-zvl16384b,-zvl2048b,-zvl256b,-zvl32768b,-zvl32b,-zvl4096b,-zvl512b,-zvl64b,-zvl65536b,-zvl8192b" }

!llvm.module.flags = !{!0, !1, !2}
!llvm.ident = !{!3}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 1, !"target-abi", !"ilp32"}
!2 = !{i32 8, !"SmallDataLimit", i32 8}
!3 = !{!"clang version 18.1.0rc (https://github.com/llvm/llvm-project.git 1acc4e456481e76822c76c850bad3994d4e04b59)"}
!4 = !{!5, !5, i64 0}
!5 = !{!"int", !6, i64 0}
!6 = !{!"omnipotent char", !7, i64 0}
!7 = !{!"Simple C/C++ TBAA"}
; *** IR Dump After CoroEarlyPass on [module] ***
; ModuleID = 'cecil_test.c'
source_filename = "cecil_test.c"
target datalayout = "e-m:e-p:32:32-i64:64-n32-S128"
target triple = "riscv32-unknown-unknown"

; Function Attrs: nounwind
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) #0 {
entry:
  %acc.addr = alloca i32, align 4
  %x.addr = alloca i32, align 4
  %y.addr = alloca i32, align 4
  store i32 %acc, ptr %acc.addr, align 4, !tbaa !4
  store i32 %x, ptr %x.addr, align 4, !tbaa !4
  store i32 %y, ptr %y.addr, align 4, !tbaa !4
  %0 = load i32, ptr %x.addr, align 4, !tbaa !4
  %and = and i32 %0, 65535
  %conv = trunc i32 %and to i16
  %conv1 = sext i16 %conv to i32
  %1 = load i32, ptr %y.addr, align 4, !tbaa !4
  %and2 = and i32 %1, 65535
  %conv3 = trunc i32 %and2 to i16
  %conv4 = sext i16 %conv3 to i32
  %mul = mul nsw i32 %conv1, %conv4
  %2 = load i32, ptr %acc.addr, align 4, !tbaa !4
  %add = add nsw i32 %2, %mul
  store i32 %add, ptr %acc.addr, align 4, !tbaa !4
  %3 = load i32, ptr %x.addr, align 4, !tbaa !4
  %shr = ashr i32 %3, 16
  %and5 = and i32 %shr, 65535
  %conv6 = trunc i32 %and5 to i16
  %conv7 = sext i16 %conv6 to i32
  %4 = load i32, ptr %y.addr, align 4, !tbaa !4
  %shr8 = ashr i32 %4, 16
  %and9 = and i32 %shr8, 65535
  %conv10 = trunc i32 %and9 to i16
  %conv11 = sext i16 %conv10 to i32
  %mul12 = mul nsw i32 %conv7, %conv11
  %5 = load i32, ptr %acc.addr, align 4, !tbaa !4
  %add13 = add nsw i32 %5, %mul12
  store i32 %add13, ptr %acc.addr, align 4, !tbaa !4
  %6 = load i32, ptr %acc.addr, align 4, !tbaa !4
  ret i32 %6
}

attributes #0 = { nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="generic-rv32" "target-features"="+32bit,+m,+relax,+xseal5testalucvabs16,+xseal5testalucvabs32,+xseal5testalucvabs8,+xseal5testalucvaddnrsi16,+xseal5testalucvaddnrsi32,+xseal5testalucvaddnrui16,+xseal5testalucvaddnrui32,+xseal5testalucvaddns,+xseal5testalucvaddnu,+xseal5testalucvaddrnrsi16,+xseal5testalucvaddrnrsi32,+xseal5testalucvaddrnrui16,+xseal5testalucvaddrnrui32,+xseal5testalucvaddrns,+xseal5testalucvaddrnu,+xseal5testalucvextbs,+xseal5testalucvextbz,+xseal5testalucvexths,+xseal5testalucvexthz,+xseal5testalucvmaxi1216,+xseal5testalucvmaxi1232,+xseal5testalucvmaxi516,+xseal5testalucvmaxi532,+xseal5testalucvmaxs16,+xseal5testalucvmaxs32,+xseal5testalucvmaxs8,+xseal5testalucvmaxu16,+xseal5testalucvmaxu32,+xseal5testalucvmaxu8,+xseal5testalucvmini1216,+xseal5testalucvmini1232,+xseal5testalucvmini516,+xseal5testalucvmini532,+xseal5testalucvmins16,+xseal5testalucvmins32,+xseal5testalucvmins8,+xseal5testalucvminu16,+xseal5testalucvminu32,+xseal5testalucvminu8,+xseal5testalucvsletsi16,+xseal5testalucvsletsi32,+xseal5testalucvsletui16,+xseal5testalucvsletui32,+xseal5testalucvsubnrsi16,+xseal5testalucvsubnrsi32,+xseal5testalucvsubnrui16,+xseal5testalucvsubnrui32,+xseal5testalucvsubns,+xseal5testalucvsubnu,+xseal5testalucvsubrnrsi16,+xseal5testalucvsubrnrsi32,+xseal5testalucvsubrnrui16,+xseal5testalucvsubrnrui32,+xseal5testalucvsubrns,+xseal5testalucvsubrnu,+xseal5testmaccvmachhns,+xseal5testmaccvmachhnu,+xseal5testmaccvmachhrns,+xseal5testmaccvmachhrnu,+xseal5testmaccvmacns,+xseal5testmaccvmacnu,+xseal5testmaccvmacrns,+xseal5testmaccvmacrnu,+xseal5testmaccvmacsi16,+xseal5testmaccvmacsi32,+xseal5testmaccvmacui16,+xseal5testmaccvmacui32,+xseal5testmaccvmsusi16,+xseal5testmaccvmsusi32,+xseal5testmaccvmsuui16,+xseal5testmaccvmsuui32,+xseal5testmaccvmulhhns,+xseal5testmaccvmulhhnu,+xseal5testmaccvmulhhrns,+xseal5testmaccvmulhhrnu,+xseal5testmaccvmulns,+xseal5testmaccvmulnu,+xseal5testmaccvmulrns,+xseal5testmaccvmulrnu,-a,-c,-d,-e,-experimental-zacas,-experimental-zcmop,-experimental-zfbfmin,-experimental-zicfilp,-experimental-zicfiss,-experimental-zimop,-experimental-ztso,-experimental-zvfbfmin,-experimental-zvfbfwma,-f,-h,-smaia,-smepmp,-ssaia,-svinval,-svnapot,-svpbmt,-v,-xcvalu,-xcvbi,-xcvbitmanip,-xcvelw,-xcvmac,-xcvmem,-xcvsimd,-xsfvcp,-xsfvfnrclipxfqf,-xsfvfwmaccqqq,-xsfvqmaccdod,-xsfvqmaccqoq,-xtheadba,-xtheadbb,-xtheadbs,-xtheadcmo,-xtheadcondmov,-xtheadfmemidx,-xtheadmac,-xtheadmemidx,-xtheadmempair,-xtheadsync,-xtheadvdot,-xventanacondops,-za128rs,-za64rs,-zawrs,-zba,-zbb,-zbc,-zbkb,-zbkc,-zbkx,-zbs,-zca,-zcb,-zcd,-zce,-zcf,-zcmp,-zcmt,-zdinx,-zfa,-zfh,-zfhmin,-zfinx,-zhinx,-zhinxmin,-zic64b,-zicbom,-zicbop,-zicboz,-ziccamoa,-ziccif,-zicclsm,-ziccrse,-zicntr,-zicond,-zicsr,-zifencei,-zihintntl,-zihintpause,-zihpm,-zk,-zkn,-zknd,-zkne,-zknh,-zkr,-zks,-zksed,-zksh,-zkt,-zmmul,-zvbb,-zvbc,-zve32f,-zve32x,-zve64d,-zve64f,-zve64x,-zvfh,-zvfhmin,-zvkb,-zvkg,-zvkn,-zvknc,-zvkned,-zvkng,-zvknha,-zvknhb,-zvks,-zvksc,-zvksed,-zvksg,-zvksh,-zvkt,-zvl1024b,-zvl128b,-zvl16384b,-zvl2048b,-zvl256b,-zvl32768b,-zvl32b,-zvl4096b,-zvl512b,-zvl64b,-zvl65536b,-zvl8192b" }

!llvm.module.flags = !{!0, !1, !2}
!llvm.ident = !{!3}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 1, !"target-abi", !"ilp32"}
!2 = !{i32 8, !"SmallDataLimit", i32 8}
!3 = !{!"clang version 18.1.0rc (https://github.com/llvm/llvm-project.git 1acc4e456481e76822c76c850bad3994d4e04b59)"}
!4 = !{!5, !5, i64 0}
!5 = !{!"int", !6, i64 0}
!6 = !{!"omnipotent char", !7, i64 0}
!7 = !{!"Simple C/C++ TBAA"}
; *** IR Dump Before LowerExpectIntrinsicPass on test_macs32_v2i16 ***
; Function Attrs: nounwind
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) #0 {
entry:
  %acc.addr = alloca i32, align 4
  %x.addr = alloca i32, align 4
  %y.addr = alloca i32, align 4
  store i32 %acc, ptr %acc.addr, align 4, !tbaa !4
  store i32 %x, ptr %x.addr, align 4, !tbaa !4
  store i32 %y, ptr %y.addr, align 4, !tbaa !4
  %0 = load i32, ptr %x.addr, align 4, !tbaa !4
  %and = and i32 %0, 65535
  %conv = trunc i32 %and to i16
  %conv1 = sext i16 %conv to i32
  %1 = load i32, ptr %y.addr, align 4, !tbaa !4
  %and2 = and i32 %1, 65535
  %conv3 = trunc i32 %and2 to i16
  %conv4 = sext i16 %conv3 to i32
  %mul = mul nsw i32 %conv1, %conv4
  %2 = load i32, ptr %acc.addr, align 4, !tbaa !4
  %add = add nsw i32 %2, %mul
  store i32 %add, ptr %acc.addr, align 4, !tbaa !4
  %3 = load i32, ptr %x.addr, align 4, !tbaa !4
  %shr = ashr i32 %3, 16
  %and5 = and i32 %shr, 65535
  %conv6 = trunc i32 %and5 to i16
  %conv7 = sext i16 %conv6 to i32
  %4 = load i32, ptr %y.addr, align 4, !tbaa !4
  %shr8 = ashr i32 %4, 16
  %and9 = and i32 %shr8, 65535
  %conv10 = trunc i32 %and9 to i16
  %conv11 = sext i16 %conv10 to i32
  %mul12 = mul nsw i32 %conv7, %conv11
  %5 = load i32, ptr %acc.addr, align 4, !tbaa !4
  %add13 = add nsw i32 %5, %mul12
  store i32 %add13, ptr %acc.addr, align 4, !tbaa !4
  %6 = load i32, ptr %acc.addr, align 4, !tbaa !4
  ret i32 %6
}
; *** IR Dump After LowerExpectIntrinsicPass on test_macs32_v2i16 ***
; Function Attrs: nounwind
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) #0 {
entry:
  %acc.addr = alloca i32, align 4
  %x.addr = alloca i32, align 4
  %y.addr = alloca i32, align 4
  store i32 %acc, ptr %acc.addr, align 4, !tbaa !4
  store i32 %x, ptr %x.addr, align 4, !tbaa !4
  store i32 %y, ptr %y.addr, align 4, !tbaa !4
  %0 = load i32, ptr %x.addr, align 4, !tbaa !4
  %and = and i32 %0, 65535
  %conv = trunc i32 %and to i16
  %conv1 = sext i16 %conv to i32
  %1 = load i32, ptr %y.addr, align 4, !tbaa !4
  %and2 = and i32 %1, 65535
  %conv3 = trunc i32 %and2 to i16
  %conv4 = sext i16 %conv3 to i32
  %mul = mul nsw i32 %conv1, %conv4
  %2 = load i32, ptr %acc.addr, align 4, !tbaa !4
  %add = add nsw i32 %2, %mul
  store i32 %add, ptr %acc.addr, align 4, !tbaa !4
  %3 = load i32, ptr %x.addr, align 4, !tbaa !4
  %shr = ashr i32 %3, 16
  %and5 = and i32 %shr, 65535
  %conv6 = trunc i32 %and5 to i16
  %conv7 = sext i16 %conv6 to i32
  %4 = load i32, ptr %y.addr, align 4, !tbaa !4
  %shr8 = ashr i32 %4, 16
  %and9 = and i32 %shr8, 65535
  %conv10 = trunc i32 %and9 to i16
  %conv11 = sext i16 %conv10 to i32
  %mul12 = mul nsw i32 %conv7, %conv11
  %5 = load i32, ptr %acc.addr, align 4, !tbaa !4
  %add13 = add nsw i32 %5, %mul12
  store i32 %add13, ptr %acc.addr, align 4, !tbaa !4
  %6 = load i32, ptr %acc.addr, align 4, !tbaa !4
  ret i32 %6
}
; *** IR Dump Before SimplifyCFGPass on test_macs32_v2i16 ***
; Function Attrs: nounwind
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) #0 {
entry:
  %acc.addr = alloca i32, align 4
  %x.addr = alloca i32, align 4
  %y.addr = alloca i32, align 4
  store i32 %acc, ptr %acc.addr, align 4, !tbaa !4
  store i32 %x, ptr %x.addr, align 4, !tbaa !4
  store i32 %y, ptr %y.addr, align 4, !tbaa !4
  %0 = load i32, ptr %x.addr, align 4, !tbaa !4
  %and = and i32 %0, 65535
  %conv = trunc i32 %and to i16
  %conv1 = sext i16 %conv to i32
  %1 = load i32, ptr %y.addr, align 4, !tbaa !4
  %and2 = and i32 %1, 65535
  %conv3 = trunc i32 %and2 to i16
  %conv4 = sext i16 %conv3 to i32
  %mul = mul nsw i32 %conv1, %conv4
  %2 = load i32, ptr %acc.addr, align 4, !tbaa !4
  %add = add nsw i32 %2, %mul
  store i32 %add, ptr %acc.addr, align 4, !tbaa !4
  %3 = load i32, ptr %x.addr, align 4, !tbaa !4
  %shr = ashr i32 %3, 16
  %and5 = and i32 %shr, 65535
  %conv6 = trunc i32 %and5 to i16
  %conv7 = sext i16 %conv6 to i32
  %4 = load i32, ptr %y.addr, align 4, !tbaa !4
  %shr8 = ashr i32 %4, 16
  %and9 = and i32 %shr8, 65535
  %conv10 = trunc i32 %and9 to i16
  %conv11 = sext i16 %conv10 to i32
  %mul12 = mul nsw i32 %conv7, %conv11
  %5 = load i32, ptr %acc.addr, align 4, !tbaa !4
  %add13 = add nsw i32 %5, %mul12
  store i32 %add13, ptr %acc.addr, align 4, !tbaa !4
  %6 = load i32, ptr %acc.addr, align 4, !tbaa !4
  ret i32 %6
}

Features:+32bit,+m,+relax,+xseal5testalucvabs16,+xseal5testalucvabs32,+xseal5testalucvabs8,+xseal5testalucvaddnrsi16,+xseal5testalucvaddnrsi32,+xseal5testalucvaddnrui16,+xseal5testalucvaddnrui32,+xseal5testalucvaddns,+xseal5testalucvaddnu,+xseal5testalucvaddrnrsi16,+xseal5testalucvaddrnrsi32,+xseal5testalucvaddrnrui16,+xseal5testalucvaddrnrui32,+xseal5testalucvaddrns,+xseal5testalucvaddrnu,+xseal5testalucvextbs,+xseal5testalucvextbz,+xseal5testalucvexths,+xseal5testalucvexthz,+xseal5testalucvmaxi1216,+xseal5testalucvmaxi1232,+xseal5testalucvmaxi516,+xseal5testalucvmaxi532,+xseal5testalucvmaxs16,+xseal5testalucvmaxs32,+xseal5testalucvmaxs8,+xseal5testalucvmaxu16,+xseal5testalucvmaxu32,+xseal5testalucvmaxu8,+xseal5testalucvmini1216,+xseal5testalucvmini1232,+xseal5testalucvmini516,+xseal5testalucvmini532,+xseal5testalucvmins16,+xseal5testalucvmins32,+xseal5testalucvmins8,+xseal5testalucvminu16,+xseal5testalucvminu32,+xseal5testalucvminu8,+xseal5testalucvsletsi16,+xseal5testalucvsletsi32,+xseal5testalucvsletui16,+xseal5testalucvsletui32,+xseal5testalucvsubnrsi16,+xseal5testalucvsubnrsi32,+xseal5testalucvsubnrui16,+xseal5testalucvsubnrui32,+xseal5testalucvsubns,+xseal5testalucvsubnu,+xseal5testalucvsubrnrsi16,+xseal5testalucvsubrnrsi32,+xseal5testalucvsubrnrui16,+xseal5testalucvsubrnrui32,+xseal5testalucvsubrns,+xseal5testalucvsubrnu,+xseal5testmaccvmachhns,+xseal5testmaccvmachhnu,+xseal5testmaccvmachhrns,+xseal5testmaccvmachhrnu,+xseal5testmaccvmacns,+xseal5testmaccvmacnu,+xseal5testmaccvmacrns,+xseal5testmaccvmacrnu,+xseal5testmaccvmacsi16,+xseal5testmaccvmacsi32,+xseal5testmaccvmacui16,+xseal5testmaccvmacui32,+xseal5testmaccvmsusi16,+xseal5testmaccvmsusi32,+xseal5testmaccvmsuui16,+xseal5testmaccvmsuui32,+xseal5testmaccvmulhhns,+xseal5testmaccvmulhhnu,+xseal5testmaccvmulhhrns,+xseal5testmaccvmulhhrnu,+xseal5testmaccvmulns,+xseal5testmaccvmulnu,+xseal5testmaccvmulrns,+xseal5testmaccvmulrnu,-a,-c,-d,-e,-experimental-zacas,-experimental-zcmop,-experimental-zfbfmin,-experimental-zicfilp,-experimental-zicfiss,-experimental-zimop,-experimental-ztso,-experimental-zvfbfmin,-experimental-zvfbfwma,-f,-h,-smaia,-smepmp,-ssaia,-svinval,-svnapot,-svpbmt,-v,-xcvalu,-xcvbi,-xcvbitmanip,-xcvelw,-xcvmac,-xcvmem,-xcvsimd,-xsfvcp,-xsfvfnrclipxfqf,-xsfvfwmaccqqq,-xsfvqmaccdod,-xsfvqmaccqoq,-xtheadba,-xtheadbb,-xtheadbs,-xtheadcmo,-xtheadcondmov,-xtheadfmemidx,-xtheadmac,-xtheadmemidx,-xtheadmempair,-xtheadsync,-xtheadvdot,-xventanacondops,-za128rs,-za64rs,-zawrs,-zba,-zbb,-zbc,-zbkb,-zbkc,-zbkx,-zbs,-zca,-zcb,-zcd,-zce,-zcf,-zcmp,-zcmt,-zdinx,-zfa,-zfh,-zfhmin,-zfinx,-zhinx,-zhinxmin,-zic64b,-zicbom,-zicbop,-zicboz,-ziccamoa,-ziccif,-zicclsm,-ziccrse,-zicntr,-zicond,-zicsr,-zifencei,-zihintntl,-zihintpause,-zihpm,-zk,-zkn,-zknd,-zkne,-zknh,-zkr,-zks,-zksed,-zksh,-zkt,-zmmul,-zvbb,-zvbc,-zve32f,-zve32x,-zve64d,-zve64f,-zve64x,-zvfh,-zvfhmin,-zvkb,-zvkg,-zvkn,-zvknc,-zvkned,-zvkng,-zvknha,-zvknhb,-zvks,-zvksc,-zvksed,-zvksg,-zvksh,-zvkt,-zvl1024b,-zvl128b,-zvl16384b,-zvl2048b,-zvl256b,-zvl32768b,-zvl32b,-zvl4096b,-zvl512b,-zvl64b,-zvl65536b,-zvl8192b
CPU:generic-rv32
TuneCPU:generic-rv32

; *** IR Dump After SimplifyCFGPass on test_macs32_v2i16 ***
; Function Attrs: nounwind
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) #0 {
entry:
  %acc.addr = alloca i32, align 4
  %x.addr = alloca i32, align 4
  %y.addr = alloca i32, align 4
  store i32 %acc, ptr %acc.addr, align 4, !tbaa !4
  store i32 %x, ptr %x.addr, align 4, !tbaa !4
  store i32 %y, ptr %y.addr, align 4, !tbaa !4
  %0 = load i32, ptr %x.addr, align 4, !tbaa !4
  %and = and i32 %0, 65535
  %conv = trunc i32 %and to i16
  %conv1 = sext i16 %conv to i32
  %1 = load i32, ptr %y.addr, align 4, !tbaa !4
  %and2 = and i32 %1, 65535
  %conv3 = trunc i32 %and2 to i16
  %conv4 = sext i16 %conv3 to i32
  %mul = mul nsw i32 %conv1, %conv4
  %2 = load i32, ptr %acc.addr, align 4, !tbaa !4
  %add = add nsw i32 %2, %mul
  store i32 %add, ptr %acc.addr, align 4, !tbaa !4
  %3 = load i32, ptr %x.addr, align 4, !tbaa !4
  %shr = ashr i32 %3, 16
  %and5 = and i32 %shr, 65535
  %conv6 = trunc i32 %and5 to i16
  %conv7 = sext i16 %conv6 to i32
  %4 = load i32, ptr %y.addr, align 4, !tbaa !4
  %shr8 = ashr i32 %4, 16
  %and9 = and i32 %shr8, 65535
  %conv10 = trunc i32 %and9 to i16
  %conv11 = sext i16 %conv10 to i32
  %mul12 = mul nsw i32 %conv7, %conv11
  %5 = load i32, ptr %acc.addr, align 4, !tbaa !4
  %add13 = add nsw i32 %5, %mul12
  store i32 %add13, ptr %acc.addr, align 4, !tbaa !4
  %6 = load i32, ptr %acc.addr, align 4, !tbaa !4
  ret i32 %6
}
; *** IR Dump Before SROAPass on test_macs32_v2i16 ***
; Function Attrs: nounwind
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) #0 {
entry:
  %acc.addr = alloca i32, align 4
  %x.addr = alloca i32, align 4
  %y.addr = alloca i32, align 4
  store i32 %acc, ptr %acc.addr, align 4, !tbaa !4
  store i32 %x, ptr %x.addr, align 4, !tbaa !4
  store i32 %y, ptr %y.addr, align 4, !tbaa !4
  %0 = load i32, ptr %x.addr, align 4, !tbaa !4
  %and = and i32 %0, 65535
  %conv = trunc i32 %and to i16
  %conv1 = sext i16 %conv to i32
  %1 = load i32, ptr %y.addr, align 4, !tbaa !4
  %and2 = and i32 %1, 65535
  %conv3 = trunc i32 %and2 to i16
  %conv4 = sext i16 %conv3 to i32
  %mul = mul nsw i32 %conv1, %conv4
  %2 = load i32, ptr %acc.addr, align 4, !tbaa !4
  %add = add nsw i32 %2, %mul
  store i32 %add, ptr %acc.addr, align 4, !tbaa !4
  %3 = load i32, ptr %x.addr, align 4, !tbaa !4
  %shr = ashr i32 %3, 16
  %and5 = and i32 %shr, 65535
  %conv6 = trunc i32 %and5 to i16
  %conv7 = sext i16 %conv6 to i32
  %4 = load i32, ptr %y.addr, align 4, !tbaa !4
  %shr8 = ashr i32 %4, 16
  %and9 = and i32 %shr8, 65535
  %conv10 = trunc i32 %and9 to i16
  %conv11 = sext i16 %conv10 to i32
  %mul12 = mul nsw i32 %conv7, %conv11
  %5 = load i32, ptr %acc.addr, align 4, !tbaa !4
  %add13 = add nsw i32 %5, %mul12
  store i32 %add13, ptr %acc.addr, align 4, !tbaa !4
  %6 = load i32, ptr %acc.addr, align 4, !tbaa !4
  ret i32 %6
}
SROA function: test_macs32_v2i16
SROA alloca:   %y.addr = alloca i32, align 4
  Rewriting FCA loads and stores...
Slices of alloca:   %y.addr = alloca i32, align 4
  [0,4) slice #0 (splittable)
    used by:   store i32 %y, ptr %y.addr, align 4, !tbaa !4
  [0,4) slice #1 (splittable)
    used by:   %1 = load i32, ptr %y.addr, align 4, !tbaa !4
  [0,4) slice #2 (splittable)
    used by:   %4 = load i32, ptr %y.addr, align 4, !tbaa !4
Pre-splitting loads and stores
  Searching for candidate loads and stores
Rewriting alloca partition [0,4) to:   %y.addr = alloca i32, align 4
  rewriting [0,4) slice #0 (splittable)
   Begin:(0, 4) NewBegin:(0, 4) NewAllocaBegin:(0, 4)
    original:   store i32 %y, ptr %y.addr, align 4, !tbaa !4
          to:   store i32 %y, ptr %y.addr, align 4, !tbaa !4
  rewriting [0,4) slice #1 (splittable)
   Begin:(0, 4) NewBegin:(0, 4) NewAllocaBegin:(0, 4)
    original:   %1 = load i32, ptr %y.addr, align 4, !tbaa !4
          to:   %y.addr.0.load = load i32, ptr %y.addr, align 4
  rewriting [0,4) slice #2 (splittable)
   Begin:(0, 4) NewBegin:(0, 4) NewAllocaBegin:(0, 4)
    original:   %4 = load i32, ptr %y.addr, align 4, !tbaa !4
          to:   %y.addr.0.load14 = load i32, ptr %y.addr, align 4
  Speculating PHIs
  Rewriting Selects
Deleting dead instruction:   %4 = load i32, ptr %y.addr, align 4, !tbaa !4
Deleting dead instruction:   %1 = load i32, ptr %y.addr, align 4, !tbaa !4
Deleting dead instruction:   store i32 %y, ptr %y.addr, align 4, !tbaa !4
SROA alloca:   %x.addr = alloca i32, align 4
  Rewriting FCA loads and stores...
Slices of alloca:   %x.addr = alloca i32, align 4
  [0,4) slice #0 (splittable)
    used by:   store i32 %x, ptr %x.addr, align 4, !tbaa !4
  [0,4) slice #1 (splittable)
    used by:   %0 = load i32, ptr %x.addr, align 4, !tbaa !4
  [0,4) slice #2 (splittable)
    used by:   %2 = load i32, ptr %x.addr, align 4, !tbaa !4
Pre-splitting loads and stores
  Searching for candidate loads and stores
Rewriting alloca partition [0,4) to:   %x.addr = alloca i32, align 4
  rewriting [0,4) slice #0 (splittable)
   Begin:(0, 4) NewBegin:(0, 4) NewAllocaBegin:(0, 4)
    original:   store i32 %x, ptr %x.addr, align 4, !tbaa !4
          to:   store i32 %x, ptr %x.addr, align 4, !tbaa !4
  rewriting [0,4) slice #1 (splittable)
   Begin:(0, 4) NewBegin:(0, 4) NewAllocaBegin:(0, 4)
    original:   %0 = load i32, ptr %x.addr, align 4, !tbaa !4
          to:   %x.addr.0.load = load i32, ptr %x.addr, align 4
  rewriting [0,4) slice #2 (splittable)
   Begin:(0, 4) NewBegin:(0, 4) NewAllocaBegin:(0, 4)
    original:   %2 = load i32, ptr %x.addr, align 4, !tbaa !4
          to:   %x.addr.0.load15 = load i32, ptr %x.addr, align 4
  Speculating PHIs
  Rewriting Selects
Deleting dead instruction:   %2 = load i32, ptr %x.addr, align 4, !tbaa !4
Deleting dead instruction:   %0 = load i32, ptr %x.addr, align 4, !tbaa !4
Deleting dead instruction:   store i32 %x, ptr %x.addr, align 4, !tbaa !4
SROA alloca:   %acc.addr = alloca i32, align 4
  Rewriting FCA loads and stores...
Slices of alloca:   %acc.addr = alloca i32, align 4
  [0,4) slice #0 (splittable)
    used by:   store i32 %acc, ptr %acc.addr, align 4, !tbaa !4
  [0,4) slice #1 (splittable)
    used by:   %0 = load i32, ptr %acc.addr, align 4, !tbaa !4
  [0,4) slice #2 (splittable)
    used by:   store i32 %add, ptr %acc.addr, align 4, !tbaa !4
  [0,4) slice #3 (splittable)
    used by:   %1 = load i32, ptr %acc.addr, align 4, !tbaa !4
  [0,4) slice #4 (splittable)
    used by:   store i32 %add13, ptr %acc.addr, align 4, !tbaa !4
  [0,4) slice #5 (splittable)
    used by:   %2 = load i32, ptr %acc.addr, align 4, !tbaa !4
Pre-splitting loads and stores
  Searching for candidate loads and stores
Rewriting alloca partition [0,4) to:   %acc.addr = alloca i32, align 4
  rewriting [0,4) slice #0 (splittable)
   Begin:(0, 4) NewBegin:(0, 4) NewAllocaBegin:(0, 4)
    original:   store i32 %acc, ptr %acc.addr, align 4, !tbaa !4
          to:   store i32 %acc, ptr %acc.addr, align 4, !tbaa !4
  rewriting [0,4) slice #1 (splittable)
   Begin:(0, 4) NewBegin:(0, 4) NewAllocaBegin:(0, 4)
    original:   %0 = load i32, ptr %acc.addr, align 4, !tbaa !4
          to:   %acc.addr.0.load = load i32, ptr %acc.addr, align 4
  rewriting [0,4) slice #2 (splittable)
   Begin:(0, 4) NewBegin:(0, 4) NewAllocaBegin:(0, 4)
    original:   store i32 %add, ptr %acc.addr, align 4, !tbaa !4
          to:   store i32 %add, ptr %acc.addr, align 4, !tbaa !4
  rewriting [0,4) slice #3 (splittable)
   Begin:(0, 4) NewBegin:(0, 4) NewAllocaBegin:(0, 4)
    original:   %1 = load i32, ptr %acc.addr, align 4, !tbaa !4
          to:   %acc.addr.0.load16 = load i32, ptr %acc.addr, align 4
  rewriting [0,4) slice #4 (splittable)
   Begin:(0, 4) NewBegin:(0, 4) NewAllocaBegin:(0, 4)
    original:   store i32 %add13, ptr %acc.addr, align 4, !tbaa !4
          to:   store i32 %add13, ptr %acc.addr, align 4, !tbaa !4
  rewriting [0,4) slice #5 (splittable)
   Begin:(0, 4) NewBegin:(0, 4) NewAllocaBegin:(0, 4)
    original:   %2 = load i32, ptr %acc.addr, align 4, !tbaa !4
          to:   %acc.addr.0.load17 = load i32, ptr %acc.addr, align 4
  Speculating PHIs
  Rewriting Selects
Deleting dead instruction:   %2 = load i32, ptr %acc.addr, align 4, !tbaa !4
Deleting dead instruction:   store i32 %add13, ptr %acc.addr, align 4, !tbaa !4
Deleting dead instruction:   %1 = load i32, ptr %acc.addr, align 4, !tbaa !4
Deleting dead instruction:   store i32 %add, ptr %acc.addr, align 4, !tbaa !4
Deleting dead instruction:   %0 = load i32, ptr %acc.addr, align 4, !tbaa !4
Deleting dead instruction:   store i32 %acc, ptr %acc.addr, align 4, !tbaa !4
Promoting allocas with mem2reg...
; *** IR Dump After SROAPass on test_macs32_v2i16 ***
; Function Attrs: nounwind
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) #0 {
entry:
  %and = and i32 %x, 65535
  %conv = trunc i32 %and to i16
  %conv1 = sext i16 %conv to i32
  %and2 = and i32 %y, 65535
  %conv3 = trunc i32 %and2 to i16
  %conv4 = sext i16 %conv3 to i32
  %mul = mul nsw i32 %conv1, %conv4
  %add = add nsw i32 %acc, %mul
  %shr = ashr i32 %x, 16
  %and5 = and i32 %shr, 65535
  %conv6 = trunc i32 %and5 to i16
  %conv7 = sext i16 %conv6 to i32
  %shr8 = ashr i32 %y, 16
  %and9 = and i32 %shr8, 65535
  %conv10 = trunc i32 %and9 to i16
  %conv11 = sext i16 %conv10 to i32
  %mul12 = mul nsw i32 %conv7, %conv11
  %add13 = add nsw i32 %add, %mul12
  ret i32 %add13
}
; *** IR Dump Before EarlyCSEPass on test_macs32_v2i16 ***
; Function Attrs: nounwind
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) #0 {
entry:
  %and = and i32 %x, 65535
  %conv = trunc i32 %and to i16
  %conv1 = sext i16 %conv to i32
  %and2 = and i32 %y, 65535
  %conv3 = trunc i32 %and2 to i16
  %conv4 = sext i16 %conv3 to i32
  %mul = mul nsw i32 %conv1, %conv4
  %add = add nsw i32 %acc, %mul
  %shr = ashr i32 %x, 16
  %and5 = and i32 %shr, 65535
  %conv6 = trunc i32 %and5 to i16
  %conv7 = sext i16 %conv6 to i32
  %shr8 = ashr i32 %y, 16
  %and9 = and i32 %shr8, 65535
  %conv10 = trunc i32 %and9 to i16
  %conv11 = sext i16 %conv10 to i32
  %mul12 = mul nsw i32 %conv7, %conv11
  %add13 = add nsw i32 %add, %mul12
  ret i32 %add13
}
; *** IR Dump After EarlyCSEPass on test_macs32_v2i16 ***
; Function Attrs: nounwind
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) #0 {
entry:
  %and = and i32 %x, 65535
  %conv = trunc i32 %and to i16
  %conv1 = sext i16 %conv to i32
  %and2 = and i32 %y, 65535
  %conv3 = trunc i32 %and2 to i16
  %conv4 = sext i16 %conv3 to i32
  %mul = mul nsw i32 %conv1, %conv4
  %add = add nsw i32 %acc, %mul
  %shr = ashr i32 %x, 16
  %and5 = and i32 %shr, 65535
  %conv6 = trunc i32 %and5 to i16
  %conv7 = sext i16 %conv6 to i32
  %shr8 = ashr i32 %y, 16
  %and9 = and i32 %shr8, 65535
  %conv10 = trunc i32 %and9 to i16
  %conv11 = sext i16 %conv10 to i32
  %mul12 = mul nsw i32 %conv7, %conv11
  %add13 = add nsw i32 %add, %mul12
  ret i32 %add13
}
; *** IR Dump Before CallSiteSplittingPass on test_macs32_v2i16 ***
; Function Attrs: nounwind
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) #0 {
entry:
  %and = and i32 %x, 65535
  %conv = trunc i32 %and to i16
  %conv1 = sext i16 %conv to i32
  %and2 = and i32 %y, 65535
  %conv3 = trunc i32 %and2 to i16
  %conv4 = sext i16 %conv3 to i32
  %mul = mul nsw i32 %conv1, %conv4
  %add = add nsw i32 %acc, %mul
  %shr = ashr i32 %x, 16
  %and5 = and i32 %shr, 65535
  %conv6 = trunc i32 %and5 to i16
  %conv7 = sext i16 %conv6 to i32
  %shr8 = ashr i32 %y, 16
  %and9 = and i32 %shr8, 65535
  %conv10 = trunc i32 %and9 to i16
  %conv11 = sext i16 %conv10 to i32
  %mul12 = mul nsw i32 %conv7, %conv11
  %add13 = add nsw i32 %add, %mul12
  ret i32 %add13
}
; *** IR Dump After CallSiteSplittingPass on test_macs32_v2i16 ***
; Function Attrs: nounwind
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) #0 {
entry:
  %and = and i32 %x, 65535
  %conv = trunc i32 %and to i16
  %conv1 = sext i16 %conv to i32
  %and2 = and i32 %y, 65535
  %conv3 = trunc i32 %and2 to i16
  %conv4 = sext i16 %conv3 to i32
  %mul = mul nsw i32 %conv1, %conv4
  %add = add nsw i32 %acc, %mul
  %shr = ashr i32 %x, 16
  %and5 = and i32 %shr, 65535
  %conv6 = trunc i32 %and5 to i16
  %conv7 = sext i16 %conv6 to i32
  %shr8 = ashr i32 %y, 16
  %and9 = and i32 %shr8, 65535
  %conv10 = trunc i32 %and9 to i16
  %conv11 = sext i16 %conv10 to i32
  %mul12 = mul nsw i32 %conv7, %conv11
  %add13 = add nsw i32 %add, %mul12
  ret i32 %add13
}
; *** IR Dump Before OpenMPOptPass on [module] ***
; ModuleID = 'cecil_test.c'
source_filename = "cecil_test.c"
target datalayout = "e-m:e-p:32:32-i64:64-n32-S128"
target triple = "riscv32-unknown-unknown"

; Function Attrs: nounwind
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) #0 {
entry:
  %and = and i32 %x, 65535
  %conv = trunc i32 %and to i16
  %conv1 = sext i16 %conv to i32
  %and2 = and i32 %y, 65535
  %conv3 = trunc i32 %and2 to i16
  %conv4 = sext i16 %conv3 to i32
  %mul = mul nsw i32 %conv1, %conv4
  %add = add nsw i32 %acc, %mul
  %shr = ashr i32 %x, 16
  %and5 = and i32 %shr, 65535
  %conv6 = trunc i32 %and5 to i16
  %conv7 = sext i16 %conv6 to i32
  %shr8 = ashr i32 %y, 16
  %and9 = and i32 %shr8, 65535
  %conv10 = trunc i32 %and9 to i16
  %conv11 = sext i16 %conv10 to i32
  %mul12 = mul nsw i32 %conv7, %conv11
  %add13 = add nsw i32 %add, %mul12
  ret i32 %add13
}

attributes #0 = { nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="generic-rv32" "target-features"="+32bit,+m,+relax,+xseal5testalucvabs16,+xseal5testalucvabs32,+xseal5testalucvabs8,+xseal5testalucvaddnrsi16,+xseal5testalucvaddnrsi32,+xseal5testalucvaddnrui16,+xseal5testalucvaddnrui32,+xseal5testalucvaddns,+xseal5testalucvaddnu,+xseal5testalucvaddrnrsi16,+xseal5testalucvaddrnrsi32,+xseal5testalucvaddrnrui16,+xseal5testalucvaddrnrui32,+xseal5testalucvaddrns,+xseal5testalucvaddrnu,+xseal5testalucvextbs,+xseal5testalucvextbz,+xseal5testalucvexths,+xseal5testalucvexthz,+xseal5testalucvmaxi1216,+xseal5testalucvmaxi1232,+xseal5testalucvmaxi516,+xseal5testalucvmaxi532,+xseal5testalucvmaxs16,+xseal5testalucvmaxs32,+xseal5testalucvmaxs8,+xseal5testalucvmaxu16,+xseal5testalucvmaxu32,+xseal5testalucvmaxu8,+xseal5testalucvmini1216,+xseal5testalucvmini1232,+xseal5testalucvmini516,+xseal5testalucvmini532,+xseal5testalucvmins16,+xseal5testalucvmins32,+xseal5testalucvmins8,+xseal5testalucvminu16,+xseal5testalucvminu32,+xseal5testalucvminu8,+xseal5testalucvsletsi16,+xseal5testalucvsletsi32,+xseal5testalucvsletui16,+xseal5testalucvsletui32,+xseal5testalucvsubnrsi16,+xseal5testalucvsubnrsi32,+xseal5testalucvsubnrui16,+xseal5testalucvsubnrui32,+xseal5testalucvsubns,+xseal5testalucvsubnu,+xseal5testalucvsubrnrsi16,+xseal5testalucvsubrnrsi32,+xseal5testalucvsubrnrui16,+xseal5testalucvsubrnrui32,+xseal5testalucvsubrns,+xseal5testalucvsubrnu,+xseal5testmaccvmachhns,+xseal5testmaccvmachhnu,+xseal5testmaccvmachhrns,+xseal5testmaccvmachhrnu,+xseal5testmaccvmacns,+xseal5testmaccvmacnu,+xseal5testmaccvmacrns,+xseal5testmaccvmacrnu,+xseal5testmaccvmacsi16,+xseal5testmaccvmacsi32,+xseal5testmaccvmacui16,+xseal5testmaccvmacui32,+xseal5testmaccvmsusi16,+xseal5testmaccvmsusi32,+xseal5testmaccvmsuui16,+xseal5testmaccvmsuui32,+xseal5testmaccvmulhhns,+xseal5testmaccvmulhhnu,+xseal5testmaccvmulhhrns,+xseal5testmaccvmulhhrnu,+xseal5testmaccvmulns,+xseal5testmaccvmulnu,+xseal5testmaccvmulrns,+xseal5testmaccvmulrnu,-a,-c,-d,-e,-experimental-zacas,-experimental-zcmop,-experimental-zfbfmin,-experimental-zicfilp,-experimental-zicfiss,-experimental-zimop,-experimental-ztso,-experimental-zvfbfmin,-experimental-zvfbfwma,-f,-h,-smaia,-smepmp,-ssaia,-svinval,-svnapot,-svpbmt,-v,-xcvalu,-xcvbi,-xcvbitmanip,-xcvelw,-xcvmac,-xcvmem,-xcvsimd,-xsfvcp,-xsfvfnrclipxfqf,-xsfvfwmaccqqq,-xsfvqmaccdod,-xsfvqmaccqoq,-xtheadba,-xtheadbb,-xtheadbs,-xtheadcmo,-xtheadcondmov,-xtheadfmemidx,-xtheadmac,-xtheadmemidx,-xtheadmempair,-xtheadsync,-xtheadvdot,-xventanacondops,-za128rs,-za64rs,-zawrs,-zba,-zbb,-zbc,-zbkb,-zbkc,-zbkx,-zbs,-zca,-zcb,-zcd,-zce,-zcf,-zcmp,-zcmt,-zdinx,-zfa,-zfh,-zfhmin,-zfinx,-zhinx,-zhinxmin,-zic64b,-zicbom,-zicbop,-zicboz,-ziccamoa,-ziccif,-zicclsm,-ziccrse,-zicntr,-zicond,-zicsr,-zifencei,-zihintntl,-zihintpause,-zihpm,-zk,-zkn,-zknd,-zkne,-zknh,-zkr,-zks,-zksed,-zksh,-zkt,-zmmul,-zvbb,-zvbc,-zve32f,-zve32x,-zve64d,-zve64f,-zve64x,-zvfh,-zvfhmin,-zvkb,-zvkg,-zvkn,-zvknc,-zvkned,-zvkng,-zvknha,-zvknhb,-zvks,-zvksc,-zvksed,-zvksg,-zvksh,-zvkt,-zvl1024b,-zvl128b,-zvl16384b,-zvl2048b,-zvl256b,-zvl32768b,-zvl32b,-zvl4096b,-zvl512b,-zvl64b,-zvl65536b,-zvl8192b" }

!llvm.module.flags = !{!0, !1, !2}
!llvm.ident = !{!3}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 1, !"target-abi", !"ilp32"}
!2 = !{i32 8, !"SmallDataLimit", i32 8}
!3 = !{!"clang version 18.1.0rc (https://github.com/llvm/llvm-project.git 1acc4e456481e76822c76c850bad3994d4e04b59)"}
; *** IR Dump After OpenMPOptPass on [module] ***
; ModuleID = 'cecil_test.c'
source_filename = "cecil_test.c"
target datalayout = "e-m:e-p:32:32-i64:64-n32-S128"
target triple = "riscv32-unknown-unknown"

; Function Attrs: nounwind
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) #0 {
entry:
  %and = and i32 %x, 65535
  %conv = trunc i32 %and to i16
  %conv1 = sext i16 %conv to i32
  %and2 = and i32 %y, 65535
  %conv3 = trunc i32 %and2 to i16
  %conv4 = sext i16 %conv3 to i32
  %mul = mul nsw i32 %conv1, %conv4
  %add = add nsw i32 %acc, %mul
  %shr = ashr i32 %x, 16
  %and5 = and i32 %shr, 65535
  %conv6 = trunc i32 %and5 to i16
  %conv7 = sext i16 %conv6 to i32
  %shr8 = ashr i32 %y, 16
  %and9 = and i32 %shr8, 65535
  %conv10 = trunc i32 %and9 to i16
  %conv11 = sext i16 %conv10 to i32
  %mul12 = mul nsw i32 %conv7, %conv11
  %add13 = add nsw i32 %add, %mul12
  ret i32 %add13
}

attributes #0 = { nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="generic-rv32" "target-features"="+32bit,+m,+relax,+xseal5testalucvabs16,+xseal5testalucvabs32,+xseal5testalucvabs8,+xseal5testalucvaddnrsi16,+xseal5testalucvaddnrsi32,+xseal5testalucvaddnrui16,+xseal5testalucvaddnrui32,+xseal5testalucvaddns,+xseal5testalucvaddnu,+xseal5testalucvaddrnrsi16,+xseal5testalucvaddrnrsi32,+xseal5testalucvaddrnrui16,+xseal5testalucvaddrnrui32,+xseal5testalucvaddrns,+xseal5testalucvaddrnu,+xseal5testalucvextbs,+xseal5testalucvextbz,+xseal5testalucvexths,+xseal5testalucvexthz,+xseal5testalucvmaxi1216,+xseal5testalucvmaxi1232,+xseal5testalucvmaxi516,+xseal5testalucvmaxi532,+xseal5testalucvmaxs16,+xseal5testalucvmaxs32,+xseal5testalucvmaxs8,+xseal5testalucvmaxu16,+xseal5testalucvmaxu32,+xseal5testalucvmaxu8,+xseal5testalucvmini1216,+xseal5testalucvmini1232,+xseal5testalucvmini516,+xseal5testalucvmini532,+xseal5testalucvmins16,+xseal5testalucvmins32,+xseal5testalucvmins8,+xseal5testalucvminu16,+xseal5testalucvminu32,+xseal5testalucvminu8,+xseal5testalucvsletsi16,+xseal5testalucvsletsi32,+xseal5testalucvsletui16,+xseal5testalucvsletui32,+xseal5testalucvsubnrsi16,+xseal5testalucvsubnrsi32,+xseal5testalucvsubnrui16,+xseal5testalucvsubnrui32,+xseal5testalucvsubns,+xseal5testalucvsubnu,+xseal5testalucvsubrnrsi16,+xseal5testalucvsubrnrsi32,+xseal5testalucvsubrnrui16,+xseal5testalucvsubrnrui32,+xseal5testalucvsubrns,+xseal5testalucvsubrnu,+xseal5testmaccvmachhns,+xseal5testmaccvmachhnu,+xseal5testmaccvmachhrns,+xseal5testmaccvmachhrnu,+xseal5testmaccvmacns,+xseal5testmaccvmacnu,+xseal5testmaccvmacrns,+xseal5testmaccvmacrnu,+xseal5testmaccvmacsi16,+xseal5testmaccvmacsi32,+xseal5testmaccvmacui16,+xseal5testmaccvmacui32,+xseal5testmaccvmsusi16,+xseal5testmaccvmsusi32,+xseal5testmaccvmsuui16,+xseal5testmaccvmsuui32,+xseal5testmaccvmulhhns,+xseal5testmaccvmulhhnu,+xseal5testmaccvmulhhrns,+xseal5testmaccvmulhhrnu,+xseal5testmaccvmulns,+xseal5testmaccvmulnu,+xseal5testmaccvmulrns,+xseal5testmaccvmulrnu,-a,-c,-d,-e,-experimental-zacas,-experimental-zcmop,-experimental-zfbfmin,-experimental-zicfilp,-experimental-zicfiss,-experimental-zimop,-experimental-ztso,-experimental-zvfbfmin,-experimental-zvfbfwma,-f,-h,-smaia,-smepmp,-ssaia,-svinval,-svnapot,-svpbmt,-v,-xcvalu,-xcvbi,-xcvbitmanip,-xcvelw,-xcvmac,-xcvmem,-xcvsimd,-xsfvcp,-xsfvfnrclipxfqf,-xsfvfwmaccqqq,-xsfvqmaccdod,-xsfvqmaccqoq,-xtheadba,-xtheadbb,-xtheadbs,-xtheadcmo,-xtheadcondmov,-xtheadfmemidx,-xtheadmac,-xtheadmemidx,-xtheadmempair,-xtheadsync,-xtheadvdot,-xventanacondops,-za128rs,-za64rs,-zawrs,-zba,-zbb,-zbc,-zbkb,-zbkc,-zbkx,-zbs,-zca,-zcb,-zcd,-zce,-zcf,-zcmp,-zcmt,-zdinx,-zfa,-zfh,-zfhmin,-zfinx,-zhinx,-zhinxmin,-zic64b,-zicbom,-zicbop,-zicboz,-ziccamoa,-ziccif,-zicclsm,-ziccrse,-zicntr,-zicond,-zicsr,-zifencei,-zihintntl,-zihintpause,-zihpm,-zk,-zkn,-zknd,-zkne,-zknh,-zkr,-zks,-zksed,-zksh,-zkt,-zmmul,-zvbb,-zvbc,-zve32f,-zve32x,-zve64d,-zve64f,-zve64x,-zvfh,-zvfhmin,-zvkb,-zvkg,-zvkn,-zvknc,-zvkned,-zvkng,-zvknha,-zvknhb,-zvks,-zvksc,-zvksed,-zvksg,-zvksh,-zvkt,-zvl1024b,-zvl128b,-zvl16384b,-zvl2048b,-zvl256b,-zvl32768b,-zvl32b,-zvl4096b,-zvl512b,-zvl64b,-zvl65536b,-zvl8192b" }

!llvm.module.flags = !{!0, !1, !2}
!llvm.ident = !{!3}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 1, !"target-abi", !"ilp32"}
!2 = !{i32 8, !"SmallDataLimit", i32 8}
!3 = !{!"clang version 18.1.0rc (https://github.com/llvm/llvm-project.git 1acc4e456481e76822c76c850bad3994d4e04b59)"}
; *** IR Dump Before IPSCCPPass on [module] ***
; ModuleID = 'cecil_test.c'
source_filename = "cecil_test.c"
target datalayout = "e-m:e-p:32:32-i64:64-n32-S128"
target triple = "riscv32-unknown-unknown"

; Function Attrs: nounwind
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) #0 {
entry:
  %and = and i32 %x, 65535
  %conv = trunc i32 %and to i16
  %conv1 = sext i16 %conv to i32
  %and2 = and i32 %y, 65535
  %conv3 = trunc i32 %and2 to i16
  %conv4 = sext i16 %conv3 to i32
  %mul = mul nsw i32 %conv1, %conv4
  %add = add nsw i32 %acc, %mul
  %shr = ashr i32 %x, 16
  %and5 = and i32 %shr, 65535
  %conv6 = trunc i32 %and5 to i16
  %conv7 = sext i16 %conv6 to i32
  %shr8 = ashr i32 %y, 16
  %and9 = and i32 %shr8, 65535
  %conv10 = trunc i32 %and9 to i16
  %conv11 = sext i16 %conv10 to i32
  %mul12 = mul nsw i32 %conv7, %conv11
  %add13 = add nsw i32 %add, %mul12
  ret i32 %add13
}

attributes #0 = { nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="generic-rv32" "target-features"="+32bit,+m,+relax,+xseal5testalucvabs16,+xseal5testalucvabs32,+xseal5testalucvabs8,+xseal5testalucvaddnrsi16,+xseal5testalucvaddnrsi32,+xseal5testalucvaddnrui16,+xseal5testalucvaddnrui32,+xseal5testalucvaddns,+xseal5testalucvaddnu,+xseal5testalucvaddrnrsi16,+xseal5testalucvaddrnrsi32,+xseal5testalucvaddrnrui16,+xseal5testalucvaddrnrui32,+xseal5testalucvaddrns,+xseal5testalucvaddrnu,+xseal5testalucvextbs,+xseal5testalucvextbz,+xseal5testalucvexths,+xseal5testalucvexthz,+xseal5testalucvmaxi1216,+xseal5testalucvmaxi1232,+xseal5testalucvmaxi516,+xseal5testalucvmaxi532,+xseal5testalucvmaxs16,+xseal5testalucvmaxs32,+xseal5testalucvmaxs8,+xseal5testalucvmaxu16,+xseal5testalucvmaxu32,+xseal5testalucvmaxu8,+xseal5testalucvmini1216,+xseal5testalucvmini1232,+xseal5testalucvmini516,+xseal5testalucvmini532,+xseal5testalucvmins16,+xseal5testalucvmins32,+xseal5testalucvmins8,+xseal5testalucvminu16,+xseal5testalucvminu32,+xseal5testalucvminu8,+xseal5testalucvsletsi16,+xseal5testalucvsletsi32,+xseal5testalucvsletui16,+xseal5testalucvsletui32,+xseal5testalucvsubnrsi16,+xseal5testalucvsubnrsi32,+xseal5testalucvsubnrui16,+xseal5testalucvsubnrui32,+xseal5testalucvsubns,+xseal5testalucvsubnu,+xseal5testalucvsubrnrsi16,+xseal5testalucvsubrnrsi32,+xseal5testalucvsubrnrui16,+xseal5testalucvsubrnrui32,+xseal5testalucvsubrns,+xseal5testalucvsubrnu,+xseal5testmaccvmachhns,+xseal5testmaccvmachhnu,+xseal5testmaccvmachhrns,+xseal5testmaccvmachhrnu,+xseal5testmaccvmacns,+xseal5testmaccvmacnu,+xseal5testmaccvmacrns,+xseal5testmaccvmacrnu,+xseal5testmaccvmacsi16,+xseal5testmaccvmacsi32,+xseal5testmaccvmacui16,+xseal5testmaccvmacui32,+xseal5testmaccvmsusi16,+xseal5testmaccvmsusi32,+xseal5testmaccvmsuui16,+xseal5testmaccvmsuui32,+xseal5testmaccvmulhhns,+xseal5testmaccvmulhhnu,+xseal5testmaccvmulhhrns,+xseal5testmaccvmulhhrnu,+xseal5testmaccvmulns,+xseal5testmaccvmulnu,+xseal5testmaccvmulrns,+xseal5testmaccvmulrnu,-a,-c,-d,-e,-experimental-zacas,-experimental-zcmop,-experimental-zfbfmin,-experimental-zicfilp,-experimental-zicfiss,-experimental-zimop,-experimental-ztso,-experimental-zvfbfmin,-experimental-zvfbfwma,-f,-h,-smaia,-smepmp,-ssaia,-svinval,-svnapot,-svpbmt,-v,-xcvalu,-xcvbi,-xcvbitmanip,-xcvelw,-xcvmac,-xcvmem,-xcvsimd,-xsfvcp,-xsfvfnrclipxfqf,-xsfvfwmaccqqq,-xsfvqmaccdod,-xsfvqmaccqoq,-xtheadba,-xtheadbb,-xtheadbs,-xtheadcmo,-xtheadcondmov,-xtheadfmemidx,-xtheadmac,-xtheadmemidx,-xtheadmempair,-xtheadsync,-xtheadvdot,-xventanacondops,-za128rs,-za64rs,-zawrs,-zba,-zbb,-zbc,-zbkb,-zbkc,-zbkx,-zbs,-zca,-zcb,-zcd,-zce,-zcf,-zcmp,-zcmt,-zdinx,-zfa,-zfh,-zfhmin,-zfinx,-zhinx,-zhinxmin,-zic64b,-zicbom,-zicbop,-zicboz,-ziccamoa,-ziccif,-zicclsm,-ziccrse,-zicntr,-zicond,-zicsr,-zifencei,-zihintntl,-zihintpause,-zihpm,-zk,-zkn,-zknd,-zkne,-zknh,-zkr,-zks,-zksed,-zksh,-zkt,-zmmul,-zvbb,-zvbc,-zve32f,-zve32x,-zve64d,-zve64f,-zve64x,-zvfh,-zvfhmin,-zvkb,-zvkg,-zvkn,-zvknc,-zvkned,-zvkng,-zvknha,-zvknhb,-zvks,-zvksc,-zvksed,-zvksg,-zvksh,-zvkt,-zvl1024b,-zvl128b,-zvl16384b,-zvl2048b,-zvl256b,-zvl32768b,-zvl32b,-zvl4096b,-zvl512b,-zvl64b,-zvl65536b,-zvl8192b" }

!llvm.module.flags = !{!0, !1, !2}
!llvm.ident = !{!3}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 1, !"target-abi", !"ilp32"}
!2 = !{i32 8, !"SmallDataLimit", i32 8}
!3 = !{!"clang version 18.1.0rc (https://github.com/llvm/llvm-project.git 1acc4e456481e76822c76c850bad3994d4e04b59)"}
Marking Block Executable: entry
markOverdefined: i32 %acc
markOverdefined: i32 %x
markOverdefined: i32 %y

Popped off OI-WL: i32 %y
Merged constantrange<0, 65536> into   %and2 = and i32 %y, 65535 : constantrange<0, 65536>
Merged constantrange<-32768, 32768> into   %shr8 = ashr i32 %y, 16 : constantrange<-32768, 32768>

Popped off OI-WL: i32 %x
Merged constantrange<0, 65536> into   %and = and i32 %x, 65535 : constantrange<0, 65536>
Merged constantrange<-32768, 32768> into   %shr = ashr i32 %x, 16 : constantrange<-32768, 32768>

Popped off OI-WL: i32 %acc

Popped off I-WL:   %shr = ashr i32 %x, 16
Merged constantrange<0, 65536> into   %and5 = and i32 %shr, 65535 : constantrange<0, 65536>

Popped off I-WL:   %and5 = and i32 %shr, 65535
Merged overdefined into   %conv6 = trunc i32 %and5 to i16 : overdefined

Popped off I-WL:   %and = and i32 %x, 65535
Merged overdefined into   %conv = trunc i32 %and to i16 : overdefined

Popped off I-WL:   %shr8 = ashr i32 %y, 16
Merged constantrange<0, 65536> into   %and9 = and i32 %shr8, 65535 : constantrange<0, 65536>

Popped off I-WL:   %and9 = and i32 %shr8, 65535
Merged overdefined into   %conv10 = trunc i32 %and9 to i16 : overdefined

Popped off I-WL:   %and2 = and i32 %y, 65535
Merged overdefined into   %conv3 = trunc i32 %and2 to i16 : overdefined

Popped off BBWL: 
entry:
  %and = and i32 %x, 65535
  %conv = trunc i32 %and to i16
  %conv1 = sext i16 %conv to i32
  %and2 = and i32 %y, 65535
  %conv3 = trunc i32 %and2 to i16
  %conv4 = sext i16 %conv3 to i32
  %mul = mul nsw i32 %conv1, %conv4
  %add = add nsw i32 %acc, %mul
  %shr = ashr i32 %x, 16
  %and5 = and i32 %shr, 65535
  %conv6 = trunc i32 %and5 to i16
  %conv7 = sext i16 %conv6 to i32
  %shr8 = ashr i32 %y, 16
  %and9 = and i32 %shr8, 65535
  %conv10 = trunc i32 %and9 to i16
  %conv11 = sext i16 %conv10 to i32
  %mul12 = mul nsw i32 %conv7, %conv11
  %add13 = add nsw i32 %add, %mul12
  ret i32 %add13

Merged constantrange<-32768, 32768> into   %conv1 = sext i16 %conv to i32 : constantrange<-32768, 32768>
Merged constantrange<-32768, 32768> into   %conv4 = sext i16 %conv3 to i32 : constantrange<-32768, 32768>
Merged constantrange<-1073709056, 1073741825> into   %mul = mul nsw i32 %conv1, %conv4 : constantrange<-1073709056, 1073741825>
Merged overdefined into   %add = add nsw i32 %acc, %mul : overdefined
Merged constantrange<-32768, 32768> into   %conv7 = sext i16 %conv6 to i32 : constantrange<-32768, 32768>
Merged constantrange<-32768, 32768> into   %conv11 = sext i16 %conv10 to i32 : constantrange<-32768, 32768>
Merged constantrange<-1073709056, 1073741825> into   %mul12 = mul nsw i32 %conv7, %conv11 : constantrange<-1073709056, 1073741825>
Merged overdefined into   %add13 = add nsw i32 %add, %mul12 : overdefined
Merged overdefined into ; Function Attrs: nounwind
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) #0 {
entry:
  %and = and i32 %x, 65535
  %conv = trunc i32 %and to i16
  %conv1 = sext i16 %conv to i32
  %and2 = and i32 %y, 65535
  %conv3 = trunc i32 %and2 to i16
  %conv4 = sext i16 %conv3 to i32
  %mul = mul nsw i32 %conv1, %conv4
  %add = add nsw i32 %acc, %mul
  %shr = ashr i32 %x, 16
  %and5 = and i32 %shr, 65535
  %conv6 = trunc i32 %and5 to i16
  %conv7 = sext i16 %conv6 to i32
  %shr8 = ashr i32 %y, 16
  %and9 = and i32 %shr8, 65535
  %conv10 = trunc i32 %and9 to i16
  %conv11 = sext i16 %conv10 to i32
  %mul12 = mul nsw i32 %conv7, %conv11
  %add13 = add nsw i32 %add, %mul12
  ret i32 %add13
}
 : overdefined

Popped off OI-WL: ; Function Attrs: nounwind
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) #0 {
entry:
  %and = and i32 %x, 65535
  %conv = trunc i32 %and to i16
  %conv1 = sext i16 %conv to i32
  %and2 = and i32 %y, 65535
  %conv3 = trunc i32 %and2 to i16
  %conv4 = sext i16 %conv3 to i32
  %mul = mul nsw i32 %conv1, %conv4
  %add = add nsw i32 %acc, %mul
  %shr = ashr i32 %x, 16
  %and5 = and i32 %shr, 65535
  %conv6 = trunc i32 %and5 to i16
  %conv7 = sext i16 %conv6 to i32
  %shr8 = ashr i32 %y, 16
  %and9 = and i32 %shr8, 65535
  %conv10 = trunc i32 %and9 to i16
  %conv11 = sext i16 %conv10 to i32
  %mul12 = mul nsw i32 %conv7, %conv11
  %add13 = add nsw i32 %add, %mul12
  ret i32 %add13
}


Popped off OI-WL:   %add13 = add nsw i32 %add, %mul12

Popped off OI-WL:   %add = add nsw i32 %acc, %mul

Popped off OI-WL:   %conv3 = trunc i32 %and2 to i16

Popped off OI-WL:   %conv10 = trunc i32 %and9 to i16

Popped off OI-WL:   %conv = trunc i32 %and to i16

Popped off OI-WL:   %conv6 = trunc i32 %and5 to i16

Popped off I-WL:   %mul12 = mul nsw i32 %conv7, %conv11

Popped off I-WL:   %conv11 = sext i16 %conv10 to i32

Popped off I-WL:   %conv7 = sext i16 %conv6 to i32

Popped off I-WL:   %mul = mul nsw i32 %conv1, %conv4

Popped off I-WL:   %conv4 = sext i16 %conv3 to i32

Popped off I-WL:   %conv1 = sext i16 %conv to i32
FnSpecialization: Try function: test_macs32_v2i16
FnSpecialization: No possible specializations found in module
; *** IR Dump After IPSCCPPass on [module] ***
; ModuleID = 'cecil_test.c'
source_filename = "cecil_test.c"
target datalayout = "e-m:e-p:32:32-i64:64-n32-S128"
target triple = "riscv32-unknown-unknown"

; Function Attrs: nounwind
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) #0 {
entry:
  %and = and i32 %x, 65535
  %conv = trunc i32 %and to i16
  %conv1 = sext i16 %conv to i32
  %and2 = and i32 %y, 65535
  %conv3 = trunc i32 %and2 to i16
  %conv4 = sext i16 %conv3 to i32
  %mul = mul nsw i32 %conv1, %conv4
  %add = add nsw i32 %acc, %mul
  %shr = ashr i32 %x, 16
  %and5 = and i32 %shr, 65535
  %conv6 = trunc i32 %and5 to i16
  %conv7 = sext i16 %conv6 to i32
  %shr8 = ashr i32 %y, 16
  %and9 = and i32 %shr8, 65535
  %conv10 = trunc i32 %and9 to i16
  %conv11 = sext i16 %conv10 to i32
  %mul12 = mul nsw i32 %conv7, %conv11
  %add13 = add nsw i32 %add, %mul12
  ret i32 %add13
}

attributes #0 = { nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="generic-rv32" "target-features"="+32bit,+m,+relax,+xseal5testalucvabs16,+xseal5testalucvabs32,+xseal5testalucvabs8,+xseal5testalucvaddnrsi16,+xseal5testalucvaddnrsi32,+xseal5testalucvaddnrui16,+xseal5testalucvaddnrui32,+xseal5testalucvaddns,+xseal5testalucvaddnu,+xseal5testalucvaddrnrsi16,+xseal5testalucvaddrnrsi32,+xseal5testalucvaddrnrui16,+xseal5testalucvaddrnrui32,+xseal5testalucvaddrns,+xseal5testalucvaddrnu,+xseal5testalucvextbs,+xseal5testalucvextbz,+xseal5testalucvexths,+xseal5testalucvexthz,+xseal5testalucvmaxi1216,+xseal5testalucvmaxi1232,+xseal5testalucvmaxi516,+xseal5testalucvmaxi532,+xseal5testalucvmaxs16,+xseal5testalucvmaxs32,+xseal5testalucvmaxs8,+xseal5testalucvmaxu16,+xseal5testalucvmaxu32,+xseal5testalucvmaxu8,+xseal5testalucvmini1216,+xseal5testalucvmini1232,+xseal5testalucvmini516,+xseal5testalucvmini532,+xseal5testalucvmins16,+xseal5testalucvmins32,+xseal5testalucvmins8,+xseal5testalucvminu16,+xseal5testalucvminu32,+xseal5testalucvminu8,+xseal5testalucvsletsi16,+xseal5testalucvsletsi32,+xseal5testalucvsletui16,+xseal5testalucvsletui32,+xseal5testalucvsubnrsi16,+xseal5testalucvsubnrsi32,+xseal5testalucvsubnrui16,+xseal5testalucvsubnrui32,+xseal5testalucvsubns,+xseal5testalucvsubnu,+xseal5testalucvsubrnrsi16,+xseal5testalucvsubrnrsi32,+xseal5testalucvsubrnrui16,+xseal5testalucvsubrnrui32,+xseal5testalucvsubrns,+xseal5testalucvsubrnu,+xseal5testmaccvmachhns,+xseal5testmaccvmachhnu,+xseal5testmaccvmachhrns,+xseal5testmaccvmachhrnu,+xseal5testmaccvmacns,+xseal5testmaccvmacnu,+xseal5testmaccvmacrns,+xseal5testmaccvmacrnu,+xseal5testmaccvmacsi16,+xseal5testmaccvmacsi32,+xseal5testmaccvmacui16,+xseal5testmaccvmacui32,+xseal5testmaccvmsusi16,+xseal5testmaccvmsusi32,+xseal5testmaccvmsuui16,+xseal5testmaccvmsuui32,+xseal5testmaccvmulhhns,+xseal5testmaccvmulhhnu,+xseal5testmaccvmulhhrns,+xseal5testmaccvmulhhrnu,+xseal5testmaccvmulns,+xseal5testmaccvmulnu,+xseal5testmaccvmulrns,+xseal5testmaccvmulrnu,-a,-c,-d,-e,-experimental-zacas,-experimental-zcmop,-experimental-zfbfmin,-experimental-zicfilp,-experimental-zicfiss,-experimental-zimop,-experimental-ztso,-experimental-zvfbfmin,-experimental-zvfbfwma,-f,-h,-smaia,-smepmp,-ssaia,-svinval,-svnapot,-svpbmt,-v,-xcvalu,-xcvbi,-xcvbitmanip,-xcvelw,-xcvmac,-xcvmem,-xcvsimd,-xsfvcp,-xsfvfnrclipxfqf,-xsfvfwmaccqqq,-xsfvqmaccdod,-xsfvqmaccqoq,-xtheadba,-xtheadbb,-xtheadbs,-xtheadcmo,-xtheadcondmov,-xtheadfmemidx,-xtheadmac,-xtheadmemidx,-xtheadmempair,-xtheadsync,-xtheadvdot,-xventanacondops,-za128rs,-za64rs,-zawrs,-zba,-zbb,-zbc,-zbkb,-zbkc,-zbkx,-zbs,-zca,-zcb,-zcd,-zce,-zcf,-zcmp,-zcmt,-zdinx,-zfa,-zfh,-zfhmin,-zfinx,-zhinx,-zhinxmin,-zic64b,-zicbom,-zicbop,-zicboz,-ziccamoa,-ziccif,-zicclsm,-ziccrse,-zicntr,-zicond,-zicsr,-zifencei,-zihintntl,-zihintpause,-zihpm,-zk,-zkn,-zknd,-zkne,-zknh,-zkr,-zks,-zksed,-zksh,-zkt,-zmmul,-zvbb,-zvbc,-zve32f,-zve32x,-zve64d,-zve64f,-zve64x,-zvfh,-zvfhmin,-zvkb,-zvkg,-zvkn,-zvknc,-zvkned,-zvkng,-zvknha,-zvknhb,-zvks,-zvksc,-zvksed,-zvksg,-zvksh,-zvkt,-zvl1024b,-zvl128b,-zvl16384b,-zvl2048b,-zvl256b,-zvl32768b,-zvl32b,-zvl4096b,-zvl512b,-zvl64b,-zvl65536b,-zvl8192b" }

!llvm.module.flags = !{!0, !1, !2}
!llvm.ident = !{!3}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 1, !"target-abi", !"ilp32"}
!2 = !{i32 8, !"SmallDataLimit", i32 8}
!3 = !{!"clang version 18.1.0rc (https://github.com/llvm/llvm-project.git 1acc4e456481e76822c76c850bad3994d4e04b59)"}
; *** IR Dump Before CalledValuePropagationPass on [module] ***
; ModuleID = 'cecil_test.c'
source_filename = "cecil_test.c"
target datalayout = "e-m:e-p:32:32-i64:64-n32-S128"
target triple = "riscv32-unknown-unknown"

; Function Attrs: nounwind
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) #0 {
entry:
  %and = and i32 %x, 65535
  %conv = trunc i32 %and to i16
  %conv1 = sext i16 %conv to i32
  %and2 = and i32 %y, 65535
  %conv3 = trunc i32 %and2 to i16
  %conv4 = sext i16 %conv3 to i32
  %mul = mul nsw i32 %conv1, %conv4
  %add = add nsw i32 %acc, %mul
  %shr = ashr i32 %x, 16
  %and5 = and i32 %shr, 65535
  %conv6 = trunc i32 %and5 to i16
  %conv7 = sext i16 %conv6 to i32
  %shr8 = ashr i32 %y, 16
  %and9 = and i32 %shr8, 65535
  %conv10 = trunc i32 %and9 to i16
  %conv11 = sext i16 %conv10 to i32
  %mul12 = mul nsw i32 %conv7, %conv11
  %add13 = add nsw i32 %add, %mul12
  ret i32 %add13
}

attributes #0 = { nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="generic-rv32" "target-features"="+32bit,+m,+relax,+xseal5testalucvabs16,+xseal5testalucvabs32,+xseal5testalucvabs8,+xseal5testalucvaddnrsi16,+xseal5testalucvaddnrsi32,+xseal5testalucvaddnrui16,+xseal5testalucvaddnrui32,+xseal5testalucvaddns,+xseal5testalucvaddnu,+xseal5testalucvaddrnrsi16,+xseal5testalucvaddrnrsi32,+xseal5testalucvaddrnrui16,+xseal5testalucvaddrnrui32,+xseal5testalucvaddrns,+xseal5testalucvaddrnu,+xseal5testalucvextbs,+xseal5testalucvextbz,+xseal5testalucvexths,+xseal5testalucvexthz,+xseal5testalucvmaxi1216,+xseal5testalucvmaxi1232,+xseal5testalucvmaxi516,+xseal5testalucvmaxi532,+xseal5testalucvmaxs16,+xseal5testalucvmaxs32,+xseal5testalucvmaxs8,+xseal5testalucvmaxu16,+xseal5testalucvmaxu32,+xseal5testalucvmaxu8,+xseal5testalucvmini1216,+xseal5testalucvmini1232,+xseal5testalucvmini516,+xseal5testalucvmini532,+xseal5testalucvmins16,+xseal5testalucvmins32,+xseal5testalucvmins8,+xseal5testalucvminu16,+xseal5testalucvminu32,+xseal5testalucvminu8,+xseal5testalucvsletsi16,+xseal5testalucvsletsi32,+xseal5testalucvsletui16,+xseal5testalucvsletui32,+xseal5testalucvsubnrsi16,+xseal5testalucvsubnrsi32,+xseal5testalucvsubnrui16,+xseal5testalucvsubnrui32,+xseal5testalucvsubns,+xseal5testalucvsubnu,+xseal5testalucvsubrnrsi16,+xseal5testalucvsubrnrsi32,+xseal5testalucvsubrnrui16,+xseal5testalucvsubrnrui32,+xseal5testalucvsubrns,+xseal5testalucvsubrnu,+xseal5testmaccvmachhns,+xseal5testmaccvmachhnu,+xseal5testmaccvmachhrns,+xseal5testmaccvmachhrnu,+xseal5testmaccvmacns,+xseal5testmaccvmacnu,+xseal5testmaccvmacrns,+xseal5testmaccvmacrnu,+xseal5testmaccvmacsi16,+xseal5testmaccvmacsi32,+xseal5testmaccvmacui16,+xseal5testmaccvmacui32,+xseal5testmaccvmsusi16,+xseal5testmaccvmsusi32,+xseal5testmaccvmsuui16,+xseal5testmaccvmsuui32,+xseal5testmaccvmulhhns,+xseal5testmaccvmulhhnu,+xseal5testmaccvmulhhrns,+xseal5testmaccvmulhhrnu,+xseal5testmaccvmulns,+xseal5testmaccvmulnu,+xseal5testmaccvmulrns,+xseal5testmaccvmulrnu,-a,-c,-d,-e,-experimental-zacas,-experimental-zcmop,-experimental-zfbfmin,-experimental-zicfilp,-experimental-zicfiss,-experimental-zimop,-experimental-ztso,-experimental-zvfbfmin,-experimental-zvfbfwma,-f,-h,-smaia,-smepmp,-ssaia,-svinval,-svnapot,-svpbmt,-v,-xcvalu,-xcvbi,-xcvbitmanip,-xcvelw,-xcvmac,-xcvmem,-xcvsimd,-xsfvcp,-xsfvfnrclipxfqf,-xsfvfwmaccqqq,-xsfvqmaccdod,-xsfvqmaccqoq,-xtheadba,-xtheadbb,-xtheadbs,-xtheadcmo,-xtheadcondmov,-xtheadfmemidx,-xtheadmac,-xtheadmemidx,-xtheadmempair,-xtheadsync,-xtheadvdot,-xventanacondops,-za128rs,-za64rs,-zawrs,-zba,-zbb,-zbc,-zbkb,-zbkc,-zbkx,-zbs,-zca,-zcb,-zcd,-zce,-zcf,-zcmp,-zcmt,-zdinx,-zfa,-zfh,-zfhmin,-zfinx,-zhinx,-zhinxmin,-zic64b,-zicbom,-zicbop,-zicboz,-ziccamoa,-ziccif,-zicclsm,-ziccrse,-zicntr,-zicond,-zicsr,-zifencei,-zihintntl,-zihintpause,-zihpm,-zk,-zkn,-zknd,-zkne,-zknh,-zkr,-zks,-zksed,-zksh,-zkt,-zmmul,-zvbb,-zvbc,-zve32f,-zve32x,-zve64d,-zve64f,-zve64x,-zvfh,-zvfhmin,-zvkb,-zvkg,-zvkn,-zvknc,-zvkned,-zvkng,-zvknha,-zvknhb,-zvks,-zvksc,-zvksed,-zvksg,-zvksh,-zvkt,-zvl1024b,-zvl128b,-zvl16384b,-zvl2048b,-zvl256b,-zvl32768b,-zvl32b,-zvl4096b,-zvl512b,-zvl64b,-zvl65536b,-zvl8192b" }

!llvm.module.flags = !{!0, !1, !2}
!llvm.ident = !{!3}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 1, !"target-abi", !"ilp32"}
!2 = !{i32 8, !"SmallDataLimit", i32 8}
!3 = !{!"clang version 18.1.0rc (https://github.com/llvm/llvm-project.git 1acc4e456481e76822c76c850bad3994d4e04b59)"}
Marking Block Executable: entry

Popped off BBWL: 
entry:
  %and = and i32 %x, 65535
  %conv = trunc i32 %and to i16
  %conv1 = sext i16 %conv to i32
  %and2 = and i32 %y, 65535
  %conv3 = trunc i32 %and2 to i16
  %conv4 = sext i16 %conv3 to i32
  %mul = mul nsw i32 %conv1, %conv4
  %add = add nsw i32 %acc, %mul
  %shr = ashr i32 %x, 16
  %and5 = and i32 %shr, 65535
  %conv6 = trunc i32 %and5 to i16
  %conv7 = sext i16 %conv6 to i32
  %shr8 = ashr i32 %y, 16
  %and9 = and i32 %shr8, 65535
  %conv10 = trunc i32 %and9 to i16
  %conv11 = sext i16 %conv10 to i32
  %mul12 = mul nsw i32 %conv7, %conv11
  %add13 = add nsw i32 %add, %mul12
  ret i32 %add13

Popped off V-WL: ; Function Attrs: nounwind
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) #0 {
entry:
  %and = and i32 %x, 65535
  %conv = trunc i32 %and to i16
  %conv1 = sext i16 %conv to i32
  %and2 = and i32 %y, 65535
  %conv3 = trunc i32 %and2 to i16
  %conv4 = sext i16 %conv3 to i32
  %mul = mul nsw i32 %conv1, %conv4
  %add = add nsw i32 %acc, %mul
  %shr = ashr i32 %x, 16
  %and5 = and i32 %shr, 65535
  %conv6 = trunc i32 %and5 to i16
  %conv7 = sext i16 %conv6 to i32
  %shr8 = ashr i32 %y, 16
  %and9 = and i32 %shr8, 65535
  %conv10 = trunc i32 %and9 to i16
  %conv11 = sext i16 %conv10 to i32
  %mul12 = mul nsw i32 %conv7, %conv11
  %add13 = add nsw i32 %add, %mul12
  ret i32 %add13
}


Popped off V-WL:   %add13 = add nsw i32 %add, %mul12

Popped off V-WL:   %mul12 = mul nsw i32 %conv7, %conv11

Popped off V-WL:   %conv11 = sext i16 %conv10 to i32

Popped off V-WL:   %conv10 = trunc i32 %and9 to i16

Popped off V-WL:   %and9 = and i32 %shr8, 65535

Popped off V-WL:   %shr8 = ashr i32 %y, 16

Popped off V-WL:   %conv7 = sext i16 %conv6 to i32

Popped off V-WL:   %conv6 = trunc i32 %and5 to i16

Popped off V-WL:   %and5 = and i32 %shr, 65535

Popped off V-WL:   %shr = ashr i32 %x, 16

Popped off V-WL:   %add = add nsw i32 %acc, %mul

Popped off V-WL:   %mul = mul nsw i32 %conv1, %conv4

Popped off V-WL:   %conv4 = sext i16 %conv3 to i32

Popped off V-WL:   %conv3 = trunc i32 %and2 to i16

Popped off V-WL:   %and2 = and i32 %y, 65535

Popped off V-WL:   %conv1 = sext i16 %conv to i32

Popped off V-WL:   %conv = trunc i32 %and to i16

Popped off V-WL:   %and = and i32 %x, 65535
; *** IR Dump After CalledValuePropagationPass on [module] ***
; ModuleID = 'cecil_test.c'
source_filename = "cecil_test.c"
target datalayout = "e-m:e-p:32:32-i64:64-n32-S128"
target triple = "riscv32-unknown-unknown"

; Function Attrs: nounwind
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) #0 {
entry:
  %and = and i32 %x, 65535
  %conv = trunc i32 %and to i16
  %conv1 = sext i16 %conv to i32
  %and2 = and i32 %y, 65535
  %conv3 = trunc i32 %and2 to i16
  %conv4 = sext i16 %conv3 to i32
  %mul = mul nsw i32 %conv1, %conv4
  %add = add nsw i32 %acc, %mul
  %shr = ashr i32 %x, 16
  %and5 = and i32 %shr, 65535
  %conv6 = trunc i32 %and5 to i16
  %conv7 = sext i16 %conv6 to i32
  %shr8 = ashr i32 %y, 16
  %and9 = and i32 %shr8, 65535
  %conv10 = trunc i32 %and9 to i16
  %conv11 = sext i16 %conv10 to i32
  %mul12 = mul nsw i32 %conv7, %conv11
  %add13 = add nsw i32 %add, %mul12
  ret i32 %add13
}

attributes #0 = { nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="generic-rv32" "target-features"="+32bit,+m,+relax,+xseal5testalucvabs16,+xseal5testalucvabs32,+xseal5testalucvabs8,+xseal5testalucvaddnrsi16,+xseal5testalucvaddnrsi32,+xseal5testalucvaddnrui16,+xseal5testalucvaddnrui32,+xseal5testalucvaddns,+xseal5testalucvaddnu,+xseal5testalucvaddrnrsi16,+xseal5testalucvaddrnrsi32,+xseal5testalucvaddrnrui16,+xseal5testalucvaddrnrui32,+xseal5testalucvaddrns,+xseal5testalucvaddrnu,+xseal5testalucvextbs,+xseal5testalucvextbz,+xseal5testalucvexths,+xseal5testalucvexthz,+xseal5testalucvmaxi1216,+xseal5testalucvmaxi1232,+xseal5testalucvmaxi516,+xseal5testalucvmaxi532,+xseal5testalucvmaxs16,+xseal5testalucvmaxs32,+xseal5testalucvmaxs8,+xseal5testalucvmaxu16,+xseal5testalucvmaxu32,+xseal5testalucvmaxu8,+xseal5testalucvmini1216,+xseal5testalucvmini1232,+xseal5testalucvmini516,+xseal5testalucvmini532,+xseal5testalucvmins16,+xseal5testalucvmins32,+xseal5testalucvmins8,+xseal5testalucvminu16,+xseal5testalucvminu32,+xseal5testalucvminu8,+xseal5testalucvsletsi16,+xseal5testalucvsletsi32,+xseal5testalucvsletui16,+xseal5testalucvsletui32,+xseal5testalucvsubnrsi16,+xseal5testalucvsubnrsi32,+xseal5testalucvsubnrui16,+xseal5testalucvsubnrui32,+xseal5testalucvsubns,+xseal5testalucvsubnu,+xseal5testalucvsubrnrsi16,+xseal5testalucvsubrnrsi32,+xseal5testalucvsubrnrui16,+xseal5testalucvsubrnrui32,+xseal5testalucvsubrns,+xseal5testalucvsubrnu,+xseal5testmaccvmachhns,+xseal5testmaccvmachhnu,+xseal5testmaccvmachhrns,+xseal5testmaccvmachhrnu,+xseal5testmaccvmacns,+xseal5testmaccvmacnu,+xseal5testmaccvmacrns,+xseal5testmaccvmacrnu,+xseal5testmaccvmacsi16,+xseal5testmaccvmacsi32,+xseal5testmaccvmacui16,+xseal5testmaccvmacui32,+xseal5testmaccvmsusi16,+xseal5testmaccvmsusi32,+xseal5testmaccvmsuui16,+xseal5testmaccvmsuui32,+xseal5testmaccvmulhhns,+xseal5testmaccvmulhhnu,+xseal5testmaccvmulhhrns,+xseal5testmaccvmulhhrnu,+xseal5testmaccvmulns,+xseal5testmaccvmulnu,+xseal5testmaccvmulrns,+xseal5testmaccvmulrnu,-a,-c,-d,-e,-experimental-zacas,-experimental-zcmop,-experimental-zfbfmin,-experimental-zicfilp,-experimental-zicfiss,-experimental-zimop,-experimental-ztso,-experimental-zvfbfmin,-experimental-zvfbfwma,-f,-h,-smaia,-smepmp,-ssaia,-svinval,-svnapot,-svpbmt,-v,-xcvalu,-xcvbi,-xcvbitmanip,-xcvelw,-xcvmac,-xcvmem,-xcvsimd,-xsfvcp,-xsfvfnrclipxfqf,-xsfvfwmaccqqq,-xsfvqmaccdod,-xsfvqmaccqoq,-xtheadba,-xtheadbb,-xtheadbs,-xtheadcmo,-xtheadcondmov,-xtheadfmemidx,-xtheadmac,-xtheadmemidx,-xtheadmempair,-xtheadsync,-xtheadvdot,-xventanacondops,-za128rs,-za64rs,-zawrs,-zba,-zbb,-zbc,-zbkb,-zbkc,-zbkx,-zbs,-zca,-zcb,-zcd,-zce,-zcf,-zcmp,-zcmt,-zdinx,-zfa,-zfh,-zfhmin,-zfinx,-zhinx,-zhinxmin,-zic64b,-zicbom,-zicbop,-zicboz,-ziccamoa,-ziccif,-zicclsm,-ziccrse,-zicntr,-zicond,-zicsr,-zifencei,-zihintntl,-zihintpause,-zihpm,-zk,-zkn,-zknd,-zkne,-zknh,-zkr,-zks,-zksed,-zksh,-zkt,-zmmul,-zvbb,-zvbc,-zve32f,-zve32x,-zve64d,-zve64f,-zve64x,-zvfh,-zvfhmin,-zvkb,-zvkg,-zvkn,-zvknc,-zvkned,-zvkng,-zvknha,-zvknhb,-zvks,-zvksc,-zvksed,-zvksg,-zvksh,-zvkt,-zvl1024b,-zvl128b,-zvl16384b,-zvl2048b,-zvl256b,-zvl32768b,-zvl32b,-zvl4096b,-zvl512b,-zvl64b,-zvl65536b,-zvl8192b" }

!llvm.module.flags = !{!0, !1, !2}
!llvm.ident = !{!3}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 1, !"target-abi", !"ilp32"}
!2 = !{i32 8, !"SmallDataLimit", i32 8}
!3 = !{!"clang version 18.1.0rc (https://github.com/llvm/llvm-project.git 1acc4e456481e76822c76c850bad3994d4e04b59)"}
; *** IR Dump Before GlobalOptPass on [module] ***
; ModuleID = 'cecil_test.c'
source_filename = "cecil_test.c"
target datalayout = "e-m:e-p:32:32-i64:64-n32-S128"
target triple = "riscv32-unknown-unknown"

; Function Attrs: nounwind
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) #0 {
entry:
  %and = and i32 %x, 65535
  %conv = trunc i32 %and to i16
  %conv1 = sext i16 %conv to i32
  %and2 = and i32 %y, 65535
  %conv3 = trunc i32 %and2 to i16
  %conv4 = sext i16 %conv3 to i32
  %mul = mul nsw i32 %conv1, %conv4
  %add = add nsw i32 %acc, %mul
  %shr = ashr i32 %x, 16
  %and5 = and i32 %shr, 65535
  %conv6 = trunc i32 %and5 to i16
  %conv7 = sext i16 %conv6 to i32
  %shr8 = ashr i32 %y, 16
  %and9 = and i32 %shr8, 65535
  %conv10 = trunc i32 %and9 to i16
  %conv11 = sext i16 %conv10 to i32
  %mul12 = mul nsw i32 %conv7, %conv11
  %add13 = add nsw i32 %add, %mul12
  ret i32 %add13
}

attributes #0 = { nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="generic-rv32" "target-features"="+32bit,+m,+relax,+xseal5testalucvabs16,+xseal5testalucvabs32,+xseal5testalucvabs8,+xseal5testalucvaddnrsi16,+xseal5testalucvaddnrsi32,+xseal5testalucvaddnrui16,+xseal5testalucvaddnrui32,+xseal5testalucvaddns,+xseal5testalucvaddnu,+xseal5testalucvaddrnrsi16,+xseal5testalucvaddrnrsi32,+xseal5testalucvaddrnrui16,+xseal5testalucvaddrnrui32,+xseal5testalucvaddrns,+xseal5testalucvaddrnu,+xseal5testalucvextbs,+xseal5testalucvextbz,+xseal5testalucvexths,+xseal5testalucvexthz,+xseal5testalucvmaxi1216,+xseal5testalucvmaxi1232,+xseal5testalucvmaxi516,+xseal5testalucvmaxi532,+xseal5testalucvmaxs16,+xseal5testalucvmaxs32,+xseal5testalucvmaxs8,+xseal5testalucvmaxu16,+xseal5testalucvmaxu32,+xseal5testalucvmaxu8,+xseal5testalucvmini1216,+xseal5testalucvmini1232,+xseal5testalucvmini516,+xseal5testalucvmini532,+xseal5testalucvmins16,+xseal5testalucvmins32,+xseal5testalucvmins8,+xseal5testalucvminu16,+xseal5testalucvminu32,+xseal5testalucvminu8,+xseal5testalucvsletsi16,+xseal5testalucvsletsi32,+xseal5testalucvsletui16,+xseal5testalucvsletui32,+xseal5testalucvsubnrsi16,+xseal5testalucvsubnrsi32,+xseal5testalucvsubnrui16,+xseal5testalucvsubnrui32,+xseal5testalucvsubns,+xseal5testalucvsubnu,+xseal5testalucvsubrnrsi16,+xseal5testalucvsubrnrsi32,+xseal5testalucvsubrnrui16,+xseal5testalucvsubrnrui32,+xseal5testalucvsubrns,+xseal5testalucvsubrnu,+xseal5testmaccvmachhns,+xseal5testmaccvmachhnu,+xseal5testmaccvmachhrns,+xseal5testmaccvmachhrnu,+xseal5testmaccvmacns,+xseal5testmaccvmacnu,+xseal5testmaccvmacrns,+xseal5testmaccvmacrnu,+xseal5testmaccvmacsi16,+xseal5testmaccvmacsi32,+xseal5testmaccvmacui16,+xseal5testmaccvmacui32,+xseal5testmaccvmsusi16,+xseal5testmaccvmsusi32,+xseal5testmaccvmsuui16,+xseal5testmaccvmsuui32,+xseal5testmaccvmulhhns,+xseal5testmaccvmulhhnu,+xseal5testmaccvmulhhrns,+xseal5testmaccvmulhhrnu,+xseal5testmaccvmulns,+xseal5testmaccvmulnu,+xseal5testmaccvmulrns,+xseal5testmaccvmulrnu,-a,-c,-d,-e,-experimental-zacas,-experimental-zcmop,-experimental-zfbfmin,-experimental-zicfilp,-experimental-zicfiss,-experimental-zimop,-experimental-ztso,-experimental-zvfbfmin,-experimental-zvfbfwma,-f,-h,-smaia,-smepmp,-ssaia,-svinval,-svnapot,-svpbmt,-v,-xcvalu,-xcvbi,-xcvbitmanip,-xcvelw,-xcvmac,-xcvmem,-xcvsimd,-xsfvcp,-xsfvfnrclipxfqf,-xsfvfwmaccqqq,-xsfvqmaccdod,-xsfvqmaccqoq,-xtheadba,-xtheadbb,-xtheadbs,-xtheadcmo,-xtheadcondmov,-xtheadfmemidx,-xtheadmac,-xtheadmemidx,-xtheadmempair,-xtheadsync,-xtheadvdot,-xventanacondops,-za128rs,-za64rs,-zawrs,-zba,-zbb,-zbc,-zbkb,-zbkc,-zbkx,-zbs,-zca,-zcb,-zcd,-zce,-zcf,-zcmp,-zcmt,-zdinx,-zfa,-zfh,-zfhmin,-zfinx,-zhinx,-zhinxmin,-zic64b,-zicbom,-zicbop,-zicboz,-ziccamoa,-ziccif,-zicclsm,-ziccrse,-zicntr,-zicond,-zicsr,-zifencei,-zihintntl,-zihintpause,-zihpm,-zk,-zkn,-zknd,-zkne,-zknh,-zkr,-zks,-zksed,-zksh,-zkt,-zmmul,-zvbb,-zvbc,-zve32f,-zve32x,-zve64d,-zve64f,-zve64x,-zvfh,-zvfhmin,-zvkb,-zvkg,-zvkn,-zvknc,-zvkned,-zvkng,-zvknha,-zvknhb,-zvks,-zvksc,-zvksed,-zvksg,-zvksh,-zvkt,-zvl1024b,-zvl128b,-zvl16384b,-zvl2048b,-zvl256b,-zvl32768b,-zvl32b,-zvl4096b,-zvl512b,-zvl64b,-zvl65536b,-zvl8192b" }

!llvm.module.flags = !{!0, !1, !2}
!llvm.ident = !{!3}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 1, !"target-abi", !"ilp32"}
!2 = !{i32 8, !"SmallDataLimit", i32 8}
!3 = !{!"clang version 18.1.0rc (https://github.com/llvm/llvm-project.git 1acc4e456481e76822c76c850bad3994d4e04b59)"}
; *** IR Dump After GlobalOptPass on [module] ***
; ModuleID = 'cecil_test.c'
source_filename = "cecil_test.c"
target datalayout = "e-m:e-p:32:32-i64:64-n32-S128"
target triple = "riscv32-unknown-unknown"

; Function Attrs: nounwind
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %and = and i32 %x, 65535
  %conv = trunc i32 %and to i16
  %conv1 = sext i16 %conv to i32
  %and2 = and i32 %y, 65535
  %conv3 = trunc i32 %and2 to i16
  %conv4 = sext i16 %conv3 to i32
  %mul = mul nsw i32 %conv1, %conv4
  %add = add nsw i32 %acc, %mul
  %shr = ashr i32 %x, 16
  %and5 = and i32 %shr, 65535
  %conv6 = trunc i32 %and5 to i16
  %conv7 = sext i16 %conv6 to i32
  %shr8 = ashr i32 %y, 16
  %and9 = and i32 %shr8, 65535
  %conv10 = trunc i32 %and9 to i16
  %conv11 = sext i16 %conv10 to i32
  %mul12 = mul nsw i32 %conv7, %conv11
  %add13 = add nsw i32 %add, %mul12
  ret i32 %add13
}

attributes #0 = { nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="generic-rv32" "target-features"="+32bit,+m,+relax,+xseal5testalucvabs16,+xseal5testalucvabs32,+xseal5testalucvabs8,+xseal5testalucvaddnrsi16,+xseal5testalucvaddnrsi32,+xseal5testalucvaddnrui16,+xseal5testalucvaddnrui32,+xseal5testalucvaddns,+xseal5testalucvaddnu,+xseal5testalucvaddrnrsi16,+xseal5testalucvaddrnrsi32,+xseal5testalucvaddrnrui16,+xseal5testalucvaddrnrui32,+xseal5testalucvaddrns,+xseal5testalucvaddrnu,+xseal5testalucvextbs,+xseal5testalucvextbz,+xseal5testalucvexths,+xseal5testalucvexthz,+xseal5testalucvmaxi1216,+xseal5testalucvmaxi1232,+xseal5testalucvmaxi516,+xseal5testalucvmaxi532,+xseal5testalucvmaxs16,+xseal5testalucvmaxs32,+xseal5testalucvmaxs8,+xseal5testalucvmaxu16,+xseal5testalucvmaxu32,+xseal5testalucvmaxu8,+xseal5testalucvmini1216,+xseal5testalucvmini1232,+xseal5testalucvmini516,+xseal5testalucvmini532,+xseal5testalucvmins16,+xseal5testalucvmins32,+xseal5testalucvmins8,+xseal5testalucvminu16,+xseal5testalucvminu32,+xseal5testalucvminu8,+xseal5testalucvsletsi16,+xseal5testalucvsletsi32,+xseal5testalucvsletui16,+xseal5testalucvsletui32,+xseal5testalucvsubnrsi16,+xseal5testalucvsubnrsi32,+xseal5testalucvsubnrui16,+xseal5testalucvsubnrui32,+xseal5testalucvsubns,+xseal5testalucvsubnu,+xseal5testalucvsubrnrsi16,+xseal5testalucvsubrnrsi32,+xseal5testalucvsubrnrui16,+xseal5testalucvsubrnrui32,+xseal5testalucvsubrns,+xseal5testalucvsubrnu,+xseal5testmaccvmachhns,+xseal5testmaccvmachhnu,+xseal5testmaccvmachhrns,+xseal5testmaccvmachhrnu,+xseal5testmaccvmacns,+xseal5testmaccvmacnu,+xseal5testmaccvmacrns,+xseal5testmaccvmacrnu,+xseal5testmaccvmacsi16,+xseal5testmaccvmacsi32,+xseal5testmaccvmacui16,+xseal5testmaccvmacui32,+xseal5testmaccvmsusi16,+xseal5testmaccvmsusi32,+xseal5testmaccvmsuui16,+xseal5testmaccvmsuui32,+xseal5testmaccvmulhhns,+xseal5testmaccvmulhhnu,+xseal5testmaccvmulhhrns,+xseal5testmaccvmulhhrnu,+xseal5testmaccvmulns,+xseal5testmaccvmulnu,+xseal5testmaccvmulrns,+xseal5testmaccvmulrnu,-a,-c,-d,-e,-experimental-zacas,-experimental-zcmop,-experimental-zfbfmin,-experimental-zicfilp,-experimental-zicfiss,-experimental-zimop,-experimental-ztso,-experimental-zvfbfmin,-experimental-zvfbfwma,-f,-h,-smaia,-smepmp,-ssaia,-svinval,-svnapot,-svpbmt,-v,-xcvalu,-xcvbi,-xcvbitmanip,-xcvelw,-xcvmac,-xcvmem,-xcvsimd,-xsfvcp,-xsfvfnrclipxfqf,-xsfvfwmaccqqq,-xsfvqmaccdod,-xsfvqmaccqoq,-xtheadba,-xtheadbb,-xtheadbs,-xtheadcmo,-xtheadcondmov,-xtheadfmemidx,-xtheadmac,-xtheadmemidx,-xtheadmempair,-xtheadsync,-xtheadvdot,-xventanacondops,-za128rs,-za64rs,-zawrs,-zba,-zbb,-zbc,-zbkb,-zbkc,-zbkx,-zbs,-zca,-zcb,-zcd,-zce,-zcf,-zcmp,-zcmt,-zdinx,-zfa,-zfh,-zfhmin,-zfinx,-zhinx,-zhinxmin,-zic64b,-zicbom,-zicbop,-zicboz,-ziccamoa,-ziccif,-zicclsm,-ziccrse,-zicntr,-zicond,-zicsr,-zifencei,-zihintntl,-zihintpause,-zihpm,-zk,-zkn,-zknd,-zkne,-zknh,-zkr,-zks,-zksed,-zksh,-zkt,-zmmul,-zvbb,-zvbc,-zve32f,-zve32x,-zve64d,-zve64f,-zve64x,-zvfh,-zvfhmin,-zvkb,-zvkg,-zvkn,-zvknc,-zvkned,-zvkng,-zvknha,-zvknhb,-zvks,-zvksc,-zvksed,-zvksg,-zvksh,-zvkt,-zvl1024b,-zvl128b,-zvl16384b,-zvl2048b,-zvl256b,-zvl32768b,-zvl32b,-zvl4096b,-zvl512b,-zvl64b,-zvl65536b,-zvl8192b" }

!llvm.module.flags = !{!0, !1, !2}
!llvm.ident = !{!3}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 1, !"target-abi", !"ilp32"}
!2 = !{i32 8, !"SmallDataLimit", i32 8}
!3 = !{!"clang version 18.1.0rc (https://github.com/llvm/llvm-project.git 1acc4e456481e76822c76c850bad3994d4e04b59)"}
; *** IR Dump Before PromotePass on test_macs32_v2i16 ***
; Function Attrs: nounwind
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %and = and i32 %x, 65535
  %conv = trunc i32 %and to i16
  %conv1 = sext i16 %conv to i32
  %and2 = and i32 %y, 65535
  %conv3 = trunc i32 %and2 to i16
  %conv4 = sext i16 %conv3 to i32
  %mul = mul nsw i32 %conv1, %conv4
  %add = add nsw i32 %acc, %mul
  %shr = ashr i32 %x, 16
  %and5 = and i32 %shr, 65535
  %conv6 = trunc i32 %and5 to i16
  %conv7 = sext i16 %conv6 to i32
  %shr8 = ashr i32 %y, 16
  %and9 = and i32 %shr8, 65535
  %conv10 = trunc i32 %and9 to i16
  %conv11 = sext i16 %conv10 to i32
  %mul12 = mul nsw i32 %conv7, %conv11
  %add13 = add nsw i32 %add, %mul12
  ret i32 %add13
}
; *** IR Dump After PromotePass on test_macs32_v2i16 ***
; Function Attrs: nounwind
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %and = and i32 %x, 65535
  %conv = trunc i32 %and to i16
  %conv1 = sext i16 %conv to i32
  %and2 = and i32 %y, 65535
  %conv3 = trunc i32 %and2 to i16
  %conv4 = sext i16 %conv3 to i32
  %mul = mul nsw i32 %conv1, %conv4
  %add = add nsw i32 %acc, %mul
  %shr = ashr i32 %x, 16
  %and5 = and i32 %shr, 65535
  %conv6 = trunc i32 %and5 to i16
  %conv7 = sext i16 %conv6 to i32
  %shr8 = ashr i32 %y, 16
  %and9 = and i32 %shr8, 65535
  %conv10 = trunc i32 %and9 to i16
  %conv11 = sext i16 %conv10 to i32
  %mul12 = mul nsw i32 %conv7, %conv11
  %add13 = add nsw i32 %add, %mul12
  ret i32 %add13
}
; *** IR Dump Before InstCombinePass on test_macs32_v2i16 ***
; Function Attrs: nounwind
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %and = and i32 %x, 65535
  %conv = trunc i32 %and to i16
  %conv1 = sext i16 %conv to i32
  %and2 = and i32 %y, 65535
  %conv3 = trunc i32 %and2 to i16
  %conv4 = sext i16 %conv3 to i32
  %mul = mul nsw i32 %conv1, %conv4
  %add = add nsw i32 %acc, %mul
  %shr = ashr i32 %x, 16
  %and5 = and i32 %shr, 65535
  %conv6 = trunc i32 %and5 to i16
  %conv7 = sext i16 %conv6 to i32
  %shr8 = ashr i32 %y, 16
  %and9 = and i32 %shr8, 65535
  %conv10 = trunc i32 %and9 to i16
  %conv11 = sext i16 %conv10 to i32
  %mul12 = mul nsw i32 %conv7, %conv11
  %add13 = add nsw i32 %add, %mul12
  ret i32 %add13
}


INSTCOMBINE ITERATION #1 on test_macs32_v2i16
ADD:   ret i32 %add13
ADD:   %add13 = add nsw i32 %add, %mul12
ADD:   %mul12 = mul nsw i32 %conv7, %conv11
ADD:   %conv11 = sext i16 %conv10 to i32
ADD:   %conv10 = trunc i32 %and9 to i16
ADD:   %and9 = and i32 %shr8, 65535
ADD:   %shr8 = ashr i32 %y, 16
ADD:   %conv7 = sext i16 %conv6 to i32
ADD:   %conv6 = trunc i32 %and5 to i16
ADD:   %and5 = and i32 %shr, 65535
ADD:   %shr = ashr i32 %x, 16
ADD:   %add = add nsw i32 %acc, %mul
ADD:   %mul = mul nsw i32 %conv1, %conv4
ADD:   %conv4 = sext i16 %conv3 to i32
ADD:   %conv3 = trunc i32 %and2 to i16
ADD:   %and2 = and i32 %y, 65535
ADD:   %conv1 = sext i16 %conv to i32
ADD:   %conv = trunc i32 %and to i16
ADD:   %and = and i32 %x, 65535
IC: Visiting:   %and = and i32 %x, 65535
IC: Visiting:   %conv = trunc i32 %and to i16
ADD DEFERRED:   %and = and i32 %x, 65535
IC: Mod =   %conv = trunc i32 %and to i16
    New =   %conv = trunc i32 %x to i16
ADD:   %conv = trunc i32 %x to i16
IC: ERASE   %and = and i32 %x, 65535
IC: Visiting:   %conv = trunc i32 %x to i16
IC: Visiting:   %conv1 = sext i16 %conv to i32
ICE: EvaluateInDifferentType converting expression type to avoid sign extend:   %conv1 = sext i16 %conv to i32
ADD DEFERRED:   %sext = shl i32 %x, 16
IC: Old =   %conv1 = sext i16 %conv to i32
    New =   <badref> = ashr i32 %sext, 16
ADD:   %conv1 = ashr i32 %sext, 16
IC: ERASE   %0 = sext i16 %conv to i32
ADD DEFERRED:   %conv = trunc i32 %x to i16
IC: ERASE   %conv = trunc i32 %x to i16
ADD:   %sext = shl i32 %x, 16
IC: Visiting:   %sext = shl i32 %x, 16
IC: Visiting:   %conv1 = ashr i32 %sext, 16
IC: Mod =   %conv1 = ashr i32 %sext, 16
    New =   %conv1 = ashr exact i32 %sext, 16
ADD:   %conv1 = ashr exact i32 %sext, 16
IC: Visiting:   %conv1 = ashr exact i32 %sext, 16
IC: Visiting:   %and2 = and i32 %y, 65535
IC: Visiting:   %conv3 = trunc i32 %and2 to i16
ADD DEFERRED:   %and2 = and i32 %y, 65535
IC: Mod =   %conv3 = trunc i32 %and2 to i16
    New =   %conv3 = trunc i32 %y to i16
ADD:   %conv3 = trunc i32 %y to i16
IC: ERASE   %and2 = and i32 %y, 65535
IC: Visiting:   %conv3 = trunc i32 %y to i16
IC: Visiting:   %conv4 = sext i16 %conv3 to i32
ICE: EvaluateInDifferentType converting expression type to avoid sign extend:   %conv4 = sext i16 %conv3 to i32
ADD DEFERRED:   %sext18 = shl i32 %y, 16
IC: Old =   %conv4 = sext i16 %conv3 to i32
    New =   <badref> = ashr i32 %sext18, 16
ADD:   %conv4 = ashr i32 %sext18, 16
IC: ERASE   %0 = sext i16 %conv3 to i32
ADD DEFERRED:   %conv3 = trunc i32 %y to i16
IC: ERASE   %conv3 = trunc i32 %y to i16
ADD:   %sext18 = shl i32 %y, 16
IC: Visiting:   %sext18 = shl i32 %y, 16
IC: Visiting:   %conv4 = ashr i32 %sext18, 16
IC: Mod =   %conv4 = ashr i32 %sext18, 16
    New =   %conv4 = ashr exact i32 %sext18, 16
ADD:   %conv4 = ashr exact i32 %sext18, 16
IC: Visiting:   %conv4 = ashr exact i32 %sext18, 16
IC: Visiting:   %mul = mul nsw i32 %conv1, %conv4
IC: Visiting:   %add = add nsw i32 %acc, %mul
IC: Mod =   %add = add nsw i32 %acc, %mul
    New =   %add = add nsw i32 %mul, %acc
ADD:   %add = add nsw i32 %mul, %acc
IC: Visiting:   %add = add nsw i32 %mul, %acc
IC: Visiting:   %shr = ashr i32 %x, 16
IC: Visiting:   %and5 = and i32 %shr, 65535
ADD DEFERRED:   %shr = lshr i32 %x, 16
ADD DEFERRED:   %0 = ashr i32 %x, 16
IC: Mod =   %and5 = and i32 %shr, 65535
    New =   %and5 = and i32 %shr, 65535
ADD:   %and5 = and i32 %shr, 65535
IC: ERASE   %0 = ashr i32 %x, 16
ADD:   %shr = lshr i32 %x, 16
IC: Visiting:   %shr = lshr i32 %x, 16
IC: Visiting:   %and5 = and i32 %shr, 65535
IC: Replacing   %and5 = and i32 %shr, 65535
    with   %shr = lshr i32 %x, 16
IC: Mod =   %and5 = and i32 %shr, 65535
    New =   %and5 = and i32 %shr, 65535
IC: ERASE   %and5 = and i32 %shr, 65535
ADD DEFERRED:   %shr = lshr i32 %x, 16
ADD DEFERRED:   %conv6 = trunc i32 %shr to i16
ADD:   %shr = lshr i32 %x, 16
IC: Visiting:   %shr = lshr i32 %x, 16
IC: Visiting:   %conv6 = trunc i32 %shr to i16
IC: Visiting:   %conv7 = sext i16 %conv6 to i32
ICE: EvaluateInDifferentType converting expression type to avoid sign extend:   %conv7 = sext i16 %conv6 to i32
ADD DEFERRED:   %sext19 = shl i32 %shr, 16
IC: Old =   %conv7 = sext i16 %conv6 to i32
    New =   <badref> = ashr i32 %sext19, 16
ADD:   %conv7 = ashr i32 %sext19, 16
IC: ERASE   %0 = sext i16 %conv6 to i32
ADD DEFERRED:   %conv6 = trunc i32 %shr to i16
IC: ERASE   %conv6 = trunc i32 %shr to i16
ADD DEFERRED:   %shr = lshr i32 %x, 16
ADD:   %shr = lshr i32 %x, 16
ADD:   %sext19 = shl i32 %shr, 16
IC: Visiting:   %sext19 = shl i32 %shr, 16
ICE: GetShiftedValue propagating shift through expression to eliminate shift:
  IN:   %shr = lshr i32 %x, 16
  SH:   %sext19 = shl i32 %shr, 16
ADD DEFERRED:   %0 = and i32 %x, -65536
IC: Replacing   %sext19 = shl i32 %0, 16
    with   %shr = and i32 %x, -65536
IC: Mod =   %sext19 = shl i32 %shr, 16
    New =   %sext19 = shl i32 %0, 16
IC: ERASE   %sext19 = shl i32 %0, 16
ADD DEFERRED:   %0 = lshr i32 %x, 16
IC: ERASE   %0 = lshr i32 %x, 16
ADD:   %shr = and i32 %x, -65536
IC: Visiting:   %shr = and i32 %x, -65536
IC: Visiting:   %conv7 = ashr i32 %shr, 16
ADD DEFERRED:   %shr = and i32 %x, -65536
IC: Mod =   %conv7 = ashr i32 %shr, 16
    New =   %conv7 = ashr i32 %x, 16
ADD:   %conv7 = ashr i32 %x, 16
IC: ERASE   %shr = and i32 %x, -65536
IC: Visiting:   %conv7 = ashr i32 %x, 16
IC: Visiting:   %shr8 = ashr i32 %y, 16
IC: Visiting:   %and9 = and i32 %shr8, 65535
ADD DEFERRED:   %shr8 = lshr i32 %y, 16
ADD DEFERRED:   %0 = ashr i32 %y, 16
IC: Mod =   %and9 = and i32 %shr8, 65535
    New =   %and9 = and i32 %shr8, 65535
ADD:   %and9 = and i32 %shr8, 65535
IC: ERASE   %0 = ashr i32 %y, 16
ADD:   %shr8 = lshr i32 %y, 16
IC: Visiting:   %shr8 = lshr i32 %y, 16
IC: Visiting:   %and9 = and i32 %shr8, 65535
IC: Replacing   %and9 = and i32 %shr8, 65535
    with   %shr8 = lshr i32 %y, 16
IC: Mod =   %and9 = and i32 %shr8, 65535
    New =   %and9 = and i32 %shr8, 65535
IC: ERASE   %and9 = and i32 %shr8, 65535
ADD DEFERRED:   %shr8 = lshr i32 %y, 16
ADD DEFERRED:   %conv10 = trunc i32 %shr8 to i16
ADD:   %shr8 = lshr i32 %y, 16
IC: Visiting:   %shr8 = lshr i32 %y, 16
IC: Visiting:   %conv10 = trunc i32 %shr8 to i16
IC: Visiting:   %conv11 = sext i16 %conv10 to i32
ICE: EvaluateInDifferentType converting expression type to avoid sign extend:   %conv11 = sext i16 %conv10 to i32
ADD DEFERRED:   %sext20 = shl i32 %shr8, 16
IC: Old =   %conv11 = sext i16 %conv10 to i32
    New =   <badref> = ashr i32 %sext20, 16
ADD:   %conv11 = ashr i32 %sext20, 16
IC: ERASE   %0 = sext i16 %conv10 to i32
ADD DEFERRED:   %conv10 = trunc i32 %shr8 to i16
IC: ERASE   %conv10 = trunc i32 %shr8 to i16
ADD DEFERRED:   %shr8 = lshr i32 %y, 16
ADD:   %shr8 = lshr i32 %y, 16
ADD:   %sext20 = shl i32 %shr8, 16
IC: Visiting:   %sext20 = shl i32 %shr8, 16
ICE: GetShiftedValue propagating shift through expression to eliminate shift:
  IN:   %shr8 = lshr i32 %y, 16
  SH:   %sext20 = shl i32 %shr8, 16
ADD DEFERRED:   %0 = and i32 %y, -65536
IC: Replacing   %sext20 = shl i32 %0, 16
    with   %shr8 = and i32 %y, -65536
IC: Mod =   %sext20 = shl i32 %shr8, 16
    New =   %sext20 = shl i32 %0, 16
IC: ERASE   %sext20 = shl i32 %0, 16
ADD DEFERRED:   %0 = lshr i32 %y, 16
IC: ERASE   %0 = lshr i32 %y, 16
ADD:   %shr8 = and i32 %y, -65536
IC: Visiting:   %shr8 = and i32 %y, -65536
IC: Visiting:   %conv11 = ashr i32 %shr8, 16
ADD DEFERRED:   %shr8 = and i32 %y, -65536
IC: Mod =   %conv11 = ashr i32 %shr8, 16
    New =   %conv11 = ashr i32 %y, 16
ADD:   %conv11 = ashr i32 %y, 16
IC: ERASE   %shr8 = and i32 %y, -65536
IC: Visiting:   %conv11 = ashr i32 %y, 16
IC: Visiting:   %mul12 = mul nsw i32 %conv7, %conv11
IC: Visiting:   %add13 = add nsw i32 %add, %mul12
IC: Visiting:   ret i32 %add13


[IC] Iteration limit #1 on test_macs32_v2i16 reached; stopping without verifying fixpoint
; *** IR Dump After InstCombinePass on test_macs32_v2i16 ***
; Function Attrs: nounwind
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv1, %conv4
  %add = add nsw i32 %mul, %acc
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv7, %conv11
  %add13 = add nsw i32 %add, %mul12
  ret i32 %add13
}
; *** IR Dump Before SimplifyCFGPass on test_macs32_v2i16 ***
; Function Attrs: nounwind
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv1, %conv4
  %add = add nsw i32 %mul, %acc
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv7, %conv11
  %add13 = add nsw i32 %add, %mul12
  ret i32 %add13
}
; *** IR Dump After SimplifyCFGPass on test_macs32_v2i16 ***
; Function Attrs: nounwind
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv1, %conv4
  %add = add nsw i32 %mul, %acc
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv7, %conv11
  %add13 = add nsw i32 %add, %mul12
  ret i32 %add13
}
; *** IR Dump Before AlwaysInlinerPass on [module] ***
; ModuleID = 'cecil_test.c'
source_filename = "cecil_test.c"
target datalayout = "e-m:e-p:32:32-i64:64-n32-S128"
target triple = "riscv32-unknown-unknown"

; Function Attrs: nounwind
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv1, %conv4
  %add = add nsw i32 %mul, %acc
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv7, %conv11
  %add13 = add nsw i32 %add, %mul12
  ret i32 %add13
}

attributes #0 = { nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="generic-rv32" "target-features"="+32bit,+m,+relax,+xseal5testalucvabs16,+xseal5testalucvabs32,+xseal5testalucvabs8,+xseal5testalucvaddnrsi16,+xseal5testalucvaddnrsi32,+xseal5testalucvaddnrui16,+xseal5testalucvaddnrui32,+xseal5testalucvaddns,+xseal5testalucvaddnu,+xseal5testalucvaddrnrsi16,+xseal5testalucvaddrnrsi32,+xseal5testalucvaddrnrui16,+xseal5testalucvaddrnrui32,+xseal5testalucvaddrns,+xseal5testalucvaddrnu,+xseal5testalucvextbs,+xseal5testalucvextbz,+xseal5testalucvexths,+xseal5testalucvexthz,+xseal5testalucvmaxi1216,+xseal5testalucvmaxi1232,+xseal5testalucvmaxi516,+xseal5testalucvmaxi532,+xseal5testalucvmaxs16,+xseal5testalucvmaxs32,+xseal5testalucvmaxs8,+xseal5testalucvmaxu16,+xseal5testalucvmaxu32,+xseal5testalucvmaxu8,+xseal5testalucvmini1216,+xseal5testalucvmini1232,+xseal5testalucvmini516,+xseal5testalucvmini532,+xseal5testalucvmins16,+xseal5testalucvmins32,+xseal5testalucvmins8,+xseal5testalucvminu16,+xseal5testalucvminu32,+xseal5testalucvminu8,+xseal5testalucvsletsi16,+xseal5testalucvsletsi32,+xseal5testalucvsletui16,+xseal5testalucvsletui32,+xseal5testalucvsubnrsi16,+xseal5testalucvsubnrsi32,+xseal5testalucvsubnrui16,+xseal5testalucvsubnrui32,+xseal5testalucvsubns,+xseal5testalucvsubnu,+xseal5testalucvsubrnrsi16,+xseal5testalucvsubrnrsi32,+xseal5testalucvsubrnrui16,+xseal5testalucvsubrnrui32,+xseal5testalucvsubrns,+xseal5testalucvsubrnu,+xseal5testmaccvmachhns,+xseal5testmaccvmachhnu,+xseal5testmaccvmachhrns,+xseal5testmaccvmachhrnu,+xseal5testmaccvmacns,+xseal5testmaccvmacnu,+xseal5testmaccvmacrns,+xseal5testmaccvmacrnu,+xseal5testmaccvmacsi16,+xseal5testmaccvmacsi32,+xseal5testmaccvmacui16,+xseal5testmaccvmacui32,+xseal5testmaccvmsusi16,+xseal5testmaccvmsusi32,+xseal5testmaccvmsuui16,+xseal5testmaccvmsuui32,+xseal5testmaccvmulhhns,+xseal5testmaccvmulhhnu,+xseal5testmaccvmulhhrns,+xseal5testmaccvmulhhrnu,+xseal5testmaccvmulns,+xseal5testmaccvmulnu,+xseal5testmaccvmulrns,+xseal5testmaccvmulrnu,-a,-c,-d,-e,-experimental-zacas,-experimental-zcmop,-experimental-zfbfmin,-experimental-zicfilp,-experimental-zicfiss,-experimental-zimop,-experimental-ztso,-experimental-zvfbfmin,-experimental-zvfbfwma,-f,-h,-smaia,-smepmp,-ssaia,-svinval,-svnapot,-svpbmt,-v,-xcvalu,-xcvbi,-xcvbitmanip,-xcvelw,-xcvmac,-xcvmem,-xcvsimd,-xsfvcp,-xsfvfnrclipxfqf,-xsfvfwmaccqqq,-xsfvqmaccdod,-xsfvqmaccqoq,-xtheadba,-xtheadbb,-xtheadbs,-xtheadcmo,-xtheadcondmov,-xtheadfmemidx,-xtheadmac,-xtheadmemidx,-xtheadmempair,-xtheadsync,-xtheadvdot,-xventanacondops,-za128rs,-za64rs,-zawrs,-zba,-zbb,-zbc,-zbkb,-zbkc,-zbkx,-zbs,-zca,-zcb,-zcd,-zce,-zcf,-zcmp,-zcmt,-zdinx,-zfa,-zfh,-zfhmin,-zfinx,-zhinx,-zhinxmin,-zic64b,-zicbom,-zicbop,-zicboz,-ziccamoa,-ziccif,-zicclsm,-ziccrse,-zicntr,-zicond,-zicsr,-zifencei,-zihintntl,-zihintpause,-zihpm,-zk,-zkn,-zknd,-zkne,-zknh,-zkr,-zks,-zksed,-zksh,-zkt,-zmmul,-zvbb,-zvbc,-zve32f,-zve32x,-zve64d,-zve64f,-zve64x,-zvfh,-zvfhmin,-zvkb,-zvkg,-zvkn,-zvknc,-zvkned,-zvkng,-zvknha,-zvknhb,-zvks,-zvksc,-zvksed,-zvksg,-zvksh,-zvkt,-zvl1024b,-zvl128b,-zvl16384b,-zvl2048b,-zvl256b,-zvl32768b,-zvl32b,-zvl4096b,-zvl512b,-zvl64b,-zvl65536b,-zvl8192b" }

!llvm.module.flags = !{!0, !1, !2}
!llvm.ident = !{!3}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 1, !"target-abi", !"ilp32"}
!2 = !{i32 8, !"SmallDataLimit", i32 8}
!3 = !{!"clang version 18.1.0rc (https://github.com/llvm/llvm-project.git 1acc4e456481e76822c76c850bad3994d4e04b59)"}
; *** IR Dump After AlwaysInlinerPass on [module] ***
; ModuleID = 'cecil_test.c'
source_filename = "cecil_test.c"
target datalayout = "e-m:e-p:32:32-i64:64-n32-S128"
target triple = "riscv32-unknown-unknown"

; Function Attrs: nounwind
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv1, %conv4
  %add = add nsw i32 %mul, %acc
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv7, %conv11
  %add13 = add nsw i32 %add, %mul12
  ret i32 %add13
}

attributes #0 = { nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="generic-rv32" "target-features"="+32bit,+m,+relax,+xseal5testalucvabs16,+xseal5testalucvabs32,+xseal5testalucvabs8,+xseal5testalucvaddnrsi16,+xseal5testalucvaddnrsi32,+xseal5testalucvaddnrui16,+xseal5testalucvaddnrui32,+xseal5testalucvaddns,+xseal5testalucvaddnu,+xseal5testalucvaddrnrsi16,+xseal5testalucvaddrnrsi32,+xseal5testalucvaddrnrui16,+xseal5testalucvaddrnrui32,+xseal5testalucvaddrns,+xseal5testalucvaddrnu,+xseal5testalucvextbs,+xseal5testalucvextbz,+xseal5testalucvexths,+xseal5testalucvexthz,+xseal5testalucvmaxi1216,+xseal5testalucvmaxi1232,+xseal5testalucvmaxi516,+xseal5testalucvmaxi532,+xseal5testalucvmaxs16,+xseal5testalucvmaxs32,+xseal5testalucvmaxs8,+xseal5testalucvmaxu16,+xseal5testalucvmaxu32,+xseal5testalucvmaxu8,+xseal5testalucvmini1216,+xseal5testalucvmini1232,+xseal5testalucvmini516,+xseal5testalucvmini532,+xseal5testalucvmins16,+xseal5testalucvmins32,+xseal5testalucvmins8,+xseal5testalucvminu16,+xseal5testalucvminu32,+xseal5testalucvminu8,+xseal5testalucvsletsi16,+xseal5testalucvsletsi32,+xseal5testalucvsletui16,+xseal5testalucvsletui32,+xseal5testalucvsubnrsi16,+xseal5testalucvsubnrsi32,+xseal5testalucvsubnrui16,+xseal5testalucvsubnrui32,+xseal5testalucvsubns,+xseal5testalucvsubnu,+xseal5testalucvsubrnrsi16,+xseal5testalucvsubrnrsi32,+xseal5testalucvsubrnrui16,+xseal5testalucvsubrnrui32,+xseal5testalucvsubrns,+xseal5testalucvsubrnu,+xseal5testmaccvmachhns,+xseal5testmaccvmachhnu,+xseal5testmaccvmachhrns,+xseal5testmaccvmachhrnu,+xseal5testmaccvmacns,+xseal5testmaccvmacnu,+xseal5testmaccvmacrns,+xseal5testmaccvmacrnu,+xseal5testmaccvmacsi16,+xseal5testmaccvmacsi32,+xseal5testmaccvmacui16,+xseal5testmaccvmacui32,+xseal5testmaccvmsusi16,+xseal5testmaccvmsusi32,+xseal5testmaccvmsuui16,+xseal5testmaccvmsuui32,+xseal5testmaccvmulhhns,+xseal5testmaccvmulhhnu,+xseal5testmaccvmulhhrns,+xseal5testmaccvmulhhrnu,+xseal5testmaccvmulns,+xseal5testmaccvmulnu,+xseal5testmaccvmulrns,+xseal5testmaccvmulrnu,-a,-c,-d,-e,-experimental-zacas,-experimental-zcmop,-experimental-zfbfmin,-experimental-zicfilp,-experimental-zicfiss,-experimental-zimop,-experimental-ztso,-experimental-zvfbfmin,-experimental-zvfbfwma,-f,-h,-smaia,-smepmp,-ssaia,-svinval,-svnapot,-svpbmt,-v,-xcvalu,-xcvbi,-xcvbitmanip,-xcvelw,-xcvmac,-xcvmem,-xcvsimd,-xsfvcp,-xsfvfnrclipxfqf,-xsfvfwmaccqqq,-xsfvqmaccdod,-xsfvqmaccqoq,-xtheadba,-xtheadbb,-xtheadbs,-xtheadcmo,-xtheadcondmov,-xtheadfmemidx,-xtheadmac,-xtheadmemidx,-xtheadmempair,-xtheadsync,-xtheadvdot,-xventanacondops,-za128rs,-za64rs,-zawrs,-zba,-zbb,-zbc,-zbkb,-zbkc,-zbkx,-zbs,-zca,-zcb,-zcd,-zce,-zcf,-zcmp,-zcmt,-zdinx,-zfa,-zfh,-zfhmin,-zfinx,-zhinx,-zhinxmin,-zic64b,-zicbom,-zicbop,-zicboz,-ziccamoa,-ziccif,-zicclsm,-ziccrse,-zicntr,-zicond,-zicsr,-zifencei,-zihintntl,-zihintpause,-zihpm,-zk,-zkn,-zknd,-zkne,-zknh,-zkr,-zks,-zksed,-zksh,-zkt,-zmmul,-zvbb,-zvbc,-zve32f,-zve32x,-zve64d,-zve64f,-zve64x,-zvfh,-zvfhmin,-zvkb,-zvkg,-zvkn,-zvknc,-zvkned,-zvkng,-zvknha,-zvknhb,-zvks,-zvksc,-zvksed,-zvksg,-zvksh,-zvkt,-zvl1024b,-zvl128b,-zvl16384b,-zvl2048b,-zvl256b,-zvl32768b,-zvl32b,-zvl4096b,-zvl512b,-zvl64b,-zvl65536b,-zvl8192b" }

!llvm.module.flags = !{!0, !1, !2}
!llvm.ident = !{!3}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 1, !"target-abi", !"ilp32"}
!2 = !{i32 8, !"SmallDataLimit", i32 8}
!3 = !{!"clang version 18.1.0rc (https://github.com/llvm/llvm-project.git 1acc4e456481e76822c76c850bad3994d4e04b59)"}
Using default inliner heuristic.
; *** IR Dump Before RequireAnalysisPass<llvm::GlobalsAA, llvm::Module> on [module] ***
; ModuleID = 'cecil_test.c'
source_filename = "cecil_test.c"
target datalayout = "e-m:e-p:32:32-i64:64-n32-S128"
target triple = "riscv32-unknown-unknown"

; Function Attrs: nounwind
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv1, %conv4
  %add = add nsw i32 %mul, %acc
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv7, %conv11
  %add13 = add nsw i32 %add, %mul12
  ret i32 %add13
}

attributes #0 = { nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="generic-rv32" "target-features"="+32bit,+m,+relax,+xseal5testalucvabs16,+xseal5testalucvabs32,+xseal5testalucvabs8,+xseal5testalucvaddnrsi16,+xseal5testalucvaddnrsi32,+xseal5testalucvaddnrui16,+xseal5testalucvaddnrui32,+xseal5testalucvaddns,+xseal5testalucvaddnu,+xseal5testalucvaddrnrsi16,+xseal5testalucvaddrnrsi32,+xseal5testalucvaddrnrui16,+xseal5testalucvaddrnrui32,+xseal5testalucvaddrns,+xseal5testalucvaddrnu,+xseal5testalucvextbs,+xseal5testalucvextbz,+xseal5testalucvexths,+xseal5testalucvexthz,+xseal5testalucvmaxi1216,+xseal5testalucvmaxi1232,+xseal5testalucvmaxi516,+xseal5testalucvmaxi532,+xseal5testalucvmaxs16,+xseal5testalucvmaxs32,+xseal5testalucvmaxs8,+xseal5testalucvmaxu16,+xseal5testalucvmaxu32,+xseal5testalucvmaxu8,+xseal5testalucvmini1216,+xseal5testalucvmini1232,+xseal5testalucvmini516,+xseal5testalucvmini532,+xseal5testalucvmins16,+xseal5testalucvmins32,+xseal5testalucvmins8,+xseal5testalucvminu16,+xseal5testalucvminu32,+xseal5testalucvminu8,+xseal5testalucvsletsi16,+xseal5testalucvsletsi32,+xseal5testalucvsletui16,+xseal5testalucvsletui32,+xseal5testalucvsubnrsi16,+xseal5testalucvsubnrsi32,+xseal5testalucvsubnrui16,+xseal5testalucvsubnrui32,+xseal5testalucvsubns,+xseal5testalucvsubnu,+xseal5testalucvsubrnrsi16,+xseal5testalucvsubrnrsi32,+xseal5testalucvsubrnrui16,+xseal5testalucvsubrnrui32,+xseal5testalucvsubrns,+xseal5testalucvsubrnu,+xseal5testmaccvmachhns,+xseal5testmaccvmachhnu,+xseal5testmaccvmachhrns,+xseal5testmaccvmachhrnu,+xseal5testmaccvmacns,+xseal5testmaccvmacnu,+xseal5testmaccvmacrns,+xseal5testmaccvmacrnu,+xseal5testmaccvmacsi16,+xseal5testmaccvmacsi32,+xseal5testmaccvmacui16,+xseal5testmaccvmacui32,+xseal5testmaccvmsusi16,+xseal5testmaccvmsusi32,+xseal5testmaccvmsuui16,+xseal5testmaccvmsuui32,+xseal5testmaccvmulhhns,+xseal5testmaccvmulhhnu,+xseal5testmaccvmulhhrns,+xseal5testmaccvmulhhrnu,+xseal5testmaccvmulns,+xseal5testmaccvmulnu,+xseal5testmaccvmulrns,+xseal5testmaccvmulrnu,-a,-c,-d,-e,-experimental-zacas,-experimental-zcmop,-experimental-zfbfmin,-experimental-zicfilp,-experimental-zicfiss,-experimental-zimop,-experimental-ztso,-experimental-zvfbfmin,-experimental-zvfbfwma,-f,-h,-smaia,-smepmp,-ssaia,-svinval,-svnapot,-svpbmt,-v,-xcvalu,-xcvbi,-xcvbitmanip,-xcvelw,-xcvmac,-xcvmem,-xcvsimd,-xsfvcp,-xsfvfnrclipxfqf,-xsfvfwmaccqqq,-xsfvqmaccdod,-xsfvqmaccqoq,-xtheadba,-xtheadbb,-xtheadbs,-xtheadcmo,-xtheadcondmov,-xtheadfmemidx,-xtheadmac,-xtheadmemidx,-xtheadmempair,-xtheadsync,-xtheadvdot,-xventanacondops,-za128rs,-za64rs,-zawrs,-zba,-zbb,-zbc,-zbkb,-zbkc,-zbkx,-zbs,-zca,-zcb,-zcd,-zce,-zcf,-zcmp,-zcmt,-zdinx,-zfa,-zfh,-zfhmin,-zfinx,-zhinx,-zhinxmin,-zic64b,-zicbom,-zicbop,-zicboz,-ziccamoa,-ziccif,-zicclsm,-ziccrse,-zicntr,-zicond,-zicsr,-zifencei,-zihintntl,-zihintpause,-zihpm,-zk,-zkn,-zknd,-zkne,-zknh,-zkr,-zks,-zksed,-zksh,-zkt,-zmmul,-zvbb,-zvbc,-zve32f,-zve32x,-zve64d,-zve64f,-zve64x,-zvfh,-zvfhmin,-zvkb,-zvkg,-zvkn,-zvknc,-zvkned,-zvkng,-zvknha,-zvknhb,-zvks,-zvksc,-zvksed,-zvksg,-zvksh,-zvkt,-zvl1024b,-zvl128b,-zvl16384b,-zvl2048b,-zvl256b,-zvl32768b,-zvl32b,-zvl4096b,-zvl512b,-zvl64b,-zvl65536b,-zvl8192b" }

!llvm.module.flags = !{!0, !1, !2}
!llvm.ident = !{!3}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 1, !"target-abi", !"ilp32"}
!2 = !{i32 8, !"SmallDataLimit", i32 8}
!3 = !{!"clang version 18.1.0rc (https://github.com/llvm/llvm-project.git 1acc4e456481e76822c76c850bad3994d4e04b59)"}
; *** IR Dump After RequireAnalysisPass<llvm::GlobalsAA, llvm::Module> on [module] ***
; ModuleID = 'cecil_test.c'
source_filename = "cecil_test.c"
target datalayout = "e-m:e-p:32:32-i64:64-n32-S128"
target triple = "riscv32-unknown-unknown"

; Function Attrs: nounwind
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv1, %conv4
  %add = add nsw i32 %mul, %acc
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv7, %conv11
  %add13 = add nsw i32 %add, %mul12
  ret i32 %add13
}

attributes #0 = { nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="generic-rv32" "target-features"="+32bit,+m,+relax,+xseal5testalucvabs16,+xseal5testalucvabs32,+xseal5testalucvabs8,+xseal5testalucvaddnrsi16,+xseal5testalucvaddnrsi32,+xseal5testalucvaddnrui16,+xseal5testalucvaddnrui32,+xseal5testalucvaddns,+xseal5testalucvaddnu,+xseal5testalucvaddrnrsi16,+xseal5testalucvaddrnrsi32,+xseal5testalucvaddrnrui16,+xseal5testalucvaddrnrui32,+xseal5testalucvaddrns,+xseal5testalucvaddrnu,+xseal5testalucvextbs,+xseal5testalucvextbz,+xseal5testalucvexths,+xseal5testalucvexthz,+xseal5testalucvmaxi1216,+xseal5testalucvmaxi1232,+xseal5testalucvmaxi516,+xseal5testalucvmaxi532,+xseal5testalucvmaxs16,+xseal5testalucvmaxs32,+xseal5testalucvmaxs8,+xseal5testalucvmaxu16,+xseal5testalucvmaxu32,+xseal5testalucvmaxu8,+xseal5testalucvmini1216,+xseal5testalucvmini1232,+xseal5testalucvmini516,+xseal5testalucvmini532,+xseal5testalucvmins16,+xseal5testalucvmins32,+xseal5testalucvmins8,+xseal5testalucvminu16,+xseal5testalucvminu32,+xseal5testalucvminu8,+xseal5testalucvsletsi16,+xseal5testalucvsletsi32,+xseal5testalucvsletui16,+xseal5testalucvsletui32,+xseal5testalucvsubnrsi16,+xseal5testalucvsubnrsi32,+xseal5testalucvsubnrui16,+xseal5testalucvsubnrui32,+xseal5testalucvsubns,+xseal5testalucvsubnu,+xseal5testalucvsubrnrsi16,+xseal5testalucvsubrnrsi32,+xseal5testalucvsubrnrui16,+xseal5testalucvsubrnrui32,+xseal5testalucvsubrns,+xseal5testalucvsubrnu,+xseal5testmaccvmachhns,+xseal5testmaccvmachhnu,+xseal5testmaccvmachhrns,+xseal5testmaccvmachhrnu,+xseal5testmaccvmacns,+xseal5testmaccvmacnu,+xseal5testmaccvmacrns,+xseal5testmaccvmacrnu,+xseal5testmaccvmacsi16,+xseal5testmaccvmacsi32,+xseal5testmaccvmacui16,+xseal5testmaccvmacui32,+xseal5testmaccvmsusi16,+xseal5testmaccvmsusi32,+xseal5testmaccvmsuui16,+xseal5testmaccvmsuui32,+xseal5testmaccvmulhhns,+xseal5testmaccvmulhhnu,+xseal5testmaccvmulhhrns,+xseal5testmaccvmulhhrnu,+xseal5testmaccvmulns,+xseal5testmaccvmulnu,+xseal5testmaccvmulrns,+xseal5testmaccvmulrnu,-a,-c,-d,-e,-experimental-zacas,-experimental-zcmop,-experimental-zfbfmin,-experimental-zicfilp,-experimental-zicfiss,-experimental-zimop,-experimental-ztso,-experimental-zvfbfmin,-experimental-zvfbfwma,-f,-h,-smaia,-smepmp,-ssaia,-svinval,-svnapot,-svpbmt,-v,-xcvalu,-xcvbi,-xcvbitmanip,-xcvelw,-xcvmac,-xcvmem,-xcvsimd,-xsfvcp,-xsfvfnrclipxfqf,-xsfvfwmaccqqq,-xsfvqmaccdod,-xsfvqmaccqoq,-xtheadba,-xtheadbb,-xtheadbs,-xtheadcmo,-xtheadcondmov,-xtheadfmemidx,-xtheadmac,-xtheadmemidx,-xtheadmempair,-xtheadsync,-xtheadvdot,-xventanacondops,-za128rs,-za64rs,-zawrs,-zba,-zbb,-zbc,-zbkb,-zbkc,-zbkx,-zbs,-zca,-zcb,-zcd,-zce,-zcf,-zcmp,-zcmt,-zdinx,-zfa,-zfh,-zfhmin,-zfinx,-zhinx,-zhinxmin,-zic64b,-zicbom,-zicbop,-zicboz,-ziccamoa,-ziccif,-zicclsm,-ziccrse,-zicntr,-zicond,-zicsr,-zifencei,-zihintntl,-zihintpause,-zihpm,-zk,-zkn,-zknd,-zkne,-zknh,-zkr,-zks,-zksed,-zksh,-zkt,-zmmul,-zvbb,-zvbc,-zve32f,-zve32x,-zve64d,-zve64f,-zve64x,-zvfh,-zvfhmin,-zvkb,-zvkg,-zvkn,-zvknc,-zvkned,-zvkng,-zvknha,-zvknhb,-zvks,-zvksc,-zvksed,-zvksg,-zvksh,-zvkt,-zvl1024b,-zvl128b,-zvl16384b,-zvl2048b,-zvl256b,-zvl32768b,-zvl32b,-zvl4096b,-zvl512b,-zvl64b,-zvl65536b,-zvl8192b" }

!llvm.module.flags = !{!0, !1, !2}
!llvm.ident = !{!3}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 1, !"target-abi", !"ilp32"}
!2 = !{i32 8, !"SmallDataLimit", i32 8}
!3 = !{!"clang version 18.1.0rc (https://github.com/llvm/llvm-project.git 1acc4e456481e76822c76c850bad3994d4e04b59)"}
; *** IR Dump Before InvalidateAnalysisPass<llvm::AAManager> on test_macs32_v2i16 ***
; Function Attrs: nounwind
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv1, %conv4
  %add = add nsw i32 %mul, %acc
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv7, %conv11
  %add13 = add nsw i32 %add, %mul12
  ret i32 %add13
}
; *** IR Dump After InvalidateAnalysisPass<llvm::AAManager> on test_macs32_v2i16 ***
; Function Attrs: nounwind
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv1, %conv4
  %add = add nsw i32 %mul, %acc
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv7, %conv11
  %add13 = add nsw i32 %add, %mul12
  ret i32 %add13
}
; *** IR Dump Before RequireAnalysisPass<llvm::ProfileSummaryAnalysis, llvm::Module> on [module] ***
; ModuleID = 'cecil_test.c'
source_filename = "cecil_test.c"
target datalayout = "e-m:e-p:32:32-i64:64-n32-S128"
target triple = "riscv32-unknown-unknown"

; Function Attrs: nounwind
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv1, %conv4
  %add = add nsw i32 %mul, %acc
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv7, %conv11
  %add13 = add nsw i32 %add, %mul12
  ret i32 %add13
}

attributes #0 = { nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="generic-rv32" "target-features"="+32bit,+m,+relax,+xseal5testalucvabs16,+xseal5testalucvabs32,+xseal5testalucvabs8,+xseal5testalucvaddnrsi16,+xseal5testalucvaddnrsi32,+xseal5testalucvaddnrui16,+xseal5testalucvaddnrui32,+xseal5testalucvaddns,+xseal5testalucvaddnu,+xseal5testalucvaddrnrsi16,+xseal5testalucvaddrnrsi32,+xseal5testalucvaddrnrui16,+xseal5testalucvaddrnrui32,+xseal5testalucvaddrns,+xseal5testalucvaddrnu,+xseal5testalucvextbs,+xseal5testalucvextbz,+xseal5testalucvexths,+xseal5testalucvexthz,+xseal5testalucvmaxi1216,+xseal5testalucvmaxi1232,+xseal5testalucvmaxi516,+xseal5testalucvmaxi532,+xseal5testalucvmaxs16,+xseal5testalucvmaxs32,+xseal5testalucvmaxs8,+xseal5testalucvmaxu16,+xseal5testalucvmaxu32,+xseal5testalucvmaxu8,+xseal5testalucvmini1216,+xseal5testalucvmini1232,+xseal5testalucvmini516,+xseal5testalucvmini532,+xseal5testalucvmins16,+xseal5testalucvmins32,+xseal5testalucvmins8,+xseal5testalucvminu16,+xseal5testalucvminu32,+xseal5testalucvminu8,+xseal5testalucvsletsi16,+xseal5testalucvsletsi32,+xseal5testalucvsletui16,+xseal5testalucvsletui32,+xseal5testalucvsubnrsi16,+xseal5testalucvsubnrsi32,+xseal5testalucvsubnrui16,+xseal5testalucvsubnrui32,+xseal5testalucvsubns,+xseal5testalucvsubnu,+xseal5testalucvsubrnrsi16,+xseal5testalucvsubrnrsi32,+xseal5testalucvsubrnrui16,+xseal5testalucvsubrnrui32,+xseal5testalucvsubrns,+xseal5testalucvsubrnu,+xseal5testmaccvmachhns,+xseal5testmaccvmachhnu,+xseal5testmaccvmachhrns,+xseal5testmaccvmachhrnu,+xseal5testmaccvmacns,+xseal5testmaccvmacnu,+xseal5testmaccvmacrns,+xseal5testmaccvmacrnu,+xseal5testmaccvmacsi16,+xseal5testmaccvmacsi32,+xseal5testmaccvmacui16,+xseal5testmaccvmacui32,+xseal5testmaccvmsusi16,+xseal5testmaccvmsusi32,+xseal5testmaccvmsuui16,+xseal5testmaccvmsuui32,+xseal5testmaccvmulhhns,+xseal5testmaccvmulhhnu,+xseal5testmaccvmulhhrns,+xseal5testmaccvmulhhrnu,+xseal5testmaccvmulns,+xseal5testmaccvmulnu,+xseal5testmaccvmulrns,+xseal5testmaccvmulrnu,-a,-c,-d,-e,-experimental-zacas,-experimental-zcmop,-experimental-zfbfmin,-experimental-zicfilp,-experimental-zicfiss,-experimental-zimop,-experimental-ztso,-experimental-zvfbfmin,-experimental-zvfbfwma,-f,-h,-smaia,-smepmp,-ssaia,-svinval,-svnapot,-svpbmt,-v,-xcvalu,-xcvbi,-xcvbitmanip,-xcvelw,-xcvmac,-xcvmem,-xcvsimd,-xsfvcp,-xsfvfnrclipxfqf,-xsfvfwmaccqqq,-xsfvqmaccdod,-xsfvqmaccqoq,-xtheadba,-xtheadbb,-xtheadbs,-xtheadcmo,-xtheadcondmov,-xtheadfmemidx,-xtheadmac,-xtheadmemidx,-xtheadmempair,-xtheadsync,-xtheadvdot,-xventanacondops,-za128rs,-za64rs,-zawrs,-zba,-zbb,-zbc,-zbkb,-zbkc,-zbkx,-zbs,-zca,-zcb,-zcd,-zce,-zcf,-zcmp,-zcmt,-zdinx,-zfa,-zfh,-zfhmin,-zfinx,-zhinx,-zhinxmin,-zic64b,-zicbom,-zicbop,-zicboz,-ziccamoa,-ziccif,-zicclsm,-ziccrse,-zicntr,-zicond,-zicsr,-zifencei,-zihintntl,-zihintpause,-zihpm,-zk,-zkn,-zknd,-zkne,-zknh,-zkr,-zks,-zksed,-zksh,-zkt,-zmmul,-zvbb,-zvbc,-zve32f,-zve32x,-zve64d,-zve64f,-zve64x,-zvfh,-zvfhmin,-zvkb,-zvkg,-zvkn,-zvknc,-zvkned,-zvkng,-zvknha,-zvknhb,-zvks,-zvksc,-zvksed,-zvksg,-zvksh,-zvkt,-zvl1024b,-zvl128b,-zvl16384b,-zvl2048b,-zvl256b,-zvl32768b,-zvl32b,-zvl4096b,-zvl512b,-zvl64b,-zvl65536b,-zvl8192b" }

!llvm.module.flags = !{!0, !1, !2}
!llvm.ident = !{!3}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 1, !"target-abi", !"ilp32"}
!2 = !{i32 8, !"SmallDataLimit", i32 8}
!3 = !{!"clang version 18.1.0rc (https://github.com/llvm/llvm-project.git 1acc4e456481e76822c76c850bad3994d4e04b59)"}
; *** IR Dump After RequireAnalysisPass<llvm::ProfileSummaryAnalysis, llvm::Module> on [module] ***
; ModuleID = 'cecil_test.c'
source_filename = "cecil_test.c"
target datalayout = "e-m:e-p:32:32-i64:64-n32-S128"
target triple = "riscv32-unknown-unknown"

; Function Attrs: nounwind
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv1, %conv4
  %add = add nsw i32 %mul, %acc
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv7, %conv11
  %add13 = add nsw i32 %add, %mul12
  ret i32 %add13
}

attributes #0 = { nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="generic-rv32" "target-features"="+32bit,+m,+relax,+xseal5testalucvabs16,+xseal5testalucvabs32,+xseal5testalucvabs8,+xseal5testalucvaddnrsi16,+xseal5testalucvaddnrsi32,+xseal5testalucvaddnrui16,+xseal5testalucvaddnrui32,+xseal5testalucvaddns,+xseal5testalucvaddnu,+xseal5testalucvaddrnrsi16,+xseal5testalucvaddrnrsi32,+xseal5testalucvaddrnrui16,+xseal5testalucvaddrnrui32,+xseal5testalucvaddrns,+xseal5testalucvaddrnu,+xseal5testalucvextbs,+xseal5testalucvextbz,+xseal5testalucvexths,+xseal5testalucvexthz,+xseal5testalucvmaxi1216,+xseal5testalucvmaxi1232,+xseal5testalucvmaxi516,+xseal5testalucvmaxi532,+xseal5testalucvmaxs16,+xseal5testalucvmaxs32,+xseal5testalucvmaxs8,+xseal5testalucvmaxu16,+xseal5testalucvmaxu32,+xseal5testalucvmaxu8,+xseal5testalucvmini1216,+xseal5testalucvmini1232,+xseal5testalucvmini516,+xseal5testalucvmini532,+xseal5testalucvmins16,+xseal5testalucvmins32,+xseal5testalucvmins8,+xseal5testalucvminu16,+xseal5testalucvminu32,+xseal5testalucvminu8,+xseal5testalucvsletsi16,+xseal5testalucvsletsi32,+xseal5testalucvsletui16,+xseal5testalucvsletui32,+xseal5testalucvsubnrsi16,+xseal5testalucvsubnrsi32,+xseal5testalucvsubnrui16,+xseal5testalucvsubnrui32,+xseal5testalucvsubns,+xseal5testalucvsubnu,+xseal5testalucvsubrnrsi16,+xseal5testalucvsubrnrsi32,+xseal5testalucvsubrnrui16,+xseal5testalucvsubrnrui32,+xseal5testalucvsubrns,+xseal5testalucvsubrnu,+xseal5testmaccvmachhns,+xseal5testmaccvmachhnu,+xseal5testmaccvmachhrns,+xseal5testmaccvmachhrnu,+xseal5testmaccvmacns,+xseal5testmaccvmacnu,+xseal5testmaccvmacrns,+xseal5testmaccvmacrnu,+xseal5testmaccvmacsi16,+xseal5testmaccvmacsi32,+xseal5testmaccvmacui16,+xseal5testmaccvmacui32,+xseal5testmaccvmsusi16,+xseal5testmaccvmsusi32,+xseal5testmaccvmsuui16,+xseal5testmaccvmsuui32,+xseal5testmaccvmulhhns,+xseal5testmaccvmulhhnu,+xseal5testmaccvmulhhrns,+xseal5testmaccvmulhhrnu,+xseal5testmaccvmulns,+xseal5testmaccvmulnu,+xseal5testmaccvmulrns,+xseal5testmaccvmulrnu,-a,-c,-d,-e,-experimental-zacas,-experimental-zcmop,-experimental-zfbfmin,-experimental-zicfilp,-experimental-zicfiss,-experimental-zimop,-experimental-ztso,-experimental-zvfbfmin,-experimental-zvfbfwma,-f,-h,-smaia,-smepmp,-ssaia,-svinval,-svnapot,-svpbmt,-v,-xcvalu,-xcvbi,-xcvbitmanip,-xcvelw,-xcvmac,-xcvmem,-xcvsimd,-xsfvcp,-xsfvfnrclipxfqf,-xsfvfwmaccqqq,-xsfvqmaccdod,-xsfvqmaccqoq,-xtheadba,-xtheadbb,-xtheadbs,-xtheadcmo,-xtheadcondmov,-xtheadfmemidx,-xtheadmac,-xtheadmemidx,-xtheadmempair,-xtheadsync,-xtheadvdot,-xventanacondops,-za128rs,-za64rs,-zawrs,-zba,-zbb,-zbc,-zbkb,-zbkc,-zbkx,-zbs,-zca,-zcb,-zcd,-zce,-zcf,-zcmp,-zcmt,-zdinx,-zfa,-zfh,-zfhmin,-zfinx,-zhinx,-zhinxmin,-zic64b,-zicbom,-zicbop,-zicboz,-ziccamoa,-ziccif,-zicclsm,-ziccrse,-zicntr,-zicond,-zicsr,-zifencei,-zihintntl,-zihintpause,-zihpm,-zk,-zkn,-zknd,-zkne,-zknh,-zkr,-zks,-zksed,-zksh,-zkt,-zmmul,-zvbb,-zvbc,-zve32f,-zve32x,-zve64d,-zve64f,-zve64x,-zvfh,-zvfhmin,-zvkb,-zvkg,-zvkn,-zvknc,-zvkned,-zvkng,-zvknha,-zvknhb,-zvks,-zvksc,-zvksed,-zvksg,-zvksh,-zvkt,-zvl1024b,-zvl128b,-zvl16384b,-zvl2048b,-zvl256b,-zvl32768b,-zvl32b,-zvl4096b,-zvl512b,-zvl64b,-zvl65536b,-zvl8192b" }

!llvm.module.flags = !{!0, !1, !2}
!llvm.ident = !{!3}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 1, !"target-abi", !"ilp32"}
!2 = !{i32 8, !"SmallDataLimit", i32 8}
!3 = !{!"clang version 18.1.0rc (https://github.com/llvm/llvm-project.git 1acc4e456481e76822c76c850bad3994d4e04b59)"}
Building CG for module: cecil_test.c
  Adding 'test_macs32_v2i16' to entry set of the graph.
    Added callable function: test_macs32_v2i16
  Adding functions referenced by global initializers to the entry set.
  Adding functions called by 'test_macs32_v2i16' to the graph.
Running an SCC pass across the RefSCC: [(test_macs32_v2i16)]
; *** IR Dump Before InlinerPass on (test_macs32_v2i16) ***
; Function Attrs: nounwind
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv1, %conv4
  %add = add nsw i32 %mul, %acc
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv7, %conv11
  %add13 = add nsw i32 %add, %mul12
  ret i32 %add13
}
; *** IR Dump After InlinerPass on (test_macs32_v2i16) ***
; Function Attrs: nounwind
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv1, %conv4
  %add = add nsw i32 %mul, %acc
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv7, %conv11
  %add13 = add nsw i32 %add, %mul12
  ret i32 %add13
}
; *** IR Dump Before PostOrderFunctionAttrsPass on (test_macs32_v2i16) ***
; Function Attrs: nounwind
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv1, %conv4
  %add = add nsw i32 %mul, %acc
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv7, %conv11
  %add13 = add nsw i32 %add, %mul12
  ret i32 %add13
}
; *** IR Dump After PostOrderFunctionAttrsPass on (test_macs32_v2i16) ***
; Function Attrs: nounwind
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv1, %conv4
  %add = add nsw i32 %mul, %acc
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv7, %conv11
  %add13 = add nsw i32 %add, %mul12
  ret i32 %add13
}
; *** IR Dump Before ArgumentPromotionPass on (test_macs32_v2i16) ***
; Function Attrs: nounwind
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv1, %conv4
  %add = add nsw i32 %mul, %acc
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv7, %conv11
  %add13 = add nsw i32 %add, %mul12
  ret i32 %add13
}
; *** IR Dump After ArgumentPromotionPass on (test_macs32_v2i16) ***
; Function Attrs: nounwind
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv1, %conv4
  %add = add nsw i32 %mul, %acc
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv7, %conv11
  %add13 = add nsw i32 %add, %mul12
  ret i32 %add13
}
; *** IR Dump Before OpenMPOptCGSCCPass on (test_macs32_v2i16) ***
; Function Attrs: nounwind
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv1, %conv4
  %add = add nsw i32 %mul, %acc
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv7, %conv11
  %add13 = add nsw i32 %add, %mul12
  ret i32 %add13
}
; *** IR Dump After OpenMPOptCGSCCPass on (test_macs32_v2i16) ***
; Function Attrs: nounwind
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv1, %conv4
  %add = add nsw i32 %mul, %acc
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv7, %conv11
  %add13 = add nsw i32 %add, %mul12
  ret i32 %add13
}
Running function passes across an SCC: (test_macs32_v2i16)
; *** IR Dump Before SROAPass on test_macs32_v2i16 ***
; Function Attrs: nounwind
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv1, %conv4
  %add = add nsw i32 %mul, %acc
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv7, %conv11
  %add13 = add nsw i32 %add, %mul12
  ret i32 %add13
}
SROA function: test_macs32_v2i16
; *** IR Dump After SROAPass on test_macs32_v2i16 ***
; Function Attrs: nounwind
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv1, %conv4
  %add = add nsw i32 %mul, %acc
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv7, %conv11
  %add13 = add nsw i32 %add, %mul12
  ret i32 %add13
}
; *** IR Dump Before EarlyCSEPass on test_macs32_v2i16 ***
; Function Attrs: nounwind
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv1, %conv4
  %add = add nsw i32 %mul, %acc
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv7, %conv11
  %add13 = add nsw i32 %add, %mul12
  ret i32 %add13
}
; *** IR Dump After EarlyCSEPass on test_macs32_v2i16 ***
; Function Attrs: nounwind
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv1, %conv4
  %add = add nsw i32 %mul, %acc
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv7, %conv11
  %add13 = add nsw i32 %add, %mul12
  ret i32 %add13
}
; *** IR Dump Before SpeculativeExecutionPass on test_macs32_v2i16 ***
; Function Attrs: nounwind
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv1, %conv4
  %add = add nsw i32 %mul, %acc
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv7, %conv11
  %add13 = add nsw i32 %add, %mul12
  ret i32 %add13
}
Not running SpeculativeExecution because TTI->hasBranchDivergence() is false.
; *** IR Dump After SpeculativeExecutionPass on test_macs32_v2i16 ***
; Function Attrs: nounwind
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv1, %conv4
  %add = add nsw i32 %mul, %acc
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv7, %conv11
  %add13 = add nsw i32 %add, %mul12
  ret i32 %add13
}
; *** IR Dump Before JumpThreadingPass on test_macs32_v2i16 ***
; Function Attrs: nounwind
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv1, %conv4
  %add = add nsw i32 %mul, %acc
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv7, %conv11
  %add13 = add nsw i32 %add, %mul12
  ret i32 %add13
}
Jump threading on function 'test_macs32_v2i16'
; *** IR Dump After JumpThreadingPass on test_macs32_v2i16 ***
; Function Attrs: nounwind
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv1, %conv4
  %add = add nsw i32 %mul, %acc
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv7, %conv11
  %add13 = add nsw i32 %add, %mul12
  ret i32 %add13
}
; *** IR Dump Before CorrelatedValuePropagationPass on test_macs32_v2i16 ***
; Function Attrs: nounwind
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv1, %conv4
  %add = add nsw i32 %mul, %acc
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv7, %conv11
  %add13 = add nsw i32 %add, %mul12
  ret i32 %add13
}
LVI Getting block end value i32 %x at 'entry'
PUSH: i32 %x in entry
POP i32 %x in entry = overdefined
  Result = overdefined
LVI Getting block end value i32 16 at 'entry'
  Result = constantrange<16, 17>
LVI Getting block end value   %sext = shl i32 %x, 16 at 'entry'
PUSH:   %sext = shl i32 %x, 16 in entry
POP   %sext = shl i32 %x, 16 in entry = constantrange<0, -65535>
  Result = constantrange<0, -65535>
LVI Getting block end value i32 %y at 'entry'
PUSH: i32 %y in entry
POP i32 %y in entry = overdefined
  Result = overdefined
LVI Getting block end value i32 16 at 'entry'
  Result = constantrange<16, 17>
LVI Getting block end value   %sext18 = shl i32 %y, 16 at 'entry'
PUSH:   %sext18 = shl i32 %y, 16 in entry
POP   %sext18 = shl i32 %y, 16 in entry = constantrange<0, -65535>
  Result = constantrange<0, -65535>
LVI Getting block end value   %conv1 = ashr exact i32 %sext, 16 at 'entry'
PUSH:   %conv1 = ashr exact i32 %sext, 16 in entry
POP   %conv1 = ashr exact i32 %sext, 16 in entry = constantrange<-32768, 32768>
  Result = constantrange<-32768, 32768>
LVI Getting block end value   %conv4 = ashr exact i32 %sext18, 16 at 'entry'
PUSH:   %conv4 = ashr exact i32 %sext18, 16 in entry
POP   %conv4 = ashr exact i32 %sext18, 16 in entry = constantrange<-32768, 32768>
  Result = constantrange<-32768, 32768>
LVI Getting block end value   %mul = mul nsw i32 %conv1, %conv4 at 'entry'
PUSH:   %mul = mul nsw i32 %conv1, %conv4 in entry
POP   %mul = mul nsw i32 %conv1, %conv4 in entry = constantrange<-1073709056, 1073741825>
  Result = constantrange<-1073709056, 1073741825>
LVI Getting block end value i32 %acc at 'entry'
PUSH: i32 %acc in entry
POP i32 %acc in entry = overdefined
  Result = overdefined
LVI Getting block end value i32 %x at 'entry'
  Result = overdefined
LVI Getting block end value i32 %y at 'entry'
  Result = overdefined
LVI Getting block end value   %conv7 = ashr i32 %x, 16 at 'entry'
PUSH:   %conv7 = ashr i32 %x, 16 in entry
POP   %conv7 = ashr i32 %x, 16 in entry = constantrange<-32768, 32768>
  Result = constantrange<-32768, 32768>
LVI Getting block end value   %conv11 = ashr i32 %y, 16 at 'entry'
PUSH:   %conv11 = ashr i32 %y, 16 in entry
POP   %conv11 = ashr i32 %y, 16 in entry = constantrange<-32768, 32768>
  Result = constantrange<-32768, 32768>
LVI Getting block end value   %add = add nsw i32 %mul, %acc at 'entry'
PUSH:   %add = add nsw i32 %mul, %acc in entry
POP   %add = add nsw i32 %mul, %acc in entry = overdefined
  Result = overdefined
LVI Getting block end value   %mul12 = mul nsw i32 %conv7, %conv11 at 'entry'
PUSH:   %mul12 = mul nsw i32 %conv7, %conv11 in entry
POP   %mul12 = mul nsw i32 %conv7, %conv11 in entry = constantrange<-1073709056, 1073741825>
  Result = constantrange<-1073709056, 1073741825>
LVI Getting block end value   %add13 = add nsw i32 %add, %mul12 at 'entry'
PUSH:   %add13 = add nsw i32 %add, %mul12 in entry
POP   %add13 = add nsw i32 %add, %mul12 in entry = overdefined
  Result = overdefined
; *** IR Dump After CorrelatedValuePropagationPass on test_macs32_v2i16 ***
; Function Attrs: nounwind
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv1, %conv4
  %add = add nsw i32 %mul, %acc
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv7, %conv11
  %add13 = add nsw i32 %add, %mul12
  ret i32 %add13
}
; *** IR Dump Before SimplifyCFGPass on test_macs32_v2i16 ***
; Function Attrs: nounwind
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv1, %conv4
  %add = add nsw i32 %mul, %acc
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv7, %conv11
  %add13 = add nsw i32 %add, %mul12
  ret i32 %add13
}
; *** IR Dump After SimplifyCFGPass on test_macs32_v2i16 ***
; Function Attrs: nounwind
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv1, %conv4
  %add = add nsw i32 %mul, %acc
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv7, %conv11
  %add13 = add nsw i32 %add, %mul12
  ret i32 %add13
}
; *** IR Dump Before InstCombinePass on test_macs32_v2i16 ***
; Function Attrs: nounwind
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv1, %conv4
  %add = add nsw i32 %mul, %acc
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv7, %conv11
  %add13 = add nsw i32 %add, %mul12
  ret i32 %add13
}


INSTCOMBINE ITERATION #1 on test_macs32_v2i16
ADD:   ret i32 %add13
ADD:   %add13 = add nsw i32 %add, %mul12
ADD:   %mul12 = mul nsw i32 %conv7, %conv11
ADD:   %conv11 = ashr i32 %y, 16
ADD:   %conv7 = ashr i32 %x, 16
ADD:   %add = add nsw i32 %mul, %acc
ADD:   %mul = mul nsw i32 %conv1, %conv4
ADD:   %conv4 = ashr exact i32 %sext18, 16
ADD:   %sext18 = shl i32 %y, 16
ADD:   %conv1 = ashr exact i32 %sext, 16
ADD:   %sext = shl i32 %x, 16
IC: Visiting:   %sext = shl i32 %x, 16
IC: Visiting:   %conv1 = ashr exact i32 %sext, 16
IC: Visiting:   %sext18 = shl i32 %y, 16
IC: Visiting:   %conv4 = ashr exact i32 %sext18, 16
IC: Visiting:   %mul = mul nsw i32 %conv1, %conv4
IC: Visiting:   %add = add nsw i32 %mul, %acc
IC: Visiting:   %conv7 = ashr i32 %x, 16
IC: Visiting:   %conv11 = ashr i32 %y, 16
IC: Visiting:   %mul12 = mul nsw i32 %conv7, %conv11
IC: Visiting:   %add13 = add nsw i32 %add, %mul12
IC: Visiting:   ret i32 %add13
; *** IR Dump After InstCombinePass on test_macs32_v2i16 ***
; Function Attrs: nounwind
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv1, %conv4
  %add = add nsw i32 %mul, %acc
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv7, %conv11
  %add13 = add nsw i32 %add, %mul12
  ret i32 %add13
}
; *** IR Dump Before AggressiveInstCombinePass on test_macs32_v2i16 ***
; Function Attrs: nounwind
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv1, %conv4
  %add = add nsw i32 %mul, %acc
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv7, %conv11
  %add13 = add nsw i32 %add, %mul12
  ret i32 %add13
}
; *** IR Dump After AggressiveInstCombinePass on test_macs32_v2i16 ***
; Function Attrs: nounwind
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv1, %conv4
  %add = add nsw i32 %mul, %acc
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv7, %conv11
  %add13 = add nsw i32 %add, %mul12
  ret i32 %add13
}
; *** IR Dump Before LibCallsShrinkWrapPass on test_macs32_v2i16 ***
; Function Attrs: nounwind
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv1, %conv4
  %add = add nsw i32 %mul, %acc
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv7, %conv11
  %add13 = add nsw i32 %add, %mul12
  ret i32 %add13
}
; *** IR Dump After LibCallsShrinkWrapPass on test_macs32_v2i16 ***
; Function Attrs: nounwind
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv1, %conv4
  %add = add nsw i32 %mul, %acc
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv7, %conv11
  %add13 = add nsw i32 %add, %mul12
  ret i32 %add13
}
; *** IR Dump Before TailCallElimPass on test_macs32_v2i16 ***
; Function Attrs: nounwind
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv1, %conv4
  %add = add nsw i32 %mul, %acc
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv7, %conv11
  %add13 = add nsw i32 %add, %mul12
  ret i32 %add13
}
; *** IR Dump After TailCallElimPass on test_macs32_v2i16 ***
; Function Attrs: nounwind
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv1, %conv4
  %add = add nsw i32 %mul, %acc
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv7, %conv11
  %add13 = add nsw i32 %add, %mul12
  ret i32 %add13
}
; *** IR Dump Before SimplifyCFGPass on test_macs32_v2i16 ***
; Function Attrs: nounwind
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv1, %conv4
  %add = add nsw i32 %mul, %acc
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv7, %conv11
  %add13 = add nsw i32 %add, %mul12
  ret i32 %add13
}
; *** IR Dump After SimplifyCFGPass on test_macs32_v2i16 ***
; Function Attrs: nounwind
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv1, %conv4
  %add = add nsw i32 %mul, %acc
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv7, %conv11
  %add13 = add nsw i32 %add, %mul12
  ret i32 %add13
}
; *** IR Dump Before ReassociatePass on test_macs32_v2i16 ***
; Function Attrs: nounwind
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv1, %conv4
  %add = add nsw i32 %mul, %acc
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv7, %conv11
  %add13 = add nsw i32 %add, %mul12
  ret i32 %add13
}
Calculated Rank[acc] = 3
Calculated Rank[x] = 4
Calculated Rank[y] = 5
Combine negations for:   %sext = shl i32 %x, 16
Combine negations for:   %conv1 = ashr exact i32 %sext, 16
Combine negations for:   %sext18 = shl i32 %y, 16
Combine negations for:   %conv4 = ashr exact i32 %sext18, 16
Calculated Rank[sext18] = 6
Calculated Rank[conv4] = 7
Calculated Rank[sext] = 5
Calculated Rank[conv1] = 6
Combine negations for:   %mul = mul nsw i32 %conv1, %conv4
LINEARIZE:   %mul = mul nsw i32 %conv1, %conv4
OPERAND:   %conv1 = ashr exact i32 %sext, 16 (1)
ADD LEAF:   %conv1 = ashr exact i32 %sext, 16 (1)
OPERAND:   %conv4 = ashr exact i32 %sext18, 16 (1)
ADD LEAF:   %conv4 = ashr exact i32 %sext18, 16 (1)
RAIn:	mul i32	[ %conv1, #6] [ %conv4, #7] 
RAOut:	mul i32	[ %conv4, #7] [ %conv1, #6] 
RAOut after CSE reorder:	mul i32	[ %conv4, #7] [ %conv1, #6] 
RA:   %mul = mul nsw i32 %conv1, %conv4
TO:   %mul = mul nsw i32 %conv4, %conv1
Calculated Rank[mul] = 8
Combine negations for:   %add = add nsw i32 %acc, %mul
Combine negations for:   %conv7 = ashr i32 %x, 16
Combine negations for:   %conv11 = ashr i32 %y, 16
Calculated Rank[conv11] = 6
Calculated Rank[conv7] = 5
Combine negations for:   %mul12 = mul nsw i32 %conv7, %conv11
LINEARIZE:   %mul12 = mul nsw i32 %conv7, %conv11
OPERAND:   %conv7 = ashr i32 %x, 16 (1)
ADD LEAF:   %conv7 = ashr i32 %x, 16 (1)
OPERAND:   %conv11 = ashr i32 %y, 16 (1)
ADD LEAF:   %conv11 = ashr i32 %y, 16 (1)
RAIn:	mul i32	[ %conv7, #5] [ %conv11, #6] 
RAOut:	mul i32	[ %conv11, #6] [ %conv7, #5] 
RAOut after CSE reorder:	mul i32	[ %conv11, #6] [ %conv7, #5] 
RA:   %mul12 = mul nsw i32 %conv7, %conv11
TO:   %mul12 = mul nsw i32 %conv11, %conv7
Calculated Rank[mul12] = 7
Calculated Rank[add] = 9
Combine negations for:   %add13 = add nsw i32 %mul12, %add
LINEARIZE:   %add13 = add nsw i32 %mul12, %add
OPERAND:   %mul12 = mul nsw i32 %conv11, %conv7 (1)
ADD LEAF:   %mul12 = mul nsw i32 %conv11, %conv7 (1)
OPERAND:   %add = add nsw i32 %acc, %mul (1)
DIRECT ADD:   %add = add nsw i32 %acc, %mul (1)
OPERAND: i32 %acc (1)
ADD LEAF: i32 %acc (1)
OPERAND:   %mul = mul nsw i32 %conv4, %conv1 (1)
ADD LEAF:   %mul = mul nsw i32 %conv4, %conv1 (1)
RAIn:	add i32	[ %mul12, #7] [ %acc, #3] [ %mul, #8] 
RAOut:	add i32	[ %mul, #8] [ %mul12, #7] [ %acc, #3] 
RAOut after CSE reorder:	add i32	[ %mul, #8] [ %mul12, #7] [ %acc, #3] 
RA:   %add13 = add nsw i32 %mul12, %add
TO:   %add13 = add nsw i32 %mul12, %mul
RA:   %add13 = add nsw i32 %mul12, %mul
TO:   %add13 = add nsw i32 %add, %mul
RA:   %add = add nsw i32 %acc, %mul
TO:   %add = add nsw i32 %mul12, %acc
Combine negations for:   %add13 = add i32 %mul, %add
LINEARIZE:   %add13 = add i32 %mul, %add
OPERAND:   %mul = mul nsw i32 %conv4, %conv1 (1)
ADD LEAF:   %mul = mul nsw i32 %conv4, %conv1 (1)
OPERAND:   %add = add i32 %mul12, %acc (1)
DIRECT ADD:   %add = add i32 %mul12, %acc (1)
OPERAND:   %mul12 = mul nsw i32 %conv11, %conv7 (1)
ADD LEAF:   %mul12 = mul nsw i32 %conv11, %conv7 (1)
OPERAND: i32 %acc (1)
ADD LEAF: i32 %acc (1)
RAIn:	add i32	[ %mul, #8] [ %mul12, #7] [ %acc, #3] 
RAOut:	add i32	[ %mul, #8] [ %mul12, #7] [ %acc, #3] 
RAOut after CSE reorder:	add i32	[ %mul, #8] [ %mul12, #7] [ %acc, #3] 
RA:   %add13 = add i32 %mul, %add
TO:   %add13 = add i32 %add, %mul
; *** IR Dump After ReassociatePass on test_macs32_v2i16 ***
; Function Attrs: nounwind
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv4, %conv1
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv11, %conv7
  %add = add i32 %mul12, %acc
  %add13 = add i32 %add, %mul
  ret i32 %add13
}
; *** IR Dump Before ConstraintEliminationPass on test_macs32_v2i16 ***
; Function Attrs: nounwind
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv4, %conv1
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv11, %conv7
  %add = add i32 %mul12, %acc
  %add13 = add i32 %add, %mul
  ret i32 %add13
}
; *** IR Dump After ConstraintEliminationPass on test_macs32_v2i16 ***
; Function Attrs: nounwind
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv4, %conv1
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv11, %conv7
  %add = add i32 %mul12, %acc
  %add13 = add i32 %add, %mul
  ret i32 %add13
}
; *** IR Dump Before LoopSimplifyPass on test_macs32_v2i16 ***
; Function Attrs: nounwind
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv4, %conv1
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv11, %conv7
  %add = add i32 %mul12, %acc
  %add13 = add i32 %add, %mul
  ret i32 %add13
}
; *** IR Dump After LoopSimplifyPass on test_macs32_v2i16 ***
; Function Attrs: nounwind
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv4, %conv1
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv11, %conv7
  %add = add i32 %mul12, %acc
  %add13 = add i32 %add, %mul
  ret i32 %add13
}
; *** IR Dump Before LCSSAPass on test_macs32_v2i16 ***
; Function Attrs: nounwind
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv4, %conv1
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv11, %conv7
  %add = add i32 %mul12, %acc
  %add13 = add i32 %add, %mul
  ret i32 %add13
}
; *** IR Dump After LCSSAPass on test_macs32_v2i16 ***
; Function Attrs: nounwind
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv4, %conv1
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv11, %conv7
  %add = add i32 %mul12, %acc
  %add13 = add i32 %add, %mul
  ret i32 %add13
}
; *** IR Dump Before SimplifyCFGPass on test_macs32_v2i16 ***
; Function Attrs: nounwind
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv4, %conv1
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv11, %conv7
  %add = add i32 %mul12, %acc
  %add13 = add i32 %add, %mul
  ret i32 %add13
}
; *** IR Dump After SimplifyCFGPass on test_macs32_v2i16 ***
; Function Attrs: nounwind
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv4, %conv1
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv11, %conv7
  %add = add i32 %mul12, %acc
  %add13 = add i32 %add, %mul
  ret i32 %add13
}
; *** IR Dump Before InstCombinePass on test_macs32_v2i16 ***
; Function Attrs: nounwind
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv4, %conv1
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv11, %conv7
  %add = add i32 %mul12, %acc
  %add13 = add i32 %add, %mul
  ret i32 %add13
}


INSTCOMBINE ITERATION #1 on test_macs32_v2i16
ADD:   ret i32 %add13
ADD:   %add13 = add i32 %add, %mul
ADD:   %add = add i32 %mul12, %acc
ADD:   %mul12 = mul nsw i32 %conv11, %conv7
ADD:   %conv11 = ashr i32 %y, 16
ADD:   %conv7 = ashr i32 %x, 16
ADD:   %mul = mul nsw i32 %conv4, %conv1
ADD:   %conv4 = ashr exact i32 %sext18, 16
ADD:   %sext18 = shl i32 %y, 16
ADD:   %conv1 = ashr exact i32 %sext, 16
ADD:   %sext = shl i32 %x, 16
IC: Visiting:   %sext = shl i32 %x, 16
IC: Visiting:   %conv1 = ashr exact i32 %sext, 16
IC: Visiting:   %sext18 = shl i32 %y, 16
IC: Visiting:   %conv4 = ashr exact i32 %sext18, 16
IC: Visiting:   %mul = mul nsw i32 %conv4, %conv1
IC: Visiting:   %conv7 = ashr i32 %x, 16
IC: Visiting:   %conv11 = ashr i32 %y, 16
IC: Visiting:   %mul12 = mul nsw i32 %conv11, %conv7
IC: Visiting:   %add = add i32 %mul12, %acc
IC: Visiting:   %add13 = add i32 %add, %mul
IC: Visiting:   ret i32 %add13
; *** IR Dump After InstCombinePass on test_macs32_v2i16 ***
; Function Attrs: nounwind
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv4, %conv1
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv11, %conv7
  %add = add i32 %mul12, %acc
  %add13 = add i32 %add, %mul
  ret i32 %add13
}
; *** IR Dump Before LoopSimplifyPass on test_macs32_v2i16 ***
; Function Attrs: nounwind
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv4, %conv1
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv11, %conv7
  %add = add i32 %mul12, %acc
  %add13 = add i32 %add, %mul
  ret i32 %add13
}
; *** IR Dump After LoopSimplifyPass on test_macs32_v2i16 ***
; Function Attrs: nounwind
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv4, %conv1
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv11, %conv7
  %add = add i32 %mul12, %acc
  %add13 = add i32 %add, %mul
  ret i32 %add13
}
; *** IR Dump Before LCSSAPass on test_macs32_v2i16 ***
; Function Attrs: nounwind
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv4, %conv1
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv11, %conv7
  %add = add i32 %mul12, %acc
  %add13 = add i32 %add, %mul
  ret i32 %add13
}
; *** IR Dump After LCSSAPass on test_macs32_v2i16 ***
; Function Attrs: nounwind
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv4, %conv1
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv11, %conv7
  %add = add i32 %mul12, %acc
  %add13 = add i32 %add, %mul
  ret i32 %add13
}
; *** IR Dump Before SROAPass on test_macs32_v2i16 ***
; Function Attrs: nounwind
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv4, %conv1
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv11, %conv7
  %add = add i32 %mul12, %acc
  %add13 = add i32 %add, %mul
  ret i32 %add13
}
SROA function: test_macs32_v2i16
; *** IR Dump After SROAPass on test_macs32_v2i16 ***
; Function Attrs: nounwind
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv4, %conv1
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv11, %conv7
  %add = add i32 %mul12, %acc
  %add13 = add i32 %add, %mul
  ret i32 %add13
}
; *** IR Dump Before VectorCombinePass on test_macs32_v2i16 ***
; Function Attrs: nounwind
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv4, %conv1
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv11, %conv7
  %add = add i32 %mul12, %acc
  %add13 = add i32 %add, %mul
  ret i32 %add13
}
; *** IR Dump After VectorCombinePass on test_macs32_v2i16 ***
; Function Attrs: nounwind
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv4, %conv1
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv11, %conv7
  %add = add i32 %mul12, %acc
  %add13 = add i32 %add, %mul
  ret i32 %add13
}
; *** IR Dump Before MergedLoadStoreMotionPass on test_macs32_v2i16 ***
; Function Attrs: nounwind
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv4, %conv1
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv11, %conv7
  %add = add i32 %mul12, %acc
  %add13 = add i32 %add, %mul
  ret i32 %add13
}
Instruction Merger
; *** IR Dump After MergedLoadStoreMotionPass on test_macs32_v2i16 ***
; Function Attrs: nounwind
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv4, %conv1
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv11, %conv7
  %add = add i32 %mul12, %acc
  %add13 = add i32 %add, %mul
  ret i32 %add13
}
; *** IR Dump Before GVNPass on test_macs32_v2i16 ***
; Function Attrs: nounwind
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv4, %conv1
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv11, %conv7
  %add = add i32 %mul12, %acc
  %add13 = add i32 %add, %mul
  ret i32 %add13
}
GVN iteration: 0
; *** IR Dump After GVNPass on test_macs32_v2i16 ***
; Function Attrs: nounwind
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv4, %conv1
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv11, %conv7
  %add = add i32 %mul12, %acc
  %add13 = add i32 %add, %mul
  ret i32 %add13
}
; *** IR Dump Before SCCPPass on test_macs32_v2i16 ***
; Function Attrs: nounwind
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv4, %conv1
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv11, %conv7
  %add = add i32 %mul12, %acc
  %add13 = add i32 %add, %mul
  ret i32 %add13
}
SCCP on function 'test_macs32_v2i16'
Marking Block Executable: entry
markOverdefined: i32 %acc
markOverdefined: i32 %x
markOverdefined: i32 %y

Popped off OI-WL: i32 %y
Merged constantrange<-32768, 32768> into   %conv11 = ashr i32 %y, 16 : constantrange<-32768, 32768>
Merged constantrange<0, -65535> into   %sext18 = shl i32 %y, 16 : constantrange<0, -65535>

Popped off OI-WL: i32 %x
Merged constantrange<-32768, 32768> into   %conv7 = ashr i32 %x, 16 : constantrange<-32768, 32768>
Merged constantrange<0, -65535> into   %sext = shl i32 %x, 16 : constantrange<0, -65535>

Popped off OI-WL: i32 %acc

Popped off I-WL:   %sext = shl i32 %x, 16
Merged constantrange<-32768, 32768> into   %conv1 = ashr exact i32 %sext, 16 : constantrange<-32768, 32768>

Popped off I-WL:   %conv1 = ashr exact i32 %sext, 16

Popped off I-WL:   %conv7 = ashr i32 %x, 16
Merged constantrange<-1073709056, 1073741825> into   %mul12 = mul nsw i32 %conv11, %conv7 : constantrange<-1073709056, 1073741825>

Popped off I-WL:   %mul12 = mul nsw i32 %conv11, %conv7
Merged overdefined into   %add = add i32 %mul12, %acc : overdefined

Popped off I-WL:   %sext18 = shl i32 %y, 16
Merged constantrange<-32768, 32768> into   %conv4 = ashr exact i32 %sext18, 16 : constantrange<-32768, 32768>

Popped off I-WL:   %conv4 = ashr exact i32 %sext18, 16
Merged constantrange<-1073709056, 1073741825> into   %mul = mul nsw i32 %conv4, %conv1 : constantrange<-1073709056, 1073741825>

Popped off I-WL:   %mul = mul nsw i32 %conv4, %conv1
Merged overdefined into   %add13 = add i32 %add, %mul : overdefined

Popped off I-WL:   %conv11 = ashr i32 %y, 16

Popped off BBWL: 
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv4, %conv1
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv11, %conv7
  %add = add i32 %mul12, %acc
  %add13 = add i32 %add, %mul
  ret i32 %add13


Popped off OI-WL:   %add13 = add i32 %add, %mul

Popped off OI-WL:   %add = add i32 %mul12, %acc
RESOLVING UNDEFs
; *** IR Dump After SCCPPass on test_macs32_v2i16 ***
; Function Attrs: nounwind
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv4, %conv1
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv11, %conv7
  %add = add i32 %mul12, %acc
  %add13 = add i32 %add, %mul
  ret i32 %add13
}
; *** IR Dump Before BDCEPass on test_macs32_v2i16 ***
; Function Attrs: nounwind
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv4, %conv1
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv11, %conv7
  %add = add i32 %mul12, %acc
  %add13 = add i32 %add, %mul
  ret i32 %add13
}
DemandedBits: Root:   ret i32 %add13
DemandedBits: Visiting:   %add13 = add i32 %add, %mul Alive Out: 0xffffffff
DemandedBits: Visiting:   %mul = mul nsw i32 %conv4, %conv1 Alive Out: 0xffffffff
DemandedBits: Visiting:   %conv1 = ashr exact i32 %sext, 16 Alive Out: 0xffffffff
DemandedBits: Visiting:   %sext = shl i32 %x, 16 Alive Out: 0xffffffff
DemandedBits: Visiting:   %conv4 = ashr exact i32 %sext18, 16 Alive Out: 0xffffffff
DemandedBits: Visiting:   %sext18 = shl i32 %y, 16 Alive Out: 0xffffffff
DemandedBits: Visiting:   %add = add i32 %mul12, %acc Alive Out: 0xffffffff
DemandedBits: Visiting:   %mul12 = mul nsw i32 %conv11, %conv7 Alive Out: 0xffffffff
DemandedBits: Visiting:   %conv7 = ashr i32 %x, 16 Alive Out: 0xffffffff
DemandedBits: Visiting:   %conv11 = ashr i32 %y, 16 Alive Out: 0xffffffff
; *** IR Dump After BDCEPass on test_macs32_v2i16 ***
; Function Attrs: nounwind
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv4, %conv1
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv11, %conv7
  %add = add i32 %mul12, %acc
  %add13 = add i32 %add, %mul
  ret i32 %add13
}
; *** IR Dump Before InstCombinePass on test_macs32_v2i16 ***
; Function Attrs: nounwind
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv4, %conv1
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv11, %conv7
  %add = add i32 %mul12, %acc
  %add13 = add i32 %add, %mul
  ret i32 %add13
}


INSTCOMBINE ITERATION #1 on test_macs32_v2i16
ADD:   ret i32 %add13
ADD:   %add13 = add i32 %add, %mul
ADD:   %add = add i32 %mul12, %acc
ADD:   %mul12 = mul nsw i32 %conv11, %conv7
ADD:   %conv11 = ashr i32 %y, 16
ADD:   %conv7 = ashr i32 %x, 16
ADD:   %mul = mul nsw i32 %conv4, %conv1
ADD:   %conv4 = ashr exact i32 %sext18, 16
ADD:   %sext18 = shl i32 %y, 16
ADD:   %conv1 = ashr exact i32 %sext, 16
ADD:   %sext = shl i32 %x, 16
IC: Visiting:   %sext = shl i32 %x, 16
IC: Visiting:   %conv1 = ashr exact i32 %sext, 16
IC: Visiting:   %sext18 = shl i32 %y, 16
IC: Visiting:   %conv4 = ashr exact i32 %sext18, 16
IC: Visiting:   %mul = mul nsw i32 %conv4, %conv1
IC: Visiting:   %conv7 = ashr i32 %x, 16
IC: Visiting:   %conv11 = ashr i32 %y, 16
IC: Visiting:   %mul12 = mul nsw i32 %conv11, %conv7
IC: Visiting:   %add = add i32 %mul12, %acc
IC: Visiting:   %add13 = add i32 %add, %mul
IC: Visiting:   ret i32 %add13
; *** IR Dump After InstCombinePass on test_macs32_v2i16 ***
; Function Attrs: nounwind
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv4, %conv1
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv11, %conv7
  %add = add i32 %mul12, %acc
  %add13 = add i32 %add, %mul
  ret i32 %add13
}
; *** IR Dump Before JumpThreadingPass on test_macs32_v2i16 ***
; Function Attrs: nounwind
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv4, %conv1
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv11, %conv7
  %add = add i32 %mul12, %acc
  %add13 = add i32 %add, %mul
  ret i32 %add13
}
Jump threading on function 'test_macs32_v2i16'
; *** IR Dump After JumpThreadingPass on test_macs32_v2i16 ***
; Function Attrs: nounwind
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv4, %conv1
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv11, %conv7
  %add = add i32 %mul12, %acc
  %add13 = add i32 %add, %mul
  ret i32 %add13
}
; *** IR Dump Before CorrelatedValuePropagationPass on test_macs32_v2i16 ***
; Function Attrs: nounwind
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv4, %conv1
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv11, %conv7
  %add = add i32 %mul12, %acc
  %add13 = add i32 %add, %mul
  ret i32 %add13
}
LVI Getting block end value i32 %x at 'entry'
PUSH: i32 %x in entry
POP i32 %x in entry = overdefined
  Result = overdefined
LVI Getting block end value i32 16 at 'entry'
  Result = constantrange<16, 17>
LVI Getting block end value   %sext = shl i32 %x, 16 at 'entry'
PUSH:   %sext = shl i32 %x, 16 in entry
POP   %sext = shl i32 %x, 16 in entry = constantrange<0, -65535>
  Result = constantrange<0, -65535>
LVI Getting block end value i32 %y at 'entry'
PUSH: i32 %y in entry
POP i32 %y in entry = overdefined
  Result = overdefined
LVI Getting block end value i32 16 at 'entry'
  Result = constantrange<16, 17>
LVI Getting block end value   %sext18 = shl i32 %y, 16 at 'entry'
PUSH:   %sext18 = shl i32 %y, 16 in entry
POP   %sext18 = shl i32 %y, 16 in entry = constantrange<0, -65535>
  Result = constantrange<0, -65535>
LVI Getting block end value   %conv4 = ashr exact i32 %sext18, 16 at 'entry'
PUSH:   %conv4 = ashr exact i32 %sext18, 16 in entry
POP   %conv4 = ashr exact i32 %sext18, 16 in entry = constantrange<-32768, 32768>
  Result = constantrange<-32768, 32768>
LVI Getting block end value   %conv1 = ashr exact i32 %sext, 16 at 'entry'
PUSH:   %conv1 = ashr exact i32 %sext, 16 in entry
POP   %conv1 = ashr exact i32 %sext, 16 in entry = constantrange<-32768, 32768>
  Result = constantrange<-32768, 32768>
LVI Getting block end value i32 %x at 'entry'
  Result = overdefined
LVI Getting block end value i32 %y at 'entry'
  Result = overdefined
LVI Getting block end value   %conv11 = ashr i32 %y, 16 at 'entry'
PUSH:   %conv11 = ashr i32 %y, 16 in entry
POP   %conv11 = ashr i32 %y, 16 in entry = constantrange<-32768, 32768>
  Result = constantrange<-32768, 32768>
LVI Getting block end value   %conv7 = ashr i32 %x, 16 at 'entry'
PUSH:   %conv7 = ashr i32 %x, 16 in entry
POP   %conv7 = ashr i32 %x, 16 in entry = constantrange<-32768, 32768>
  Result = constantrange<-32768, 32768>
LVI Getting block end value   %mul12 = mul nsw i32 %conv11, %conv7 at 'entry'
PUSH:   %mul12 = mul nsw i32 %conv11, %conv7 in entry
POP   %mul12 = mul nsw i32 %conv11, %conv7 in entry = constantrange<-1073709056, 1073741825>
  Result = constantrange<-1073709056, 1073741825>
LVI Getting block end value i32 %acc at 'entry'
PUSH: i32 %acc in entry
POP i32 %acc in entry = overdefined
  Result = overdefined
LVI Getting block end value   %add = add i32 %mul12, %acc at 'entry'
PUSH:   %add = add i32 %mul12, %acc in entry
POP   %add = add i32 %mul12, %acc in entry = overdefined
  Result = overdefined
LVI Getting block end value   %mul = mul nsw i32 %conv4, %conv1 at 'entry'
PUSH:   %mul = mul nsw i32 %conv4, %conv1 in entry
POP   %mul = mul nsw i32 %conv4, %conv1 in entry = constantrange<-1073709056, 1073741825>
  Result = constantrange<-1073709056, 1073741825>
LVI Getting block end value   %add13 = add i32 %add, %mul at 'entry'
PUSH:   %add13 = add i32 %add, %mul in entry
POP   %add13 = add i32 %add, %mul in entry = overdefined
  Result = overdefined
; *** IR Dump After CorrelatedValuePropagationPass on test_macs32_v2i16 ***
; Function Attrs: nounwind
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv4, %conv1
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv11, %conv7
  %add = add i32 %mul12, %acc
  %add13 = add i32 %add, %mul
  ret i32 %add13
}
; *** IR Dump Before ADCEPass on test_macs32_v2i16 ***
; Function Attrs: nounwind
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv4, %conv1
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv11, %conv7
  %add = add i32 %mul12, %acc
  %add13 = add i32 %add, %mul
  ret i32 %add13
}
		Looking for trivial roots
Found a new trivial root: %entry
Last visited node: %entry
		Looking for non-trivial roots
Total: 1, Num: 2
Discovered CFG nodes:
0: nullptr
1: nullptr
2: %entry
Found roots: %entry 
mark live:   ret i32 %add13
mark block live: entry
post-dom root child is a return: entry
work live:   ret i32 %add13
mark live:   %add13 = add i32 %add, %mul
work live:   %add13 = add i32 %add, %mul
mark live:   %add = add i32 %mul12, %acc
mark live:   %mul = mul nsw i32 %conv4, %conv1
work live:   %mul = mul nsw i32 %conv4, %conv1
mark live:   %conv4 = ashr exact i32 %sext18, 16
mark live:   %conv1 = ashr exact i32 %sext, 16
work live:   %conv1 = ashr exact i32 %sext, 16
mark live:   %sext = shl i32 %x, 16
work live:   %sext = shl i32 %x, 16
work live:   %conv4 = ashr exact i32 %sext18, 16
mark live:   %sext18 = shl i32 %y, 16
work live:   %sext18 = shl i32 %y, 16
work live:   %add = add i32 %mul12, %acc
mark live:   %mul12 = mul nsw i32 %conv11, %conv7
work live:   %mul12 = mul nsw i32 %conv11, %conv7
mark live:   %conv11 = ashr i32 %y, 16
mark live:   %conv7 = ashr i32 %x, 16
work live:   %conv7 = ashr i32 %x, 16
work live:   %conv11 = ashr i32 %y, 16
final dead terminator blocks: 
; *** IR Dump After ADCEPass on test_macs32_v2i16 ***
; Function Attrs: nounwind
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv4, %conv1
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv11, %conv7
  %add = add i32 %mul12, %acc
  %add13 = add i32 %add, %mul
  ret i32 %add13
}
; *** IR Dump Before MemCpyOptPass on test_macs32_v2i16 ***
; Function Attrs: nounwind
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv4, %conv1
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv11, %conv7
  %add = add i32 %mul12, %acc
  %add13 = add i32 %add, %mul
  ret i32 %add13
}
; *** IR Dump After MemCpyOptPass on test_macs32_v2i16 ***
; Function Attrs: nounwind
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv4, %conv1
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv11, %conv7
  %add = add i32 %mul12, %acc
  %add13 = add i32 %add, %mul
  ret i32 %add13
}
; *** IR Dump Before DSEPass on test_macs32_v2i16 ***
; Function Attrs: nounwind
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv4, %conv1
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv11, %conv7
  %add = add i32 %mul12, %acc
  %add13 = add i32 %add, %mul
  ret i32 %add13
}
Trying to eliminate MemoryDefs that write the already existing value
Trying to eliminate MemoryDefs at the end of the function
; *** IR Dump After DSEPass on test_macs32_v2i16 ***
; Function Attrs: nounwind
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv4, %conv1
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv11, %conv7
  %add = add i32 %mul12, %acc
  %add13 = add i32 %add, %mul
  ret i32 %add13
}
; *** IR Dump Before MoveAutoInitPass on test_macs32_v2i16 ***
; Function Attrs: nounwind
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv4, %conv1
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv11, %conv7
  %add = add i32 %mul12, %acc
  %add13 = add i32 %add, %mul
  ret i32 %add13
}
; *** IR Dump After MoveAutoInitPass on test_macs32_v2i16 ***
; Function Attrs: nounwind
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv4, %conv1
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv11, %conv7
  %add = add i32 %mul12, %acc
  %add13 = add i32 %add, %mul
  ret i32 %add13
}
; *** IR Dump Before LoopSimplifyPass on test_macs32_v2i16 ***
; Function Attrs: nounwind
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv4, %conv1
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv11, %conv7
  %add = add i32 %mul12, %acc
  %add13 = add i32 %add, %mul
  ret i32 %add13
}
; *** IR Dump After LoopSimplifyPass on test_macs32_v2i16 ***
; Function Attrs: nounwind
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv4, %conv1
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv11, %conv7
  %add = add i32 %mul12, %acc
  %add13 = add i32 %add, %mul
  ret i32 %add13
}
; *** IR Dump Before LCSSAPass on test_macs32_v2i16 ***
; Function Attrs: nounwind
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv4, %conv1
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv11, %conv7
  %add = add i32 %mul12, %acc
  %add13 = add i32 %add, %mul
  ret i32 %add13
}
; *** IR Dump After LCSSAPass on test_macs32_v2i16 ***
; Function Attrs: nounwind
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv4, %conv1
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv11, %conv7
  %add = add i32 %mul12, %acc
  %add13 = add i32 %add, %mul
  ret i32 %add13
}
; *** IR Dump Before CoroElidePass on test_macs32_v2i16 ***
; Function Attrs: nounwind
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv4, %conv1
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv11, %conv7
  %add = add i32 %mul12, %acc
  %add13 = add i32 %add, %mul
  ret i32 %add13
}
; *** IR Dump After CoroElidePass on test_macs32_v2i16 ***
; Function Attrs: nounwind
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv4, %conv1
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv11, %conv7
  %add = add i32 %mul12, %acc
  %add13 = add i32 %add, %mul
  ret i32 %add13
}
; *** IR Dump Before SimplifyCFGPass on test_macs32_v2i16 ***
; Function Attrs: nounwind
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv4, %conv1
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv11, %conv7
  %add = add i32 %mul12, %acc
  %add13 = add i32 %add, %mul
  ret i32 %add13
}
; *** IR Dump After SimplifyCFGPass on test_macs32_v2i16 ***
; Function Attrs: nounwind
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv4, %conv1
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv11, %conv7
  %add = add i32 %mul12, %acc
  %add13 = add i32 %add, %mul
  ret i32 %add13
}
; *** IR Dump Before InstCombinePass on test_macs32_v2i16 ***
; Function Attrs: nounwind
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv4, %conv1
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv11, %conv7
  %add = add i32 %mul12, %acc
  %add13 = add i32 %add, %mul
  ret i32 %add13
}


INSTCOMBINE ITERATION #1 on test_macs32_v2i16
ADD:   ret i32 %add13
ADD:   %add13 = add i32 %add, %mul
ADD:   %add = add i32 %mul12, %acc
ADD:   %mul12 = mul nsw i32 %conv11, %conv7
ADD:   %conv11 = ashr i32 %y, 16
ADD:   %conv7 = ashr i32 %x, 16
ADD:   %mul = mul nsw i32 %conv4, %conv1
ADD:   %conv4 = ashr exact i32 %sext18, 16
ADD:   %sext18 = shl i32 %y, 16
ADD:   %conv1 = ashr exact i32 %sext, 16
ADD:   %sext = shl i32 %x, 16
IC: Visiting:   %sext = shl i32 %x, 16
IC: Visiting:   %conv1 = ashr exact i32 %sext, 16
IC: Visiting:   %sext18 = shl i32 %y, 16
IC: Visiting:   %conv4 = ashr exact i32 %sext18, 16
IC: Visiting:   %mul = mul nsw i32 %conv4, %conv1
IC: Visiting:   %conv7 = ashr i32 %x, 16
IC: Visiting:   %conv11 = ashr i32 %y, 16
IC: Visiting:   %mul12 = mul nsw i32 %conv11, %conv7
IC: Visiting:   %add = add i32 %mul12, %acc
IC: Visiting:   %add13 = add i32 %add, %mul
IC: Visiting:   ret i32 %add13
; *** IR Dump After InstCombinePass on test_macs32_v2i16 ***
; Function Attrs: nounwind
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv4, %conv1
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv11, %conv7
  %add = add i32 %mul12, %acc
  %add13 = add i32 %add, %mul
  ret i32 %add13
}
; *** IR Dump Before PostOrderFunctionAttrsPass on (test_macs32_v2i16) ***
; Function Attrs: nounwind
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv4, %conv1
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv11, %conv7
  %add = add i32 %mul12, %acc
  %add13 = add i32 %add, %mul
  ret i32 %add13
}
Adding nosync attr to fn test_macs32_v2i16
; *** IR Dump After PostOrderFunctionAttrsPass on (test_macs32_v2i16) ***
; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none)
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv4, %conv1
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv11, %conv7
  %add = add i32 %mul12, %acc
  %add13 = add i32 %add, %mul
  ret i32 %add13
}
Running function passes across an SCC: (test_macs32_v2i16)
; *** IR Dump Before RequireAnalysisPass<llvm::ShouldNotRunFunctionPassesAnalysis, llvm::Function> on test_macs32_v2i16 ***
; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none)
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv4, %conv1
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv11, %conv7
  %add = add i32 %mul12, %acc
  %add13 = add i32 %add, %mul
  ret i32 %add13
}
; *** IR Dump After RequireAnalysisPass<llvm::ShouldNotRunFunctionPassesAnalysis, llvm::Function> on test_macs32_v2i16 ***
; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none)
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv4, %conv1
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv11, %conv7
  %add = add i32 %mul12, %acc
  %add13 = add i32 %add, %mul
  ret i32 %add13
}
; *** IR Dump Before CoroSplitPass on (test_macs32_v2i16) ***
; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none)
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv4, %conv1
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv11, %conv7
  %add = add i32 %mul12, %acc
  %add13 = add i32 %add, %mul
  ret i32 %add13
}
; *** IR Dump After CoroSplitPass on (test_macs32_v2i16) ***
; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none)
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv4, %conv1
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv11, %conv7
  %add = add i32 %mul12, %acc
  %add13 = add i32 %add, %mul
  ret i32 %add13
}
; *** IR Dump Before InvalidateAnalysisPass<llvm::ShouldNotRunFunctionPassesAnalysis> on test_macs32_v2i16 ***
; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none)
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv4, %conv1
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv11, %conv7
  %add = add i32 %mul12, %acc
  %add13 = add i32 %add, %mul
  ret i32 %add13
}
; *** IR Dump After InvalidateAnalysisPass<llvm::ShouldNotRunFunctionPassesAnalysis> on test_macs32_v2i16 ***
; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none)
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv4, %conv1
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv11, %conv7
  %add = add i32 %mul12, %acc
  %add13 = add i32 %add, %mul
  ret i32 %add13
}
; *** IR Dump Before DeadArgumentEliminationPass on [module] ***
; ModuleID = 'cecil_test.c'
source_filename = "cecil_test.c"
target datalayout = "e-m:e-p:32:32-i64:64-n32-S128"
target triple = "riscv32-unknown-unknown"

; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none)
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv4, %conv1
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv11, %conv7
  %add = add i32 %mul12, %acc
  %add13 = add i32 %add, %mul
  ret i32 %add13
}

attributes #0 = { mustprogress nofree norecurse nosync nounwind willreturn memory(none) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="generic-rv32" "target-features"="+32bit,+m,+relax,+xseal5testalucvabs16,+xseal5testalucvabs32,+xseal5testalucvabs8,+xseal5testalucvaddnrsi16,+xseal5testalucvaddnrsi32,+xseal5testalucvaddnrui16,+xseal5testalucvaddnrui32,+xseal5testalucvaddns,+xseal5testalucvaddnu,+xseal5testalucvaddrnrsi16,+xseal5testalucvaddrnrsi32,+xseal5testalucvaddrnrui16,+xseal5testalucvaddrnrui32,+xseal5testalucvaddrns,+xseal5testalucvaddrnu,+xseal5testalucvextbs,+xseal5testalucvextbz,+xseal5testalucvexths,+xseal5testalucvexthz,+xseal5testalucvmaxi1216,+xseal5testalucvmaxi1232,+xseal5testalucvmaxi516,+xseal5testalucvmaxi532,+xseal5testalucvmaxs16,+xseal5testalucvmaxs32,+xseal5testalucvmaxs8,+xseal5testalucvmaxu16,+xseal5testalucvmaxu32,+xseal5testalucvmaxu8,+xseal5testalucvmini1216,+xseal5testalucvmini1232,+xseal5testalucvmini516,+xseal5testalucvmini532,+xseal5testalucvmins16,+xseal5testalucvmins32,+xseal5testalucvmins8,+xseal5testalucvminu16,+xseal5testalucvminu32,+xseal5testalucvminu8,+xseal5testalucvsletsi16,+xseal5testalucvsletsi32,+xseal5testalucvsletui16,+xseal5testalucvsletui32,+xseal5testalucvsubnrsi16,+xseal5testalucvsubnrsi32,+xseal5testalucvsubnrui16,+xseal5testalucvsubnrui32,+xseal5testalucvsubns,+xseal5testalucvsubnu,+xseal5testalucvsubrnrsi16,+xseal5testalucvsubrnrsi32,+xseal5testalucvsubrnrui16,+xseal5testalucvsubrnrui32,+xseal5testalucvsubrns,+xseal5testalucvsubrnu,+xseal5testmaccvmachhns,+xseal5testmaccvmachhnu,+xseal5testmaccvmachhrns,+xseal5testmaccvmachhrnu,+xseal5testmaccvmacns,+xseal5testmaccvmacnu,+xseal5testmaccvmacrns,+xseal5testmaccvmacrnu,+xseal5testmaccvmacsi16,+xseal5testmaccvmacsi32,+xseal5testmaccvmacui16,+xseal5testmaccvmacui32,+xseal5testmaccvmsusi16,+xseal5testmaccvmsusi32,+xseal5testmaccvmsuui16,+xseal5testmaccvmsuui32,+xseal5testmaccvmulhhns,+xseal5testmaccvmulhhnu,+xseal5testmaccvmulhhrns,+xseal5testmaccvmulhhrnu,+xseal5testmaccvmulns,+xseal5testmaccvmulnu,+xseal5testmaccvmulrns,+xseal5testmaccvmulrnu,-a,-c,-d,-e,-experimental-zacas,-experimental-zcmop,-experimental-zfbfmin,-experimental-zicfilp,-experimental-zicfiss,-experimental-zimop,-experimental-ztso,-experimental-zvfbfmin,-experimental-zvfbfwma,-f,-h,-smaia,-smepmp,-ssaia,-svinval,-svnapot,-svpbmt,-v,-xcvalu,-xcvbi,-xcvbitmanip,-xcvelw,-xcvmac,-xcvmem,-xcvsimd,-xsfvcp,-xsfvfnrclipxfqf,-xsfvfwmaccqqq,-xsfvqmaccdod,-xsfvqmaccqoq,-xtheadba,-xtheadbb,-xtheadbs,-xtheadcmo,-xtheadcondmov,-xtheadfmemidx,-xtheadmac,-xtheadmemidx,-xtheadmempair,-xtheadsync,-xtheadvdot,-xventanacondops,-za128rs,-za64rs,-zawrs,-zba,-zbb,-zbc,-zbkb,-zbkc,-zbkx,-zbs,-zca,-zcb,-zcd,-zce,-zcf,-zcmp,-zcmt,-zdinx,-zfa,-zfh,-zfhmin,-zfinx,-zhinx,-zhinxmin,-zic64b,-zicbom,-zicbop,-zicboz,-ziccamoa,-ziccif,-zicclsm,-ziccrse,-zicntr,-zicond,-zicsr,-zifencei,-zihintntl,-zihintpause,-zihpm,-zk,-zkn,-zknd,-zkne,-zknh,-zkr,-zks,-zksed,-zksh,-zkt,-zmmul,-zvbb,-zvbc,-zve32f,-zve32x,-zve64d,-zve64f,-zve64x,-zvfh,-zvfhmin,-zvkb,-zvkg,-zvkn,-zvknc,-zvkned,-zvkng,-zvknha,-zvknhb,-zvks,-zvksc,-zvksed,-zvksg,-zvksh,-zvkt,-zvl1024b,-zvl128b,-zvl16384b,-zvl2048b,-zvl256b,-zvl32768b,-zvl32b,-zvl4096b,-zvl512b,-zvl64b,-zvl65536b,-zvl8192b" }

!llvm.module.flags = !{!0, !1, !2}
!llvm.ident = !{!3}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 1, !"target-abi", !"ilp32"}
!2 = !{i32 8, !"SmallDataLimit", i32 8}
!3 = !{!"clang version 18.1.0rc (https://github.com/llvm/llvm-project.git 1acc4e456481e76822c76c850bad3994d4e04b59)"}
DeadArgumentEliminationPass - Deleting dead varargs
DeadArgumentEliminationPass - Determining liveness
DeadArgumentEliminationPass - Intrinsically live fn: test_macs32_v2i16
; *** IR Dump After DeadArgumentEliminationPass on [module] ***
; ModuleID = 'cecil_test.c'
source_filename = "cecil_test.c"
target datalayout = "e-m:e-p:32:32-i64:64-n32-S128"
target triple = "riscv32-unknown-unknown"

; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none)
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv4, %conv1
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv11, %conv7
  %add = add i32 %mul12, %acc
  %add13 = add i32 %add, %mul
  ret i32 %add13
}

attributes #0 = { mustprogress nofree norecurse nosync nounwind willreturn memory(none) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="generic-rv32" "target-features"="+32bit,+m,+relax,+xseal5testalucvabs16,+xseal5testalucvabs32,+xseal5testalucvabs8,+xseal5testalucvaddnrsi16,+xseal5testalucvaddnrsi32,+xseal5testalucvaddnrui16,+xseal5testalucvaddnrui32,+xseal5testalucvaddns,+xseal5testalucvaddnu,+xseal5testalucvaddrnrsi16,+xseal5testalucvaddrnrsi32,+xseal5testalucvaddrnrui16,+xseal5testalucvaddrnrui32,+xseal5testalucvaddrns,+xseal5testalucvaddrnu,+xseal5testalucvextbs,+xseal5testalucvextbz,+xseal5testalucvexths,+xseal5testalucvexthz,+xseal5testalucvmaxi1216,+xseal5testalucvmaxi1232,+xseal5testalucvmaxi516,+xseal5testalucvmaxi532,+xseal5testalucvmaxs16,+xseal5testalucvmaxs32,+xseal5testalucvmaxs8,+xseal5testalucvmaxu16,+xseal5testalucvmaxu32,+xseal5testalucvmaxu8,+xseal5testalucvmini1216,+xseal5testalucvmini1232,+xseal5testalucvmini516,+xseal5testalucvmini532,+xseal5testalucvmins16,+xseal5testalucvmins32,+xseal5testalucvmins8,+xseal5testalucvminu16,+xseal5testalucvminu32,+xseal5testalucvminu8,+xseal5testalucvsletsi16,+xseal5testalucvsletsi32,+xseal5testalucvsletui16,+xseal5testalucvsletui32,+xseal5testalucvsubnrsi16,+xseal5testalucvsubnrsi32,+xseal5testalucvsubnrui16,+xseal5testalucvsubnrui32,+xseal5testalucvsubns,+xseal5testalucvsubnu,+xseal5testalucvsubrnrsi16,+xseal5testalucvsubrnrsi32,+xseal5testalucvsubrnrui16,+xseal5testalucvsubrnrui32,+xseal5testalucvsubrns,+xseal5testalucvsubrnu,+xseal5testmaccvmachhns,+xseal5testmaccvmachhnu,+xseal5testmaccvmachhrns,+xseal5testmaccvmachhrnu,+xseal5testmaccvmacns,+xseal5testmaccvmacnu,+xseal5testmaccvmacrns,+xseal5testmaccvmacrnu,+xseal5testmaccvmacsi16,+xseal5testmaccvmacsi32,+xseal5testmaccvmacui16,+xseal5testmaccvmacui32,+xseal5testmaccvmsusi16,+xseal5testmaccvmsusi32,+xseal5testmaccvmsuui16,+xseal5testmaccvmsuui32,+xseal5testmaccvmulhhns,+xseal5testmaccvmulhhnu,+xseal5testmaccvmulhhrns,+xseal5testmaccvmulhhrnu,+xseal5testmaccvmulns,+xseal5testmaccvmulnu,+xseal5testmaccvmulrns,+xseal5testmaccvmulrnu,-a,-c,-d,-e,-experimental-zacas,-experimental-zcmop,-experimental-zfbfmin,-experimental-zicfilp,-experimental-zicfiss,-experimental-zimop,-experimental-ztso,-experimental-zvfbfmin,-experimental-zvfbfwma,-f,-h,-smaia,-smepmp,-ssaia,-svinval,-svnapot,-svpbmt,-v,-xcvalu,-xcvbi,-xcvbitmanip,-xcvelw,-xcvmac,-xcvmem,-xcvsimd,-xsfvcp,-xsfvfnrclipxfqf,-xsfvfwmaccqqq,-xsfvqmaccdod,-xsfvqmaccqoq,-xtheadba,-xtheadbb,-xtheadbs,-xtheadcmo,-xtheadcondmov,-xtheadfmemidx,-xtheadmac,-xtheadmemidx,-xtheadmempair,-xtheadsync,-xtheadvdot,-xventanacondops,-za128rs,-za64rs,-zawrs,-zba,-zbb,-zbc,-zbkb,-zbkc,-zbkx,-zbs,-zca,-zcb,-zcd,-zce,-zcf,-zcmp,-zcmt,-zdinx,-zfa,-zfh,-zfhmin,-zfinx,-zhinx,-zhinxmin,-zic64b,-zicbom,-zicbop,-zicboz,-ziccamoa,-ziccif,-zicclsm,-ziccrse,-zicntr,-zicond,-zicsr,-zifencei,-zihintntl,-zihintpause,-zihpm,-zk,-zkn,-zknd,-zkne,-zknh,-zkr,-zks,-zksed,-zksh,-zkt,-zmmul,-zvbb,-zvbc,-zve32f,-zve32x,-zve64d,-zve64f,-zve64x,-zvfh,-zvfhmin,-zvkb,-zvkg,-zvkn,-zvknc,-zvkned,-zvkng,-zvknha,-zvknhb,-zvks,-zvksc,-zvksed,-zvksg,-zvksh,-zvkt,-zvl1024b,-zvl128b,-zvl16384b,-zvl2048b,-zvl256b,-zvl32768b,-zvl32b,-zvl4096b,-zvl512b,-zvl64b,-zvl65536b,-zvl8192b" }

!llvm.module.flags = !{!0, !1, !2}
!llvm.ident = !{!3}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 1, !"target-abi", !"ilp32"}
!2 = !{i32 8, !"SmallDataLimit", i32 8}
!3 = !{!"clang version 18.1.0rc (https://github.com/llvm/llvm-project.git 1acc4e456481e76822c76c850bad3994d4e04b59)"}
; *** IR Dump Before CoroCleanupPass on [module] ***
; ModuleID = 'cecil_test.c'
source_filename = "cecil_test.c"
target datalayout = "e-m:e-p:32:32-i64:64-n32-S128"
target triple = "riscv32-unknown-unknown"

; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none)
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv4, %conv1
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv11, %conv7
  %add = add i32 %mul12, %acc
  %add13 = add i32 %add, %mul
  ret i32 %add13
}

attributes #0 = { mustprogress nofree norecurse nosync nounwind willreturn memory(none) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="generic-rv32" "target-features"="+32bit,+m,+relax,+xseal5testalucvabs16,+xseal5testalucvabs32,+xseal5testalucvabs8,+xseal5testalucvaddnrsi16,+xseal5testalucvaddnrsi32,+xseal5testalucvaddnrui16,+xseal5testalucvaddnrui32,+xseal5testalucvaddns,+xseal5testalucvaddnu,+xseal5testalucvaddrnrsi16,+xseal5testalucvaddrnrsi32,+xseal5testalucvaddrnrui16,+xseal5testalucvaddrnrui32,+xseal5testalucvaddrns,+xseal5testalucvaddrnu,+xseal5testalucvextbs,+xseal5testalucvextbz,+xseal5testalucvexths,+xseal5testalucvexthz,+xseal5testalucvmaxi1216,+xseal5testalucvmaxi1232,+xseal5testalucvmaxi516,+xseal5testalucvmaxi532,+xseal5testalucvmaxs16,+xseal5testalucvmaxs32,+xseal5testalucvmaxs8,+xseal5testalucvmaxu16,+xseal5testalucvmaxu32,+xseal5testalucvmaxu8,+xseal5testalucvmini1216,+xseal5testalucvmini1232,+xseal5testalucvmini516,+xseal5testalucvmini532,+xseal5testalucvmins16,+xseal5testalucvmins32,+xseal5testalucvmins8,+xseal5testalucvminu16,+xseal5testalucvminu32,+xseal5testalucvminu8,+xseal5testalucvsletsi16,+xseal5testalucvsletsi32,+xseal5testalucvsletui16,+xseal5testalucvsletui32,+xseal5testalucvsubnrsi16,+xseal5testalucvsubnrsi32,+xseal5testalucvsubnrui16,+xseal5testalucvsubnrui32,+xseal5testalucvsubns,+xseal5testalucvsubnu,+xseal5testalucvsubrnrsi16,+xseal5testalucvsubrnrsi32,+xseal5testalucvsubrnrui16,+xseal5testalucvsubrnrui32,+xseal5testalucvsubrns,+xseal5testalucvsubrnu,+xseal5testmaccvmachhns,+xseal5testmaccvmachhnu,+xseal5testmaccvmachhrns,+xseal5testmaccvmachhrnu,+xseal5testmaccvmacns,+xseal5testmaccvmacnu,+xseal5testmaccvmacrns,+xseal5testmaccvmacrnu,+xseal5testmaccvmacsi16,+xseal5testmaccvmacsi32,+xseal5testmaccvmacui16,+xseal5testmaccvmacui32,+xseal5testmaccvmsusi16,+xseal5testmaccvmsusi32,+xseal5testmaccvmsuui16,+xseal5testmaccvmsuui32,+xseal5testmaccvmulhhns,+xseal5testmaccvmulhhnu,+xseal5testmaccvmulhhrns,+xseal5testmaccvmulhhrnu,+xseal5testmaccvmulns,+xseal5testmaccvmulnu,+xseal5testmaccvmulrns,+xseal5testmaccvmulrnu,-a,-c,-d,-e,-experimental-zacas,-experimental-zcmop,-experimental-zfbfmin,-experimental-zicfilp,-experimental-zicfiss,-experimental-zimop,-experimental-ztso,-experimental-zvfbfmin,-experimental-zvfbfwma,-f,-h,-smaia,-smepmp,-ssaia,-svinval,-svnapot,-svpbmt,-v,-xcvalu,-xcvbi,-xcvbitmanip,-xcvelw,-xcvmac,-xcvmem,-xcvsimd,-xsfvcp,-xsfvfnrclipxfqf,-xsfvfwmaccqqq,-xsfvqmaccdod,-xsfvqmaccqoq,-xtheadba,-xtheadbb,-xtheadbs,-xtheadcmo,-xtheadcondmov,-xtheadfmemidx,-xtheadmac,-xtheadmemidx,-xtheadmempair,-xtheadsync,-xtheadvdot,-xventanacondops,-za128rs,-za64rs,-zawrs,-zba,-zbb,-zbc,-zbkb,-zbkc,-zbkx,-zbs,-zca,-zcb,-zcd,-zce,-zcf,-zcmp,-zcmt,-zdinx,-zfa,-zfh,-zfhmin,-zfinx,-zhinx,-zhinxmin,-zic64b,-zicbom,-zicbop,-zicboz,-ziccamoa,-ziccif,-zicclsm,-ziccrse,-zicntr,-zicond,-zicsr,-zifencei,-zihintntl,-zihintpause,-zihpm,-zk,-zkn,-zknd,-zkne,-zknh,-zkr,-zks,-zksed,-zksh,-zkt,-zmmul,-zvbb,-zvbc,-zve32f,-zve32x,-zve64d,-zve64f,-zve64x,-zvfh,-zvfhmin,-zvkb,-zvkg,-zvkn,-zvknc,-zvkned,-zvkng,-zvknha,-zvknhb,-zvks,-zvksc,-zvksed,-zvksg,-zvksh,-zvkt,-zvl1024b,-zvl128b,-zvl16384b,-zvl2048b,-zvl256b,-zvl32768b,-zvl32b,-zvl4096b,-zvl512b,-zvl64b,-zvl65536b,-zvl8192b" }

!llvm.module.flags = !{!0, !1, !2}
!llvm.ident = !{!3}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 1, !"target-abi", !"ilp32"}
!2 = !{i32 8, !"SmallDataLimit", i32 8}
!3 = !{!"clang version 18.1.0rc (https://github.com/llvm/llvm-project.git 1acc4e456481e76822c76c850bad3994d4e04b59)"}
; *** IR Dump After CoroCleanupPass on [module] ***
; ModuleID = 'cecil_test.c'
source_filename = "cecil_test.c"
target datalayout = "e-m:e-p:32:32-i64:64-n32-S128"
target triple = "riscv32-unknown-unknown"

; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none)
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv4, %conv1
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv11, %conv7
  %add = add i32 %mul12, %acc
  %add13 = add i32 %add, %mul
  ret i32 %add13
}

attributes #0 = { mustprogress nofree norecurse nosync nounwind willreturn memory(none) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="generic-rv32" "target-features"="+32bit,+m,+relax,+xseal5testalucvabs16,+xseal5testalucvabs32,+xseal5testalucvabs8,+xseal5testalucvaddnrsi16,+xseal5testalucvaddnrsi32,+xseal5testalucvaddnrui16,+xseal5testalucvaddnrui32,+xseal5testalucvaddns,+xseal5testalucvaddnu,+xseal5testalucvaddrnrsi16,+xseal5testalucvaddrnrsi32,+xseal5testalucvaddrnrui16,+xseal5testalucvaddrnrui32,+xseal5testalucvaddrns,+xseal5testalucvaddrnu,+xseal5testalucvextbs,+xseal5testalucvextbz,+xseal5testalucvexths,+xseal5testalucvexthz,+xseal5testalucvmaxi1216,+xseal5testalucvmaxi1232,+xseal5testalucvmaxi516,+xseal5testalucvmaxi532,+xseal5testalucvmaxs16,+xseal5testalucvmaxs32,+xseal5testalucvmaxs8,+xseal5testalucvmaxu16,+xseal5testalucvmaxu32,+xseal5testalucvmaxu8,+xseal5testalucvmini1216,+xseal5testalucvmini1232,+xseal5testalucvmini516,+xseal5testalucvmini532,+xseal5testalucvmins16,+xseal5testalucvmins32,+xseal5testalucvmins8,+xseal5testalucvminu16,+xseal5testalucvminu32,+xseal5testalucvminu8,+xseal5testalucvsletsi16,+xseal5testalucvsletsi32,+xseal5testalucvsletui16,+xseal5testalucvsletui32,+xseal5testalucvsubnrsi16,+xseal5testalucvsubnrsi32,+xseal5testalucvsubnrui16,+xseal5testalucvsubnrui32,+xseal5testalucvsubns,+xseal5testalucvsubnu,+xseal5testalucvsubrnrsi16,+xseal5testalucvsubrnrsi32,+xseal5testalucvsubrnrui16,+xseal5testalucvsubrnrui32,+xseal5testalucvsubrns,+xseal5testalucvsubrnu,+xseal5testmaccvmachhns,+xseal5testmaccvmachhnu,+xseal5testmaccvmachhrns,+xseal5testmaccvmachhrnu,+xseal5testmaccvmacns,+xseal5testmaccvmacnu,+xseal5testmaccvmacrns,+xseal5testmaccvmacrnu,+xseal5testmaccvmacsi16,+xseal5testmaccvmacsi32,+xseal5testmaccvmacui16,+xseal5testmaccvmacui32,+xseal5testmaccvmsusi16,+xseal5testmaccvmsusi32,+xseal5testmaccvmsuui16,+xseal5testmaccvmsuui32,+xseal5testmaccvmulhhns,+xseal5testmaccvmulhhnu,+xseal5testmaccvmulhhrns,+xseal5testmaccvmulhhrnu,+xseal5testmaccvmulns,+xseal5testmaccvmulnu,+xseal5testmaccvmulrns,+xseal5testmaccvmulrnu,-a,-c,-d,-e,-experimental-zacas,-experimental-zcmop,-experimental-zfbfmin,-experimental-zicfilp,-experimental-zicfiss,-experimental-zimop,-experimental-ztso,-experimental-zvfbfmin,-experimental-zvfbfwma,-f,-h,-smaia,-smepmp,-ssaia,-svinval,-svnapot,-svpbmt,-v,-xcvalu,-xcvbi,-xcvbitmanip,-xcvelw,-xcvmac,-xcvmem,-xcvsimd,-xsfvcp,-xsfvfnrclipxfqf,-xsfvfwmaccqqq,-xsfvqmaccdod,-xsfvqmaccqoq,-xtheadba,-xtheadbb,-xtheadbs,-xtheadcmo,-xtheadcondmov,-xtheadfmemidx,-xtheadmac,-xtheadmemidx,-xtheadmempair,-xtheadsync,-xtheadvdot,-xventanacondops,-za128rs,-za64rs,-zawrs,-zba,-zbb,-zbc,-zbkb,-zbkc,-zbkx,-zbs,-zca,-zcb,-zcd,-zce,-zcf,-zcmp,-zcmt,-zdinx,-zfa,-zfh,-zfhmin,-zfinx,-zhinx,-zhinxmin,-zic64b,-zicbom,-zicbop,-zicboz,-ziccamoa,-ziccif,-zicclsm,-ziccrse,-zicntr,-zicond,-zicsr,-zifencei,-zihintntl,-zihintpause,-zihpm,-zk,-zkn,-zknd,-zkne,-zknh,-zkr,-zks,-zksed,-zksh,-zkt,-zmmul,-zvbb,-zvbc,-zve32f,-zve32x,-zve64d,-zve64f,-zve64x,-zvfh,-zvfhmin,-zvkb,-zvkg,-zvkn,-zvknc,-zvkned,-zvkng,-zvknha,-zvknhb,-zvks,-zvksc,-zvksed,-zvksg,-zvksh,-zvkt,-zvl1024b,-zvl128b,-zvl16384b,-zvl2048b,-zvl256b,-zvl32768b,-zvl32b,-zvl4096b,-zvl512b,-zvl64b,-zvl65536b,-zvl8192b" }

!llvm.module.flags = !{!0, !1, !2}
!llvm.ident = !{!3}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 1, !"target-abi", !"ilp32"}
!2 = !{i32 8, !"SmallDataLimit", i32 8}
!3 = !{!"clang version 18.1.0rc (https://github.com/llvm/llvm-project.git 1acc4e456481e76822c76c850bad3994d4e04b59)"}
; *** IR Dump Before GlobalOptPass on [module] ***
; ModuleID = 'cecil_test.c'
source_filename = "cecil_test.c"
target datalayout = "e-m:e-p:32:32-i64:64-n32-S128"
target triple = "riscv32-unknown-unknown"

; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none)
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv4, %conv1
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv11, %conv7
  %add = add i32 %mul12, %acc
  %add13 = add i32 %add, %mul
  ret i32 %add13
}

attributes #0 = { mustprogress nofree norecurse nosync nounwind willreturn memory(none) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="generic-rv32" "target-features"="+32bit,+m,+relax,+xseal5testalucvabs16,+xseal5testalucvabs32,+xseal5testalucvabs8,+xseal5testalucvaddnrsi16,+xseal5testalucvaddnrsi32,+xseal5testalucvaddnrui16,+xseal5testalucvaddnrui32,+xseal5testalucvaddns,+xseal5testalucvaddnu,+xseal5testalucvaddrnrsi16,+xseal5testalucvaddrnrsi32,+xseal5testalucvaddrnrui16,+xseal5testalucvaddrnrui32,+xseal5testalucvaddrns,+xseal5testalucvaddrnu,+xseal5testalucvextbs,+xseal5testalucvextbz,+xseal5testalucvexths,+xseal5testalucvexthz,+xseal5testalucvmaxi1216,+xseal5testalucvmaxi1232,+xseal5testalucvmaxi516,+xseal5testalucvmaxi532,+xseal5testalucvmaxs16,+xseal5testalucvmaxs32,+xseal5testalucvmaxs8,+xseal5testalucvmaxu16,+xseal5testalucvmaxu32,+xseal5testalucvmaxu8,+xseal5testalucvmini1216,+xseal5testalucvmini1232,+xseal5testalucvmini516,+xseal5testalucvmini532,+xseal5testalucvmins16,+xseal5testalucvmins32,+xseal5testalucvmins8,+xseal5testalucvminu16,+xseal5testalucvminu32,+xseal5testalucvminu8,+xseal5testalucvsletsi16,+xseal5testalucvsletsi32,+xseal5testalucvsletui16,+xseal5testalucvsletui32,+xseal5testalucvsubnrsi16,+xseal5testalucvsubnrsi32,+xseal5testalucvsubnrui16,+xseal5testalucvsubnrui32,+xseal5testalucvsubns,+xseal5testalucvsubnu,+xseal5testalucvsubrnrsi16,+xseal5testalucvsubrnrsi32,+xseal5testalucvsubrnrui16,+xseal5testalucvsubrnrui32,+xseal5testalucvsubrns,+xseal5testalucvsubrnu,+xseal5testmaccvmachhns,+xseal5testmaccvmachhnu,+xseal5testmaccvmachhrns,+xseal5testmaccvmachhrnu,+xseal5testmaccvmacns,+xseal5testmaccvmacnu,+xseal5testmaccvmacrns,+xseal5testmaccvmacrnu,+xseal5testmaccvmacsi16,+xseal5testmaccvmacsi32,+xseal5testmaccvmacui16,+xseal5testmaccvmacui32,+xseal5testmaccvmsusi16,+xseal5testmaccvmsusi32,+xseal5testmaccvmsuui16,+xseal5testmaccvmsuui32,+xseal5testmaccvmulhhns,+xseal5testmaccvmulhhnu,+xseal5testmaccvmulhhrns,+xseal5testmaccvmulhhrnu,+xseal5testmaccvmulns,+xseal5testmaccvmulnu,+xseal5testmaccvmulrns,+xseal5testmaccvmulrnu,-a,-c,-d,-e,-experimental-zacas,-experimental-zcmop,-experimental-zfbfmin,-experimental-zicfilp,-experimental-zicfiss,-experimental-zimop,-experimental-ztso,-experimental-zvfbfmin,-experimental-zvfbfwma,-f,-h,-smaia,-smepmp,-ssaia,-svinval,-svnapot,-svpbmt,-v,-xcvalu,-xcvbi,-xcvbitmanip,-xcvelw,-xcvmac,-xcvmem,-xcvsimd,-xsfvcp,-xsfvfnrclipxfqf,-xsfvfwmaccqqq,-xsfvqmaccdod,-xsfvqmaccqoq,-xtheadba,-xtheadbb,-xtheadbs,-xtheadcmo,-xtheadcondmov,-xtheadfmemidx,-xtheadmac,-xtheadmemidx,-xtheadmempair,-xtheadsync,-xtheadvdot,-xventanacondops,-za128rs,-za64rs,-zawrs,-zba,-zbb,-zbc,-zbkb,-zbkc,-zbkx,-zbs,-zca,-zcb,-zcd,-zce,-zcf,-zcmp,-zcmt,-zdinx,-zfa,-zfh,-zfhmin,-zfinx,-zhinx,-zhinxmin,-zic64b,-zicbom,-zicbop,-zicboz,-ziccamoa,-ziccif,-zicclsm,-ziccrse,-zicntr,-zicond,-zicsr,-zifencei,-zihintntl,-zihintpause,-zihpm,-zk,-zkn,-zknd,-zkne,-zknh,-zkr,-zks,-zksed,-zksh,-zkt,-zmmul,-zvbb,-zvbc,-zve32f,-zve32x,-zve64d,-zve64f,-zve64x,-zvfh,-zvfhmin,-zvkb,-zvkg,-zvkn,-zvknc,-zvkned,-zvkng,-zvknha,-zvknhb,-zvks,-zvksc,-zvksed,-zvksg,-zvksh,-zvkt,-zvl1024b,-zvl128b,-zvl16384b,-zvl2048b,-zvl256b,-zvl32768b,-zvl32b,-zvl4096b,-zvl512b,-zvl64b,-zvl65536b,-zvl8192b" }

!llvm.module.flags = !{!0, !1, !2}
!llvm.ident = !{!3}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 1, !"target-abi", !"ilp32"}
!2 = !{i32 8, !"SmallDataLimit", i32 8}
!3 = !{!"clang version 18.1.0rc (https://github.com/llvm/llvm-project.git 1acc4e456481e76822c76c850bad3994d4e04b59)"}
; *** IR Dump After GlobalOptPass on [module] ***
; ModuleID = 'cecil_test.c'
source_filename = "cecil_test.c"
target datalayout = "e-m:e-p:32:32-i64:64-n32-S128"
target triple = "riscv32-unknown-unknown"

; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none)
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv4, %conv1
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv11, %conv7
  %add = add i32 %mul12, %acc
  %add13 = add i32 %add, %mul
  ret i32 %add13
}

attributes #0 = { mustprogress nofree norecurse nosync nounwind willreturn memory(none) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="generic-rv32" "target-features"="+32bit,+m,+relax,+xseal5testalucvabs16,+xseal5testalucvabs32,+xseal5testalucvabs8,+xseal5testalucvaddnrsi16,+xseal5testalucvaddnrsi32,+xseal5testalucvaddnrui16,+xseal5testalucvaddnrui32,+xseal5testalucvaddns,+xseal5testalucvaddnu,+xseal5testalucvaddrnrsi16,+xseal5testalucvaddrnrsi32,+xseal5testalucvaddrnrui16,+xseal5testalucvaddrnrui32,+xseal5testalucvaddrns,+xseal5testalucvaddrnu,+xseal5testalucvextbs,+xseal5testalucvextbz,+xseal5testalucvexths,+xseal5testalucvexthz,+xseal5testalucvmaxi1216,+xseal5testalucvmaxi1232,+xseal5testalucvmaxi516,+xseal5testalucvmaxi532,+xseal5testalucvmaxs16,+xseal5testalucvmaxs32,+xseal5testalucvmaxs8,+xseal5testalucvmaxu16,+xseal5testalucvmaxu32,+xseal5testalucvmaxu8,+xseal5testalucvmini1216,+xseal5testalucvmini1232,+xseal5testalucvmini516,+xseal5testalucvmini532,+xseal5testalucvmins16,+xseal5testalucvmins32,+xseal5testalucvmins8,+xseal5testalucvminu16,+xseal5testalucvminu32,+xseal5testalucvminu8,+xseal5testalucvsletsi16,+xseal5testalucvsletsi32,+xseal5testalucvsletui16,+xseal5testalucvsletui32,+xseal5testalucvsubnrsi16,+xseal5testalucvsubnrsi32,+xseal5testalucvsubnrui16,+xseal5testalucvsubnrui32,+xseal5testalucvsubns,+xseal5testalucvsubnu,+xseal5testalucvsubrnrsi16,+xseal5testalucvsubrnrsi32,+xseal5testalucvsubrnrui16,+xseal5testalucvsubrnrui32,+xseal5testalucvsubrns,+xseal5testalucvsubrnu,+xseal5testmaccvmachhns,+xseal5testmaccvmachhnu,+xseal5testmaccvmachhrns,+xseal5testmaccvmachhrnu,+xseal5testmaccvmacns,+xseal5testmaccvmacnu,+xseal5testmaccvmacrns,+xseal5testmaccvmacrnu,+xseal5testmaccvmacsi16,+xseal5testmaccvmacsi32,+xseal5testmaccvmacui16,+xseal5testmaccvmacui32,+xseal5testmaccvmsusi16,+xseal5testmaccvmsusi32,+xseal5testmaccvmsuui16,+xseal5testmaccvmsuui32,+xseal5testmaccvmulhhns,+xseal5testmaccvmulhhnu,+xseal5testmaccvmulhhrns,+xseal5testmaccvmulhhrnu,+xseal5testmaccvmulns,+xseal5testmaccvmulnu,+xseal5testmaccvmulrns,+xseal5testmaccvmulrnu,-a,-c,-d,-e,-experimental-zacas,-experimental-zcmop,-experimental-zfbfmin,-experimental-zicfilp,-experimental-zicfiss,-experimental-zimop,-experimental-ztso,-experimental-zvfbfmin,-experimental-zvfbfwma,-f,-h,-smaia,-smepmp,-ssaia,-svinval,-svnapot,-svpbmt,-v,-xcvalu,-xcvbi,-xcvbitmanip,-xcvelw,-xcvmac,-xcvmem,-xcvsimd,-xsfvcp,-xsfvfnrclipxfqf,-xsfvfwmaccqqq,-xsfvqmaccdod,-xsfvqmaccqoq,-xtheadba,-xtheadbb,-xtheadbs,-xtheadcmo,-xtheadcondmov,-xtheadfmemidx,-xtheadmac,-xtheadmemidx,-xtheadmempair,-xtheadsync,-xtheadvdot,-xventanacondops,-za128rs,-za64rs,-zawrs,-zba,-zbb,-zbc,-zbkb,-zbkc,-zbkx,-zbs,-zca,-zcb,-zcd,-zce,-zcf,-zcmp,-zcmt,-zdinx,-zfa,-zfh,-zfhmin,-zfinx,-zhinx,-zhinxmin,-zic64b,-zicbom,-zicbop,-zicboz,-ziccamoa,-ziccif,-zicclsm,-ziccrse,-zicntr,-zicond,-zicsr,-zifencei,-zihintntl,-zihintpause,-zihpm,-zk,-zkn,-zknd,-zkne,-zknh,-zkr,-zks,-zksed,-zksh,-zkt,-zmmul,-zvbb,-zvbc,-zve32f,-zve32x,-zve64d,-zve64f,-zve64x,-zvfh,-zvfhmin,-zvkb,-zvkg,-zvkn,-zvknc,-zvkned,-zvkng,-zvknha,-zvknhb,-zvks,-zvksc,-zvksed,-zvksg,-zvksh,-zvkt,-zvl1024b,-zvl128b,-zvl16384b,-zvl2048b,-zvl256b,-zvl32768b,-zvl32b,-zvl4096b,-zvl512b,-zvl64b,-zvl65536b,-zvl8192b" }

!llvm.module.flags = !{!0, !1, !2}
!llvm.ident = !{!3}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 1, !"target-abi", !"ilp32"}
!2 = !{i32 8, !"SmallDataLimit", i32 8}
!3 = !{!"clang version 18.1.0rc (https://github.com/llvm/llvm-project.git 1acc4e456481e76822c76c850bad3994d4e04b59)"}
; *** IR Dump Before GlobalDCEPass on [module] ***
; ModuleID = 'cecil_test.c'
source_filename = "cecil_test.c"
target datalayout = "e-m:e-p:32:32-i64:64-n32-S128"
target triple = "riscv32-unknown-unknown"

; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none)
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv4, %conv1
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv11, %conv7
  %add = add i32 %mul12, %acc
  %add13 = add i32 %add, %mul
  ret i32 %add13
}

attributes #0 = { mustprogress nofree norecurse nosync nounwind willreturn memory(none) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="generic-rv32" "target-features"="+32bit,+m,+relax,+xseal5testalucvabs16,+xseal5testalucvabs32,+xseal5testalucvabs8,+xseal5testalucvaddnrsi16,+xseal5testalucvaddnrsi32,+xseal5testalucvaddnrui16,+xseal5testalucvaddnrui32,+xseal5testalucvaddns,+xseal5testalucvaddnu,+xseal5testalucvaddrnrsi16,+xseal5testalucvaddrnrsi32,+xseal5testalucvaddrnrui16,+xseal5testalucvaddrnrui32,+xseal5testalucvaddrns,+xseal5testalucvaddrnu,+xseal5testalucvextbs,+xseal5testalucvextbz,+xseal5testalucvexths,+xseal5testalucvexthz,+xseal5testalucvmaxi1216,+xseal5testalucvmaxi1232,+xseal5testalucvmaxi516,+xseal5testalucvmaxi532,+xseal5testalucvmaxs16,+xseal5testalucvmaxs32,+xseal5testalucvmaxs8,+xseal5testalucvmaxu16,+xseal5testalucvmaxu32,+xseal5testalucvmaxu8,+xseal5testalucvmini1216,+xseal5testalucvmini1232,+xseal5testalucvmini516,+xseal5testalucvmini532,+xseal5testalucvmins16,+xseal5testalucvmins32,+xseal5testalucvmins8,+xseal5testalucvminu16,+xseal5testalucvminu32,+xseal5testalucvminu8,+xseal5testalucvsletsi16,+xseal5testalucvsletsi32,+xseal5testalucvsletui16,+xseal5testalucvsletui32,+xseal5testalucvsubnrsi16,+xseal5testalucvsubnrsi32,+xseal5testalucvsubnrui16,+xseal5testalucvsubnrui32,+xseal5testalucvsubns,+xseal5testalucvsubnu,+xseal5testalucvsubrnrsi16,+xseal5testalucvsubrnrsi32,+xseal5testalucvsubrnrui16,+xseal5testalucvsubrnrui32,+xseal5testalucvsubrns,+xseal5testalucvsubrnu,+xseal5testmaccvmachhns,+xseal5testmaccvmachhnu,+xseal5testmaccvmachhrns,+xseal5testmaccvmachhrnu,+xseal5testmaccvmacns,+xseal5testmaccvmacnu,+xseal5testmaccvmacrns,+xseal5testmaccvmacrnu,+xseal5testmaccvmacsi16,+xseal5testmaccvmacsi32,+xseal5testmaccvmacui16,+xseal5testmaccvmacui32,+xseal5testmaccvmsusi16,+xseal5testmaccvmsusi32,+xseal5testmaccvmsuui16,+xseal5testmaccvmsuui32,+xseal5testmaccvmulhhns,+xseal5testmaccvmulhhnu,+xseal5testmaccvmulhhrns,+xseal5testmaccvmulhhrnu,+xseal5testmaccvmulns,+xseal5testmaccvmulnu,+xseal5testmaccvmulrns,+xseal5testmaccvmulrnu,-a,-c,-d,-e,-experimental-zacas,-experimental-zcmop,-experimental-zfbfmin,-experimental-zicfilp,-experimental-zicfiss,-experimental-zimop,-experimental-ztso,-experimental-zvfbfmin,-experimental-zvfbfwma,-f,-h,-smaia,-smepmp,-ssaia,-svinval,-svnapot,-svpbmt,-v,-xcvalu,-xcvbi,-xcvbitmanip,-xcvelw,-xcvmac,-xcvmem,-xcvsimd,-xsfvcp,-xsfvfnrclipxfqf,-xsfvfwmaccqqq,-xsfvqmaccdod,-xsfvqmaccqoq,-xtheadba,-xtheadbb,-xtheadbs,-xtheadcmo,-xtheadcondmov,-xtheadfmemidx,-xtheadmac,-xtheadmemidx,-xtheadmempair,-xtheadsync,-xtheadvdot,-xventanacondops,-za128rs,-za64rs,-zawrs,-zba,-zbb,-zbc,-zbkb,-zbkc,-zbkx,-zbs,-zca,-zcb,-zcd,-zce,-zcf,-zcmp,-zcmt,-zdinx,-zfa,-zfh,-zfhmin,-zfinx,-zhinx,-zhinxmin,-zic64b,-zicbom,-zicbop,-zicboz,-ziccamoa,-ziccif,-zicclsm,-ziccrse,-zicntr,-zicond,-zicsr,-zifencei,-zihintntl,-zihintpause,-zihpm,-zk,-zkn,-zknd,-zkne,-zknh,-zkr,-zks,-zksed,-zksh,-zkt,-zmmul,-zvbb,-zvbc,-zve32f,-zve32x,-zve64d,-zve64f,-zve64x,-zvfh,-zvfhmin,-zvkb,-zvkg,-zvkn,-zvknc,-zvkned,-zvkng,-zvknha,-zvknhb,-zvks,-zvksc,-zvksed,-zvksg,-zvksh,-zvkt,-zvl1024b,-zvl128b,-zvl16384b,-zvl2048b,-zvl256b,-zvl32768b,-zvl32b,-zvl4096b,-zvl512b,-zvl64b,-zvl65536b,-zvl8192b" }

!llvm.module.flags = !{!0, !1, !2}
!llvm.ident = !{!3}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 1, !"target-abi", !"ilp32"}
!2 = !{i32 8, !"SmallDataLimit", i32 8}
!3 = !{!"clang version 18.1.0rc (https://github.com/llvm/llvm-project.git 1acc4e456481e76822c76c850bad3994d4e04b59)"}
; *** IR Dump After GlobalDCEPass on [module] ***
; ModuleID = 'cecil_test.c'
source_filename = "cecil_test.c"
target datalayout = "e-m:e-p:32:32-i64:64-n32-S128"
target triple = "riscv32-unknown-unknown"

; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none)
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv4, %conv1
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv11, %conv7
  %add = add i32 %mul12, %acc
  %add13 = add i32 %add, %mul
  ret i32 %add13
}

attributes #0 = { mustprogress nofree norecurse nosync nounwind willreturn memory(none) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="generic-rv32" "target-features"="+32bit,+m,+relax,+xseal5testalucvabs16,+xseal5testalucvabs32,+xseal5testalucvabs8,+xseal5testalucvaddnrsi16,+xseal5testalucvaddnrsi32,+xseal5testalucvaddnrui16,+xseal5testalucvaddnrui32,+xseal5testalucvaddns,+xseal5testalucvaddnu,+xseal5testalucvaddrnrsi16,+xseal5testalucvaddrnrsi32,+xseal5testalucvaddrnrui16,+xseal5testalucvaddrnrui32,+xseal5testalucvaddrns,+xseal5testalucvaddrnu,+xseal5testalucvextbs,+xseal5testalucvextbz,+xseal5testalucvexths,+xseal5testalucvexthz,+xseal5testalucvmaxi1216,+xseal5testalucvmaxi1232,+xseal5testalucvmaxi516,+xseal5testalucvmaxi532,+xseal5testalucvmaxs16,+xseal5testalucvmaxs32,+xseal5testalucvmaxs8,+xseal5testalucvmaxu16,+xseal5testalucvmaxu32,+xseal5testalucvmaxu8,+xseal5testalucvmini1216,+xseal5testalucvmini1232,+xseal5testalucvmini516,+xseal5testalucvmini532,+xseal5testalucvmins16,+xseal5testalucvmins32,+xseal5testalucvmins8,+xseal5testalucvminu16,+xseal5testalucvminu32,+xseal5testalucvminu8,+xseal5testalucvsletsi16,+xseal5testalucvsletsi32,+xseal5testalucvsletui16,+xseal5testalucvsletui32,+xseal5testalucvsubnrsi16,+xseal5testalucvsubnrsi32,+xseal5testalucvsubnrui16,+xseal5testalucvsubnrui32,+xseal5testalucvsubns,+xseal5testalucvsubnu,+xseal5testalucvsubrnrsi16,+xseal5testalucvsubrnrsi32,+xseal5testalucvsubrnrui16,+xseal5testalucvsubrnrui32,+xseal5testalucvsubrns,+xseal5testalucvsubrnu,+xseal5testmaccvmachhns,+xseal5testmaccvmachhnu,+xseal5testmaccvmachhrns,+xseal5testmaccvmachhrnu,+xseal5testmaccvmacns,+xseal5testmaccvmacnu,+xseal5testmaccvmacrns,+xseal5testmaccvmacrnu,+xseal5testmaccvmacsi16,+xseal5testmaccvmacsi32,+xseal5testmaccvmacui16,+xseal5testmaccvmacui32,+xseal5testmaccvmsusi16,+xseal5testmaccvmsusi32,+xseal5testmaccvmsuui16,+xseal5testmaccvmsuui32,+xseal5testmaccvmulhhns,+xseal5testmaccvmulhhnu,+xseal5testmaccvmulhhrns,+xseal5testmaccvmulhhrnu,+xseal5testmaccvmulns,+xseal5testmaccvmulnu,+xseal5testmaccvmulrns,+xseal5testmaccvmulrnu,-a,-c,-d,-e,-experimental-zacas,-experimental-zcmop,-experimental-zfbfmin,-experimental-zicfilp,-experimental-zicfiss,-experimental-zimop,-experimental-ztso,-experimental-zvfbfmin,-experimental-zvfbfwma,-f,-h,-smaia,-smepmp,-ssaia,-svinval,-svnapot,-svpbmt,-v,-xcvalu,-xcvbi,-xcvbitmanip,-xcvelw,-xcvmac,-xcvmem,-xcvsimd,-xsfvcp,-xsfvfnrclipxfqf,-xsfvfwmaccqqq,-xsfvqmaccdod,-xsfvqmaccqoq,-xtheadba,-xtheadbb,-xtheadbs,-xtheadcmo,-xtheadcondmov,-xtheadfmemidx,-xtheadmac,-xtheadmemidx,-xtheadmempair,-xtheadsync,-xtheadvdot,-xventanacondops,-za128rs,-za64rs,-zawrs,-zba,-zbb,-zbc,-zbkb,-zbkc,-zbkx,-zbs,-zca,-zcb,-zcd,-zce,-zcf,-zcmp,-zcmt,-zdinx,-zfa,-zfh,-zfhmin,-zfinx,-zhinx,-zhinxmin,-zic64b,-zicbom,-zicbop,-zicboz,-ziccamoa,-ziccif,-zicclsm,-ziccrse,-zicntr,-zicond,-zicsr,-zifencei,-zihintntl,-zihintpause,-zihpm,-zk,-zkn,-zknd,-zkne,-zknh,-zkr,-zks,-zksed,-zksh,-zkt,-zmmul,-zvbb,-zvbc,-zve32f,-zve32x,-zve64d,-zve64f,-zve64x,-zvfh,-zvfhmin,-zvkb,-zvkg,-zvkn,-zvknc,-zvkned,-zvkng,-zvknha,-zvknhb,-zvks,-zvksc,-zvksed,-zvksg,-zvksh,-zvkt,-zvl1024b,-zvl128b,-zvl16384b,-zvl2048b,-zvl256b,-zvl32768b,-zvl32b,-zvl4096b,-zvl512b,-zvl64b,-zvl65536b,-zvl8192b" }

!llvm.module.flags = !{!0, !1, !2}
!llvm.ident = !{!3}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 1, !"target-abi", !"ilp32"}
!2 = !{i32 8, !"SmallDataLimit", i32 8}
!3 = !{!"clang version 18.1.0rc (https://github.com/llvm/llvm-project.git 1acc4e456481e76822c76c850bad3994d4e04b59)"}
; *** IR Dump Before EliminateAvailableExternallyPass on [module] ***
; ModuleID = 'cecil_test.c'
source_filename = "cecil_test.c"
target datalayout = "e-m:e-p:32:32-i64:64-n32-S128"
target triple = "riscv32-unknown-unknown"

; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none)
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv4, %conv1
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv11, %conv7
  %add = add i32 %mul12, %acc
  %add13 = add i32 %add, %mul
  ret i32 %add13
}

attributes #0 = { mustprogress nofree norecurse nosync nounwind willreturn memory(none) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="generic-rv32" "target-features"="+32bit,+m,+relax,+xseal5testalucvabs16,+xseal5testalucvabs32,+xseal5testalucvabs8,+xseal5testalucvaddnrsi16,+xseal5testalucvaddnrsi32,+xseal5testalucvaddnrui16,+xseal5testalucvaddnrui32,+xseal5testalucvaddns,+xseal5testalucvaddnu,+xseal5testalucvaddrnrsi16,+xseal5testalucvaddrnrsi32,+xseal5testalucvaddrnrui16,+xseal5testalucvaddrnrui32,+xseal5testalucvaddrns,+xseal5testalucvaddrnu,+xseal5testalucvextbs,+xseal5testalucvextbz,+xseal5testalucvexths,+xseal5testalucvexthz,+xseal5testalucvmaxi1216,+xseal5testalucvmaxi1232,+xseal5testalucvmaxi516,+xseal5testalucvmaxi532,+xseal5testalucvmaxs16,+xseal5testalucvmaxs32,+xseal5testalucvmaxs8,+xseal5testalucvmaxu16,+xseal5testalucvmaxu32,+xseal5testalucvmaxu8,+xseal5testalucvmini1216,+xseal5testalucvmini1232,+xseal5testalucvmini516,+xseal5testalucvmini532,+xseal5testalucvmins16,+xseal5testalucvmins32,+xseal5testalucvmins8,+xseal5testalucvminu16,+xseal5testalucvminu32,+xseal5testalucvminu8,+xseal5testalucvsletsi16,+xseal5testalucvsletsi32,+xseal5testalucvsletui16,+xseal5testalucvsletui32,+xseal5testalucvsubnrsi16,+xseal5testalucvsubnrsi32,+xseal5testalucvsubnrui16,+xseal5testalucvsubnrui32,+xseal5testalucvsubns,+xseal5testalucvsubnu,+xseal5testalucvsubrnrsi16,+xseal5testalucvsubrnrsi32,+xseal5testalucvsubrnrui16,+xseal5testalucvsubrnrui32,+xseal5testalucvsubrns,+xseal5testalucvsubrnu,+xseal5testmaccvmachhns,+xseal5testmaccvmachhnu,+xseal5testmaccvmachhrns,+xseal5testmaccvmachhrnu,+xseal5testmaccvmacns,+xseal5testmaccvmacnu,+xseal5testmaccvmacrns,+xseal5testmaccvmacrnu,+xseal5testmaccvmacsi16,+xseal5testmaccvmacsi32,+xseal5testmaccvmacui16,+xseal5testmaccvmacui32,+xseal5testmaccvmsusi16,+xseal5testmaccvmsusi32,+xseal5testmaccvmsuui16,+xseal5testmaccvmsuui32,+xseal5testmaccvmulhhns,+xseal5testmaccvmulhhnu,+xseal5testmaccvmulhhrns,+xseal5testmaccvmulhhrnu,+xseal5testmaccvmulns,+xseal5testmaccvmulnu,+xseal5testmaccvmulrns,+xseal5testmaccvmulrnu,-a,-c,-d,-e,-experimental-zacas,-experimental-zcmop,-experimental-zfbfmin,-experimental-zicfilp,-experimental-zicfiss,-experimental-zimop,-experimental-ztso,-experimental-zvfbfmin,-experimental-zvfbfwma,-f,-h,-smaia,-smepmp,-ssaia,-svinval,-svnapot,-svpbmt,-v,-xcvalu,-xcvbi,-xcvbitmanip,-xcvelw,-xcvmac,-xcvmem,-xcvsimd,-xsfvcp,-xsfvfnrclipxfqf,-xsfvfwmaccqqq,-xsfvqmaccdod,-xsfvqmaccqoq,-xtheadba,-xtheadbb,-xtheadbs,-xtheadcmo,-xtheadcondmov,-xtheadfmemidx,-xtheadmac,-xtheadmemidx,-xtheadmempair,-xtheadsync,-xtheadvdot,-xventanacondops,-za128rs,-za64rs,-zawrs,-zba,-zbb,-zbc,-zbkb,-zbkc,-zbkx,-zbs,-zca,-zcb,-zcd,-zce,-zcf,-zcmp,-zcmt,-zdinx,-zfa,-zfh,-zfhmin,-zfinx,-zhinx,-zhinxmin,-zic64b,-zicbom,-zicbop,-zicboz,-ziccamoa,-ziccif,-zicclsm,-ziccrse,-zicntr,-zicond,-zicsr,-zifencei,-zihintntl,-zihintpause,-zihpm,-zk,-zkn,-zknd,-zkne,-zknh,-zkr,-zks,-zksed,-zksh,-zkt,-zmmul,-zvbb,-zvbc,-zve32f,-zve32x,-zve64d,-zve64f,-zve64x,-zvfh,-zvfhmin,-zvkb,-zvkg,-zvkn,-zvknc,-zvkned,-zvkng,-zvknha,-zvknhb,-zvks,-zvksc,-zvksed,-zvksg,-zvksh,-zvkt,-zvl1024b,-zvl128b,-zvl16384b,-zvl2048b,-zvl256b,-zvl32768b,-zvl32b,-zvl4096b,-zvl512b,-zvl64b,-zvl65536b,-zvl8192b" }

!llvm.module.flags = !{!0, !1, !2}
!llvm.ident = !{!3}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 1, !"target-abi", !"ilp32"}
!2 = !{i32 8, !"SmallDataLimit", i32 8}
!3 = !{!"clang version 18.1.0rc (https://github.com/llvm/llvm-project.git 1acc4e456481e76822c76c850bad3994d4e04b59)"}
; *** IR Dump After EliminateAvailableExternallyPass on [module] ***
; ModuleID = 'cecil_test.c'
source_filename = "cecil_test.c"
target datalayout = "e-m:e-p:32:32-i64:64-n32-S128"
target triple = "riscv32-unknown-unknown"

; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none)
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv4, %conv1
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv11, %conv7
  %add = add i32 %mul12, %acc
  %add13 = add i32 %add, %mul
  ret i32 %add13
}

attributes #0 = { mustprogress nofree norecurse nosync nounwind willreturn memory(none) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="generic-rv32" "target-features"="+32bit,+m,+relax,+xseal5testalucvabs16,+xseal5testalucvabs32,+xseal5testalucvabs8,+xseal5testalucvaddnrsi16,+xseal5testalucvaddnrsi32,+xseal5testalucvaddnrui16,+xseal5testalucvaddnrui32,+xseal5testalucvaddns,+xseal5testalucvaddnu,+xseal5testalucvaddrnrsi16,+xseal5testalucvaddrnrsi32,+xseal5testalucvaddrnrui16,+xseal5testalucvaddrnrui32,+xseal5testalucvaddrns,+xseal5testalucvaddrnu,+xseal5testalucvextbs,+xseal5testalucvextbz,+xseal5testalucvexths,+xseal5testalucvexthz,+xseal5testalucvmaxi1216,+xseal5testalucvmaxi1232,+xseal5testalucvmaxi516,+xseal5testalucvmaxi532,+xseal5testalucvmaxs16,+xseal5testalucvmaxs32,+xseal5testalucvmaxs8,+xseal5testalucvmaxu16,+xseal5testalucvmaxu32,+xseal5testalucvmaxu8,+xseal5testalucvmini1216,+xseal5testalucvmini1232,+xseal5testalucvmini516,+xseal5testalucvmini532,+xseal5testalucvmins16,+xseal5testalucvmins32,+xseal5testalucvmins8,+xseal5testalucvminu16,+xseal5testalucvminu32,+xseal5testalucvminu8,+xseal5testalucvsletsi16,+xseal5testalucvsletsi32,+xseal5testalucvsletui16,+xseal5testalucvsletui32,+xseal5testalucvsubnrsi16,+xseal5testalucvsubnrsi32,+xseal5testalucvsubnrui16,+xseal5testalucvsubnrui32,+xseal5testalucvsubns,+xseal5testalucvsubnu,+xseal5testalucvsubrnrsi16,+xseal5testalucvsubrnrsi32,+xseal5testalucvsubrnrui16,+xseal5testalucvsubrnrui32,+xseal5testalucvsubrns,+xseal5testalucvsubrnu,+xseal5testmaccvmachhns,+xseal5testmaccvmachhnu,+xseal5testmaccvmachhrns,+xseal5testmaccvmachhrnu,+xseal5testmaccvmacns,+xseal5testmaccvmacnu,+xseal5testmaccvmacrns,+xseal5testmaccvmacrnu,+xseal5testmaccvmacsi16,+xseal5testmaccvmacsi32,+xseal5testmaccvmacui16,+xseal5testmaccvmacui32,+xseal5testmaccvmsusi16,+xseal5testmaccvmsusi32,+xseal5testmaccvmsuui16,+xseal5testmaccvmsuui32,+xseal5testmaccvmulhhns,+xseal5testmaccvmulhhnu,+xseal5testmaccvmulhhrns,+xseal5testmaccvmulhhrnu,+xseal5testmaccvmulns,+xseal5testmaccvmulnu,+xseal5testmaccvmulrns,+xseal5testmaccvmulrnu,-a,-c,-d,-e,-experimental-zacas,-experimental-zcmop,-experimental-zfbfmin,-experimental-zicfilp,-experimental-zicfiss,-experimental-zimop,-experimental-ztso,-experimental-zvfbfmin,-experimental-zvfbfwma,-f,-h,-smaia,-smepmp,-ssaia,-svinval,-svnapot,-svpbmt,-v,-xcvalu,-xcvbi,-xcvbitmanip,-xcvelw,-xcvmac,-xcvmem,-xcvsimd,-xsfvcp,-xsfvfnrclipxfqf,-xsfvfwmaccqqq,-xsfvqmaccdod,-xsfvqmaccqoq,-xtheadba,-xtheadbb,-xtheadbs,-xtheadcmo,-xtheadcondmov,-xtheadfmemidx,-xtheadmac,-xtheadmemidx,-xtheadmempair,-xtheadsync,-xtheadvdot,-xventanacondops,-za128rs,-za64rs,-zawrs,-zba,-zbb,-zbc,-zbkb,-zbkc,-zbkx,-zbs,-zca,-zcb,-zcd,-zce,-zcf,-zcmp,-zcmt,-zdinx,-zfa,-zfh,-zfhmin,-zfinx,-zhinx,-zhinxmin,-zic64b,-zicbom,-zicbop,-zicboz,-ziccamoa,-ziccif,-zicclsm,-ziccrse,-zicntr,-zicond,-zicsr,-zifencei,-zihintntl,-zihintpause,-zihpm,-zk,-zkn,-zknd,-zkne,-zknh,-zkr,-zks,-zksed,-zksh,-zkt,-zmmul,-zvbb,-zvbc,-zve32f,-zve32x,-zve64d,-zve64f,-zve64x,-zvfh,-zvfhmin,-zvkb,-zvkg,-zvkn,-zvknc,-zvkned,-zvkng,-zvknha,-zvknhb,-zvks,-zvksc,-zvksed,-zvksg,-zvksh,-zvkt,-zvl1024b,-zvl128b,-zvl16384b,-zvl2048b,-zvl256b,-zvl32768b,-zvl32b,-zvl4096b,-zvl512b,-zvl64b,-zvl65536b,-zvl8192b" }

!llvm.module.flags = !{!0, !1, !2}
!llvm.ident = !{!3}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 1, !"target-abi", !"ilp32"}
!2 = !{i32 8, !"SmallDataLimit", i32 8}
!3 = !{!"clang version 18.1.0rc (https://github.com/llvm/llvm-project.git 1acc4e456481e76822c76c850bad3994d4e04b59)"}
; *** IR Dump Before ReversePostOrderFunctionAttrsPass on [module] ***
; ModuleID = 'cecil_test.c'
source_filename = "cecil_test.c"
target datalayout = "e-m:e-p:32:32-i64:64-n32-S128"
target triple = "riscv32-unknown-unknown"

; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none)
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv4, %conv1
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv11, %conv7
  %add = add i32 %mul12, %acc
  %add13 = add i32 %add, %mul
  ret i32 %add13
}

attributes #0 = { mustprogress nofree norecurse nosync nounwind willreturn memory(none) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="generic-rv32" "target-features"="+32bit,+m,+relax,+xseal5testalucvabs16,+xseal5testalucvabs32,+xseal5testalucvabs8,+xseal5testalucvaddnrsi16,+xseal5testalucvaddnrsi32,+xseal5testalucvaddnrui16,+xseal5testalucvaddnrui32,+xseal5testalucvaddns,+xseal5testalucvaddnu,+xseal5testalucvaddrnrsi16,+xseal5testalucvaddrnrsi32,+xseal5testalucvaddrnrui16,+xseal5testalucvaddrnrui32,+xseal5testalucvaddrns,+xseal5testalucvaddrnu,+xseal5testalucvextbs,+xseal5testalucvextbz,+xseal5testalucvexths,+xseal5testalucvexthz,+xseal5testalucvmaxi1216,+xseal5testalucvmaxi1232,+xseal5testalucvmaxi516,+xseal5testalucvmaxi532,+xseal5testalucvmaxs16,+xseal5testalucvmaxs32,+xseal5testalucvmaxs8,+xseal5testalucvmaxu16,+xseal5testalucvmaxu32,+xseal5testalucvmaxu8,+xseal5testalucvmini1216,+xseal5testalucvmini1232,+xseal5testalucvmini516,+xseal5testalucvmini532,+xseal5testalucvmins16,+xseal5testalucvmins32,+xseal5testalucvmins8,+xseal5testalucvminu16,+xseal5testalucvminu32,+xseal5testalucvminu8,+xseal5testalucvsletsi16,+xseal5testalucvsletsi32,+xseal5testalucvsletui16,+xseal5testalucvsletui32,+xseal5testalucvsubnrsi16,+xseal5testalucvsubnrsi32,+xseal5testalucvsubnrui16,+xseal5testalucvsubnrui32,+xseal5testalucvsubns,+xseal5testalucvsubnu,+xseal5testalucvsubrnrsi16,+xseal5testalucvsubrnrsi32,+xseal5testalucvsubrnrui16,+xseal5testalucvsubrnrui32,+xseal5testalucvsubrns,+xseal5testalucvsubrnu,+xseal5testmaccvmachhns,+xseal5testmaccvmachhnu,+xseal5testmaccvmachhrns,+xseal5testmaccvmachhrnu,+xseal5testmaccvmacns,+xseal5testmaccvmacnu,+xseal5testmaccvmacrns,+xseal5testmaccvmacrnu,+xseal5testmaccvmacsi16,+xseal5testmaccvmacsi32,+xseal5testmaccvmacui16,+xseal5testmaccvmacui32,+xseal5testmaccvmsusi16,+xseal5testmaccvmsusi32,+xseal5testmaccvmsuui16,+xseal5testmaccvmsuui32,+xseal5testmaccvmulhhns,+xseal5testmaccvmulhhnu,+xseal5testmaccvmulhhrns,+xseal5testmaccvmulhhrnu,+xseal5testmaccvmulns,+xseal5testmaccvmulnu,+xseal5testmaccvmulrns,+xseal5testmaccvmulrnu,-a,-c,-d,-e,-experimental-zacas,-experimental-zcmop,-experimental-zfbfmin,-experimental-zicfilp,-experimental-zicfiss,-experimental-zimop,-experimental-ztso,-experimental-zvfbfmin,-experimental-zvfbfwma,-f,-h,-smaia,-smepmp,-ssaia,-svinval,-svnapot,-svpbmt,-v,-xcvalu,-xcvbi,-xcvbitmanip,-xcvelw,-xcvmac,-xcvmem,-xcvsimd,-xsfvcp,-xsfvfnrclipxfqf,-xsfvfwmaccqqq,-xsfvqmaccdod,-xsfvqmaccqoq,-xtheadba,-xtheadbb,-xtheadbs,-xtheadcmo,-xtheadcondmov,-xtheadfmemidx,-xtheadmac,-xtheadmemidx,-xtheadmempair,-xtheadsync,-xtheadvdot,-xventanacondops,-za128rs,-za64rs,-zawrs,-zba,-zbb,-zbc,-zbkb,-zbkc,-zbkx,-zbs,-zca,-zcb,-zcd,-zce,-zcf,-zcmp,-zcmt,-zdinx,-zfa,-zfh,-zfhmin,-zfinx,-zhinx,-zhinxmin,-zic64b,-zicbom,-zicbop,-zicboz,-ziccamoa,-ziccif,-zicclsm,-ziccrse,-zicntr,-zicond,-zicsr,-zifencei,-zihintntl,-zihintpause,-zihpm,-zk,-zkn,-zknd,-zkne,-zknh,-zkr,-zks,-zksed,-zksh,-zkt,-zmmul,-zvbb,-zvbc,-zve32f,-zve32x,-zve64d,-zve64f,-zve64x,-zvfh,-zvfhmin,-zvkb,-zvkg,-zvkn,-zvknc,-zvkned,-zvkng,-zvknha,-zvknhb,-zvks,-zvksc,-zvksed,-zvksg,-zvksh,-zvkt,-zvl1024b,-zvl128b,-zvl16384b,-zvl2048b,-zvl256b,-zvl32768b,-zvl32b,-zvl4096b,-zvl512b,-zvl64b,-zvl65536b,-zvl8192b" }

!llvm.module.flags = !{!0, !1, !2}
!llvm.ident = !{!3}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 1, !"target-abi", !"ilp32"}
!2 = !{i32 8, !"SmallDataLimit", i32 8}
!3 = !{!"clang version 18.1.0rc (https://github.com/llvm/llvm-project.git 1acc4e456481e76822c76c850bad3994d4e04b59)"}
; *** IR Dump After ReversePostOrderFunctionAttrsPass on [module] ***
; ModuleID = 'cecil_test.c'
source_filename = "cecil_test.c"
target datalayout = "e-m:e-p:32:32-i64:64-n32-S128"
target triple = "riscv32-unknown-unknown"

; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none)
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv4, %conv1
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv11, %conv7
  %add = add i32 %mul12, %acc
  %add13 = add i32 %add, %mul
  ret i32 %add13
}

attributes #0 = { mustprogress nofree norecurse nosync nounwind willreturn memory(none) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="generic-rv32" "target-features"="+32bit,+m,+relax,+xseal5testalucvabs16,+xseal5testalucvabs32,+xseal5testalucvabs8,+xseal5testalucvaddnrsi16,+xseal5testalucvaddnrsi32,+xseal5testalucvaddnrui16,+xseal5testalucvaddnrui32,+xseal5testalucvaddns,+xseal5testalucvaddnu,+xseal5testalucvaddrnrsi16,+xseal5testalucvaddrnrsi32,+xseal5testalucvaddrnrui16,+xseal5testalucvaddrnrui32,+xseal5testalucvaddrns,+xseal5testalucvaddrnu,+xseal5testalucvextbs,+xseal5testalucvextbz,+xseal5testalucvexths,+xseal5testalucvexthz,+xseal5testalucvmaxi1216,+xseal5testalucvmaxi1232,+xseal5testalucvmaxi516,+xseal5testalucvmaxi532,+xseal5testalucvmaxs16,+xseal5testalucvmaxs32,+xseal5testalucvmaxs8,+xseal5testalucvmaxu16,+xseal5testalucvmaxu32,+xseal5testalucvmaxu8,+xseal5testalucvmini1216,+xseal5testalucvmini1232,+xseal5testalucvmini516,+xseal5testalucvmini532,+xseal5testalucvmins16,+xseal5testalucvmins32,+xseal5testalucvmins8,+xseal5testalucvminu16,+xseal5testalucvminu32,+xseal5testalucvminu8,+xseal5testalucvsletsi16,+xseal5testalucvsletsi32,+xseal5testalucvsletui16,+xseal5testalucvsletui32,+xseal5testalucvsubnrsi16,+xseal5testalucvsubnrsi32,+xseal5testalucvsubnrui16,+xseal5testalucvsubnrui32,+xseal5testalucvsubns,+xseal5testalucvsubnu,+xseal5testalucvsubrnrsi16,+xseal5testalucvsubrnrsi32,+xseal5testalucvsubrnrui16,+xseal5testalucvsubrnrui32,+xseal5testalucvsubrns,+xseal5testalucvsubrnu,+xseal5testmaccvmachhns,+xseal5testmaccvmachhnu,+xseal5testmaccvmachhrns,+xseal5testmaccvmachhrnu,+xseal5testmaccvmacns,+xseal5testmaccvmacnu,+xseal5testmaccvmacrns,+xseal5testmaccvmacrnu,+xseal5testmaccvmacsi16,+xseal5testmaccvmacsi32,+xseal5testmaccvmacui16,+xseal5testmaccvmacui32,+xseal5testmaccvmsusi16,+xseal5testmaccvmsusi32,+xseal5testmaccvmsuui16,+xseal5testmaccvmsuui32,+xseal5testmaccvmulhhns,+xseal5testmaccvmulhhnu,+xseal5testmaccvmulhhrns,+xseal5testmaccvmulhhrnu,+xseal5testmaccvmulns,+xseal5testmaccvmulnu,+xseal5testmaccvmulrns,+xseal5testmaccvmulrnu,-a,-c,-d,-e,-experimental-zacas,-experimental-zcmop,-experimental-zfbfmin,-experimental-zicfilp,-experimental-zicfiss,-experimental-zimop,-experimental-ztso,-experimental-zvfbfmin,-experimental-zvfbfwma,-f,-h,-smaia,-smepmp,-ssaia,-svinval,-svnapot,-svpbmt,-v,-xcvalu,-xcvbi,-xcvbitmanip,-xcvelw,-xcvmac,-xcvmem,-xcvsimd,-xsfvcp,-xsfvfnrclipxfqf,-xsfvfwmaccqqq,-xsfvqmaccdod,-xsfvqmaccqoq,-xtheadba,-xtheadbb,-xtheadbs,-xtheadcmo,-xtheadcondmov,-xtheadfmemidx,-xtheadmac,-xtheadmemidx,-xtheadmempair,-xtheadsync,-xtheadvdot,-xventanacondops,-za128rs,-za64rs,-zawrs,-zba,-zbb,-zbc,-zbkb,-zbkc,-zbkx,-zbs,-zca,-zcb,-zcd,-zce,-zcf,-zcmp,-zcmt,-zdinx,-zfa,-zfh,-zfhmin,-zfinx,-zhinx,-zhinxmin,-zic64b,-zicbom,-zicbop,-zicboz,-ziccamoa,-ziccif,-zicclsm,-ziccrse,-zicntr,-zicond,-zicsr,-zifencei,-zihintntl,-zihintpause,-zihpm,-zk,-zkn,-zknd,-zkne,-zknh,-zkr,-zks,-zksed,-zksh,-zkt,-zmmul,-zvbb,-zvbc,-zve32f,-zve32x,-zve64d,-zve64f,-zve64x,-zvfh,-zvfhmin,-zvkb,-zvkg,-zvkn,-zvknc,-zvkned,-zvkng,-zvknha,-zvknhb,-zvks,-zvksc,-zvksed,-zvksg,-zvksh,-zvkt,-zvl1024b,-zvl128b,-zvl16384b,-zvl2048b,-zvl256b,-zvl32768b,-zvl32b,-zvl4096b,-zvl512b,-zvl64b,-zvl65536b,-zvl8192b" }

!llvm.module.flags = !{!0, !1, !2}
!llvm.ident = !{!3}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 1, !"target-abi", !"ilp32"}
!2 = !{i32 8, !"SmallDataLimit", i32 8}
!3 = !{!"clang version 18.1.0rc (https://github.com/llvm/llvm-project.git 1acc4e456481e76822c76c850bad3994d4e04b59)"}
; *** IR Dump Before RecomputeGlobalsAAPass on [module] ***
; ModuleID = 'cecil_test.c'
source_filename = "cecil_test.c"
target datalayout = "e-m:e-p:32:32-i64:64-n32-S128"
target triple = "riscv32-unknown-unknown"

; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none)
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv4, %conv1
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv11, %conv7
  %add = add i32 %mul12, %acc
  %add13 = add i32 %add, %mul
  ret i32 %add13
}

attributes #0 = { mustprogress nofree norecurse nosync nounwind willreturn memory(none) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="generic-rv32" "target-features"="+32bit,+m,+relax,+xseal5testalucvabs16,+xseal5testalucvabs32,+xseal5testalucvabs8,+xseal5testalucvaddnrsi16,+xseal5testalucvaddnrsi32,+xseal5testalucvaddnrui16,+xseal5testalucvaddnrui32,+xseal5testalucvaddns,+xseal5testalucvaddnu,+xseal5testalucvaddrnrsi16,+xseal5testalucvaddrnrsi32,+xseal5testalucvaddrnrui16,+xseal5testalucvaddrnrui32,+xseal5testalucvaddrns,+xseal5testalucvaddrnu,+xseal5testalucvextbs,+xseal5testalucvextbz,+xseal5testalucvexths,+xseal5testalucvexthz,+xseal5testalucvmaxi1216,+xseal5testalucvmaxi1232,+xseal5testalucvmaxi516,+xseal5testalucvmaxi532,+xseal5testalucvmaxs16,+xseal5testalucvmaxs32,+xseal5testalucvmaxs8,+xseal5testalucvmaxu16,+xseal5testalucvmaxu32,+xseal5testalucvmaxu8,+xseal5testalucvmini1216,+xseal5testalucvmini1232,+xseal5testalucvmini516,+xseal5testalucvmini532,+xseal5testalucvmins16,+xseal5testalucvmins32,+xseal5testalucvmins8,+xseal5testalucvminu16,+xseal5testalucvminu32,+xseal5testalucvminu8,+xseal5testalucvsletsi16,+xseal5testalucvsletsi32,+xseal5testalucvsletui16,+xseal5testalucvsletui32,+xseal5testalucvsubnrsi16,+xseal5testalucvsubnrsi32,+xseal5testalucvsubnrui16,+xseal5testalucvsubnrui32,+xseal5testalucvsubns,+xseal5testalucvsubnu,+xseal5testalucvsubrnrsi16,+xseal5testalucvsubrnrsi32,+xseal5testalucvsubrnrui16,+xseal5testalucvsubrnrui32,+xseal5testalucvsubrns,+xseal5testalucvsubrnu,+xseal5testmaccvmachhns,+xseal5testmaccvmachhnu,+xseal5testmaccvmachhrns,+xseal5testmaccvmachhrnu,+xseal5testmaccvmacns,+xseal5testmaccvmacnu,+xseal5testmaccvmacrns,+xseal5testmaccvmacrnu,+xseal5testmaccvmacsi16,+xseal5testmaccvmacsi32,+xseal5testmaccvmacui16,+xseal5testmaccvmacui32,+xseal5testmaccvmsusi16,+xseal5testmaccvmsusi32,+xseal5testmaccvmsuui16,+xseal5testmaccvmsuui32,+xseal5testmaccvmulhhns,+xseal5testmaccvmulhhnu,+xseal5testmaccvmulhhrns,+xseal5testmaccvmulhhrnu,+xseal5testmaccvmulns,+xseal5testmaccvmulnu,+xseal5testmaccvmulrns,+xseal5testmaccvmulrnu,-a,-c,-d,-e,-experimental-zacas,-experimental-zcmop,-experimental-zfbfmin,-experimental-zicfilp,-experimental-zicfiss,-experimental-zimop,-experimental-ztso,-experimental-zvfbfmin,-experimental-zvfbfwma,-f,-h,-smaia,-smepmp,-ssaia,-svinval,-svnapot,-svpbmt,-v,-xcvalu,-xcvbi,-xcvbitmanip,-xcvelw,-xcvmac,-xcvmem,-xcvsimd,-xsfvcp,-xsfvfnrclipxfqf,-xsfvfwmaccqqq,-xsfvqmaccdod,-xsfvqmaccqoq,-xtheadba,-xtheadbb,-xtheadbs,-xtheadcmo,-xtheadcondmov,-xtheadfmemidx,-xtheadmac,-xtheadmemidx,-xtheadmempair,-xtheadsync,-xtheadvdot,-xventanacondops,-za128rs,-za64rs,-zawrs,-zba,-zbb,-zbc,-zbkb,-zbkc,-zbkx,-zbs,-zca,-zcb,-zcd,-zce,-zcf,-zcmp,-zcmt,-zdinx,-zfa,-zfh,-zfhmin,-zfinx,-zhinx,-zhinxmin,-zic64b,-zicbom,-zicbop,-zicboz,-ziccamoa,-ziccif,-zicclsm,-ziccrse,-zicntr,-zicond,-zicsr,-zifencei,-zihintntl,-zihintpause,-zihpm,-zk,-zkn,-zknd,-zkne,-zknh,-zkr,-zks,-zksed,-zksh,-zkt,-zmmul,-zvbb,-zvbc,-zve32f,-zve32x,-zve64d,-zve64f,-zve64x,-zvfh,-zvfhmin,-zvkb,-zvkg,-zvkn,-zvknc,-zvkned,-zvkng,-zvknha,-zvknhb,-zvks,-zvksc,-zvksed,-zvksg,-zvksh,-zvkt,-zvl1024b,-zvl128b,-zvl16384b,-zvl2048b,-zvl256b,-zvl32768b,-zvl32b,-zvl4096b,-zvl512b,-zvl64b,-zvl65536b,-zvl8192b" }

!llvm.module.flags = !{!0, !1, !2}
!llvm.ident = !{!3}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 1, !"target-abi", !"ilp32"}
!2 = !{i32 8, !"SmallDataLimit", i32 8}
!3 = !{!"clang version 18.1.0rc (https://github.com/llvm/llvm-project.git 1acc4e456481e76822c76c850bad3994d4e04b59)"}
; *** IR Dump After RecomputeGlobalsAAPass on [module] ***
; ModuleID = 'cecil_test.c'
source_filename = "cecil_test.c"
target datalayout = "e-m:e-p:32:32-i64:64-n32-S128"
target triple = "riscv32-unknown-unknown"

; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none)
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv4, %conv1
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv11, %conv7
  %add = add i32 %mul12, %acc
  %add13 = add i32 %add, %mul
  ret i32 %add13
}

attributes #0 = { mustprogress nofree norecurse nosync nounwind willreturn memory(none) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="generic-rv32" "target-features"="+32bit,+m,+relax,+xseal5testalucvabs16,+xseal5testalucvabs32,+xseal5testalucvabs8,+xseal5testalucvaddnrsi16,+xseal5testalucvaddnrsi32,+xseal5testalucvaddnrui16,+xseal5testalucvaddnrui32,+xseal5testalucvaddns,+xseal5testalucvaddnu,+xseal5testalucvaddrnrsi16,+xseal5testalucvaddrnrsi32,+xseal5testalucvaddrnrui16,+xseal5testalucvaddrnrui32,+xseal5testalucvaddrns,+xseal5testalucvaddrnu,+xseal5testalucvextbs,+xseal5testalucvextbz,+xseal5testalucvexths,+xseal5testalucvexthz,+xseal5testalucvmaxi1216,+xseal5testalucvmaxi1232,+xseal5testalucvmaxi516,+xseal5testalucvmaxi532,+xseal5testalucvmaxs16,+xseal5testalucvmaxs32,+xseal5testalucvmaxs8,+xseal5testalucvmaxu16,+xseal5testalucvmaxu32,+xseal5testalucvmaxu8,+xseal5testalucvmini1216,+xseal5testalucvmini1232,+xseal5testalucvmini516,+xseal5testalucvmini532,+xseal5testalucvmins16,+xseal5testalucvmins32,+xseal5testalucvmins8,+xseal5testalucvminu16,+xseal5testalucvminu32,+xseal5testalucvminu8,+xseal5testalucvsletsi16,+xseal5testalucvsletsi32,+xseal5testalucvsletui16,+xseal5testalucvsletui32,+xseal5testalucvsubnrsi16,+xseal5testalucvsubnrsi32,+xseal5testalucvsubnrui16,+xseal5testalucvsubnrui32,+xseal5testalucvsubns,+xseal5testalucvsubnu,+xseal5testalucvsubrnrsi16,+xseal5testalucvsubrnrsi32,+xseal5testalucvsubrnrui16,+xseal5testalucvsubrnrui32,+xseal5testalucvsubrns,+xseal5testalucvsubrnu,+xseal5testmaccvmachhns,+xseal5testmaccvmachhnu,+xseal5testmaccvmachhrns,+xseal5testmaccvmachhrnu,+xseal5testmaccvmacns,+xseal5testmaccvmacnu,+xseal5testmaccvmacrns,+xseal5testmaccvmacrnu,+xseal5testmaccvmacsi16,+xseal5testmaccvmacsi32,+xseal5testmaccvmacui16,+xseal5testmaccvmacui32,+xseal5testmaccvmsusi16,+xseal5testmaccvmsusi32,+xseal5testmaccvmsuui16,+xseal5testmaccvmsuui32,+xseal5testmaccvmulhhns,+xseal5testmaccvmulhhnu,+xseal5testmaccvmulhhrns,+xseal5testmaccvmulhhrnu,+xseal5testmaccvmulns,+xseal5testmaccvmulnu,+xseal5testmaccvmulrns,+xseal5testmaccvmulrnu,-a,-c,-d,-e,-experimental-zacas,-experimental-zcmop,-experimental-zfbfmin,-experimental-zicfilp,-experimental-zicfiss,-experimental-zimop,-experimental-ztso,-experimental-zvfbfmin,-experimental-zvfbfwma,-f,-h,-smaia,-smepmp,-ssaia,-svinval,-svnapot,-svpbmt,-v,-xcvalu,-xcvbi,-xcvbitmanip,-xcvelw,-xcvmac,-xcvmem,-xcvsimd,-xsfvcp,-xsfvfnrclipxfqf,-xsfvfwmaccqqq,-xsfvqmaccdod,-xsfvqmaccqoq,-xtheadba,-xtheadbb,-xtheadbs,-xtheadcmo,-xtheadcondmov,-xtheadfmemidx,-xtheadmac,-xtheadmemidx,-xtheadmempair,-xtheadsync,-xtheadvdot,-xventanacondops,-za128rs,-za64rs,-zawrs,-zba,-zbb,-zbc,-zbkb,-zbkc,-zbkx,-zbs,-zca,-zcb,-zcd,-zce,-zcf,-zcmp,-zcmt,-zdinx,-zfa,-zfh,-zfhmin,-zfinx,-zhinx,-zhinxmin,-zic64b,-zicbom,-zicbop,-zicboz,-ziccamoa,-ziccif,-zicclsm,-ziccrse,-zicntr,-zicond,-zicsr,-zifencei,-zihintntl,-zihintpause,-zihpm,-zk,-zkn,-zknd,-zkne,-zknh,-zkr,-zks,-zksed,-zksh,-zkt,-zmmul,-zvbb,-zvbc,-zve32f,-zve32x,-zve64d,-zve64f,-zve64x,-zvfh,-zvfhmin,-zvkb,-zvkg,-zvkn,-zvknc,-zvkned,-zvkng,-zvknha,-zvknhb,-zvks,-zvksc,-zvksed,-zvksg,-zvksh,-zvkt,-zvl1024b,-zvl128b,-zvl16384b,-zvl2048b,-zvl256b,-zvl32768b,-zvl32b,-zvl4096b,-zvl512b,-zvl64b,-zvl65536b,-zvl8192b" }

!llvm.module.flags = !{!0, !1, !2}
!llvm.ident = !{!3}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 1, !"target-abi", !"ilp32"}
!2 = !{i32 8, !"SmallDataLimit", i32 8}
!3 = !{!"clang version 18.1.0rc (https://github.com/llvm/llvm-project.git 1acc4e456481e76822c76c850bad3994d4e04b59)"}
; *** IR Dump Before Float2IntPass on test_macs32_v2i16 ***
; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none)
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv4, %conv1
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv11, %conv7
  %add = add i32 %mul12, %acc
  %add13 = add i32 %add, %mul
  ret i32 %add13
}
F2I: Looking at function test_macs32_v2i16
; *** IR Dump After Float2IntPass on test_macs32_v2i16 ***
; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none)
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv4, %conv1
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv11, %conv7
  %add = add i32 %mul12, %acc
  %add13 = add i32 %add, %mul
  ret i32 %add13
}
; *** IR Dump Before LowerConstantIntrinsicsPass on test_macs32_v2i16 ***
; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none)
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv4, %conv1
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv11, %conv7
  %add = add i32 %mul12, %acc
  %add13 = add i32 %add, %mul
  ret i32 %add13
}
; *** IR Dump After LowerConstantIntrinsicsPass on test_macs32_v2i16 ***
; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none)
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv4, %conv1
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv11, %conv7
  %add = add i32 %mul12, %acc
  %add13 = add i32 %add, %mul
  ret i32 %add13
}
; *** IR Dump Before ControlHeightReductionPass on test_macs32_v2i16 ***
; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none)
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv4, %conv1
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv11, %conv7
  %add = add i32 %mul12, %acc
  %add13 = add i32 %add, %mul
  ret i32 %add13
}
; *** IR Dump After ControlHeightReductionPass on test_macs32_v2i16 ***
; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none)
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv4, %conv1
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv11, %conv7
  %add = add i32 %mul12, %acc
  %add13 = add i32 %add, %mul
  ret i32 %add13
}
; *** IR Dump Before LoopSimplifyPass on test_macs32_v2i16 ***
; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none)
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv4, %conv1
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv11, %conv7
  %add = add i32 %mul12, %acc
  %add13 = add i32 %add, %mul
  ret i32 %add13
}
; *** IR Dump After LoopSimplifyPass on test_macs32_v2i16 ***
; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none)
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv4, %conv1
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv11, %conv7
  %add = add i32 %mul12, %acc
  %add13 = add i32 %add, %mul
  ret i32 %add13
}
; *** IR Dump Before LCSSAPass on test_macs32_v2i16 ***
; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none)
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv4, %conv1
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv11, %conv7
  %add = add i32 %mul12, %acc
  %add13 = add i32 %add, %mul
  ret i32 %add13
}
; *** IR Dump After LCSSAPass on test_macs32_v2i16 ***
; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none)
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv4, %conv1
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv11, %conv7
  %add = add i32 %mul12, %acc
  %add13 = add i32 %add, %mul
  ret i32 %add13
}
; *** IR Dump Before LoopDistributePass on test_macs32_v2i16 ***
; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none)
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv4, %conv1
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv11, %conv7
  %add = add i32 %mul12, %acc
  %add13 = add i32 %add, %mul
  ret i32 %add13
}
; *** IR Dump After LoopDistributePass on test_macs32_v2i16 ***
; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none)
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv4, %conv1
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv11, %conv7
  %add = add i32 %mul12, %acc
  %add13 = add i32 %add, %mul
  ret i32 %add13
}
; *** IR Dump Before InjectTLIMappings on test_macs32_v2i16 ***
; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none)
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv4, %conv1
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv11, %conv7
  %add = add i32 %mul12, %acc
  %add13 = add i32 %add, %mul
  ret i32 %add13
}
; *** IR Dump After InjectTLIMappings on test_macs32_v2i16 ***
; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none)
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv4, %conv1
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv11, %conv7
  %add = add i32 %mul12, %acc
  %add13 = add i32 %add, %mul
  ret i32 %add13
}
; *** IR Dump Before LoopVectorizePass on test_macs32_v2i16 ***
; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none)
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv4, %conv1
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv11, %conv7
  %add = add i32 %mul12, %acc
  %add13 = add i32 %add, %mul
  ret i32 %add13
}
; *** IR Dump After LoopVectorizePass on test_macs32_v2i16 ***
; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none)
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv4, %conv1
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv11, %conv7
  %add = add i32 %mul12, %acc
  %add13 = add i32 %add, %mul
  ret i32 %add13
}
; *** IR Dump Before InferAlignmentPass on test_macs32_v2i16 ***
; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none)
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv4, %conv1
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv11, %conv7
  %add = add i32 %mul12, %acc
  %add13 = add i32 %add, %mul
  ret i32 %add13
}
; *** IR Dump After InferAlignmentPass on test_macs32_v2i16 ***
; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none)
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv4, %conv1
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv11, %conv7
  %add = add i32 %mul12, %acc
  %add13 = add i32 %add, %mul
  ret i32 %add13
}
; *** IR Dump Before LoopLoadEliminationPass on test_macs32_v2i16 ***
; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none)
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv4, %conv1
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv11, %conv7
  %add = add i32 %mul12, %acc
  %add13 = add i32 %add, %mul
  ret i32 %add13
}
; *** IR Dump After LoopLoadEliminationPass on test_macs32_v2i16 ***
; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none)
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv4, %conv1
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv11, %conv7
  %add = add i32 %mul12, %acc
  %add13 = add i32 %add, %mul
  ret i32 %add13
}
; *** IR Dump Before InstCombinePass on test_macs32_v2i16 ***
; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none)
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv4, %conv1
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv11, %conv7
  %add = add i32 %mul12, %acc
  %add13 = add i32 %add, %mul
  ret i32 %add13
}


INSTCOMBINE ITERATION #1 on test_macs32_v2i16
ADD:   ret i32 %add13
ADD:   %add13 = add i32 %add, %mul
ADD:   %add = add i32 %mul12, %acc
ADD:   %mul12 = mul nsw i32 %conv11, %conv7
ADD:   %conv11 = ashr i32 %y, 16
ADD:   %conv7 = ashr i32 %x, 16
ADD:   %mul = mul nsw i32 %conv4, %conv1
ADD:   %conv4 = ashr exact i32 %sext18, 16
ADD:   %sext18 = shl i32 %y, 16
ADD:   %conv1 = ashr exact i32 %sext, 16
ADD:   %sext = shl i32 %x, 16
IC: Visiting:   %sext = shl i32 %x, 16
IC: Visiting:   %conv1 = ashr exact i32 %sext, 16
IC: Visiting:   %sext18 = shl i32 %y, 16
IC: Visiting:   %conv4 = ashr exact i32 %sext18, 16
IC: Visiting:   %mul = mul nsw i32 %conv4, %conv1
IC: Visiting:   %conv7 = ashr i32 %x, 16
IC: Visiting:   %conv11 = ashr i32 %y, 16
IC: Visiting:   %mul12 = mul nsw i32 %conv11, %conv7
IC: Visiting:   %add = add i32 %mul12, %acc
IC: Visiting:   %add13 = add i32 %add, %mul
IC: Visiting:   ret i32 %add13
; *** IR Dump After InstCombinePass on test_macs32_v2i16 ***
; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none)
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv4, %conv1
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv11, %conv7
  %add = add i32 %mul12, %acc
  %add13 = add i32 %add, %mul
  ret i32 %add13
}
; *** IR Dump Before SimplifyCFGPass on test_macs32_v2i16 ***
; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none)
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv4, %conv1
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv11, %conv7
  %add = add i32 %mul12, %acc
  %add13 = add i32 %add, %mul
  ret i32 %add13
}
; *** IR Dump After SimplifyCFGPass on test_macs32_v2i16 ***
; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none)
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv4, %conv1
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv11, %conv7
  %add = add i32 %mul12, %acc
  %add13 = add i32 %add, %mul
  ret i32 %add13
}
; *** IR Dump Before SLPVectorizerPass on test_macs32_v2i16 ***
; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none)
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv4, %conv1
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv11, %conv7
  %add = add i32 %mul12, %acc
  %add13 = add i32 %add, %mul
  ret i32 %add13
}
SLP: Didn't find any vector registers for target, abort.
; *** IR Dump After SLPVectorizerPass on test_macs32_v2i16 ***
; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none)
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv4, %conv1
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv11, %conv7
  %add = add i32 %mul12, %acc
  %add13 = add i32 %add, %mul
  ret i32 %add13
}
; *** IR Dump Before VectorCombinePass on test_macs32_v2i16 ***
; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none)
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv4, %conv1
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv11, %conv7
  %add = add i32 %mul12, %acc
  %add13 = add i32 %add, %mul
  ret i32 %add13
}
; *** IR Dump After VectorCombinePass on test_macs32_v2i16 ***
; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none)
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv4, %conv1
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv11, %conv7
  %add = add i32 %mul12, %acc
  %add13 = add i32 %add, %mul
  ret i32 %add13
}
; *** IR Dump Before InstCombinePass on test_macs32_v2i16 ***
; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none)
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv4, %conv1
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv11, %conv7
  %add = add i32 %mul12, %acc
  %add13 = add i32 %add, %mul
  ret i32 %add13
}


INSTCOMBINE ITERATION #1 on test_macs32_v2i16
ADD:   ret i32 %add13
ADD:   %add13 = add i32 %add, %mul
ADD:   %add = add i32 %mul12, %acc
ADD:   %mul12 = mul nsw i32 %conv11, %conv7
ADD:   %conv11 = ashr i32 %y, 16
ADD:   %conv7 = ashr i32 %x, 16
ADD:   %mul = mul nsw i32 %conv4, %conv1
ADD:   %conv4 = ashr exact i32 %sext18, 16
ADD:   %sext18 = shl i32 %y, 16
ADD:   %conv1 = ashr exact i32 %sext, 16
ADD:   %sext = shl i32 %x, 16
IC: Visiting:   %sext = shl i32 %x, 16
IC: Visiting:   %conv1 = ashr exact i32 %sext, 16
IC: Visiting:   %sext18 = shl i32 %y, 16
IC: Visiting:   %conv4 = ashr exact i32 %sext18, 16
IC: Visiting:   %mul = mul nsw i32 %conv4, %conv1
IC: Visiting:   %conv7 = ashr i32 %x, 16
IC: Visiting:   %conv11 = ashr i32 %y, 16
IC: Visiting:   %mul12 = mul nsw i32 %conv11, %conv7
IC: Visiting:   %add = add i32 %mul12, %acc
IC: Visiting:   %add13 = add i32 %add, %mul
IC: Visiting:   ret i32 %add13
; *** IR Dump After InstCombinePass on test_macs32_v2i16 ***
; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none)
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv4, %conv1
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv11, %conv7
  %add = add i32 %mul12, %acc
  %add13 = add i32 %add, %mul
  ret i32 %add13
}
; *** IR Dump Before LoopUnrollPass on test_macs32_v2i16 ***
; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none)
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv4, %conv1
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv11, %conv7
  %add = add i32 %mul12, %acc
  %add13 = add i32 %add, %mul
  ret i32 %add13
}
; *** IR Dump After LoopUnrollPass on test_macs32_v2i16 ***
; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none)
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv4, %conv1
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv11, %conv7
  %add = add i32 %mul12, %acc
  %add13 = add i32 %add, %mul
  ret i32 %add13
}
; *** IR Dump Before WarnMissedTransformationsPass on test_macs32_v2i16 ***
; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none)
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv4, %conv1
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv11, %conv7
  %add = add i32 %mul12, %acc
  %add13 = add i32 %add, %mul
  ret i32 %add13
}
; *** IR Dump After WarnMissedTransformationsPass on test_macs32_v2i16 ***
; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none)
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv4, %conv1
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv11, %conv7
  %add = add i32 %mul12, %acc
  %add13 = add i32 %add, %mul
  ret i32 %add13
}
; *** IR Dump Before SROAPass on test_macs32_v2i16 ***
; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none)
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv4, %conv1
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv11, %conv7
  %add = add i32 %mul12, %acc
  %add13 = add i32 %add, %mul
  ret i32 %add13
}
SROA function: test_macs32_v2i16
; *** IR Dump After SROAPass on test_macs32_v2i16 ***
; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none)
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv4, %conv1
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv11, %conv7
  %add = add i32 %mul12, %acc
  %add13 = add i32 %add, %mul
  ret i32 %add13
}
; *** IR Dump Before InferAlignmentPass on test_macs32_v2i16 ***
; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none)
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv4, %conv1
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv11, %conv7
  %add = add i32 %mul12, %acc
  %add13 = add i32 %add, %mul
  ret i32 %add13
}
; *** IR Dump After InferAlignmentPass on test_macs32_v2i16 ***
; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none)
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv4, %conv1
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv11, %conv7
  %add = add i32 %mul12, %acc
  %add13 = add i32 %add, %mul
  ret i32 %add13
}
; *** IR Dump Before InstCombinePass on test_macs32_v2i16 ***
; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none)
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv4, %conv1
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv11, %conv7
  %add = add i32 %mul12, %acc
  %add13 = add i32 %add, %mul
  ret i32 %add13
}


INSTCOMBINE ITERATION #1 on test_macs32_v2i16
ADD:   ret i32 %add13
ADD:   %add13 = add i32 %add, %mul
ADD:   %add = add i32 %mul12, %acc
ADD:   %mul12 = mul nsw i32 %conv11, %conv7
ADD:   %conv11 = ashr i32 %y, 16
ADD:   %conv7 = ashr i32 %x, 16
ADD:   %mul = mul nsw i32 %conv4, %conv1
ADD:   %conv4 = ashr exact i32 %sext18, 16
ADD:   %sext18 = shl i32 %y, 16
ADD:   %conv1 = ashr exact i32 %sext, 16
ADD:   %sext = shl i32 %x, 16
IC: Visiting:   %sext = shl i32 %x, 16
IC: Visiting:   %conv1 = ashr exact i32 %sext, 16
IC: Visiting:   %sext18 = shl i32 %y, 16
IC: Visiting:   %conv4 = ashr exact i32 %sext18, 16
IC: Visiting:   %mul = mul nsw i32 %conv4, %conv1
IC: Visiting:   %conv7 = ashr i32 %x, 16
IC: Visiting:   %conv11 = ashr i32 %y, 16
IC: Visiting:   %mul12 = mul nsw i32 %conv11, %conv7
IC: Visiting:   %add = add i32 %mul12, %acc
IC: Visiting:   %add13 = add i32 %add, %mul
IC: Visiting:   ret i32 %add13
; *** IR Dump After InstCombinePass on test_macs32_v2i16 ***
; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none)
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv4, %conv1
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv11, %conv7
  %add = add i32 %mul12, %acc
  %add13 = add i32 %add, %mul
  ret i32 %add13
}
; *** IR Dump Before LoopSimplifyPass on test_macs32_v2i16 ***
; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none)
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv4, %conv1
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv11, %conv7
  %add = add i32 %mul12, %acc
  %add13 = add i32 %add, %mul
  ret i32 %add13
}
; *** IR Dump After LoopSimplifyPass on test_macs32_v2i16 ***
; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none)
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv4, %conv1
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv11, %conv7
  %add = add i32 %mul12, %acc
  %add13 = add i32 %add, %mul
  ret i32 %add13
}
; *** IR Dump Before LCSSAPass on test_macs32_v2i16 ***
; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none)
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv4, %conv1
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv11, %conv7
  %add = add i32 %mul12, %acc
  %add13 = add i32 %add, %mul
  ret i32 %add13
}
; *** IR Dump After LCSSAPass on test_macs32_v2i16 ***
; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none)
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv4, %conv1
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv11, %conv7
  %add = add i32 %mul12, %acc
  %add13 = add i32 %add, %mul
  ret i32 %add13
}
; *** IR Dump Before AlignmentFromAssumptionsPass on test_macs32_v2i16 ***
; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none)
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv4, %conv1
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv11, %conv7
  %add = add i32 %mul12, %acc
  %add13 = add i32 %add, %mul
  ret i32 %add13
}
; *** IR Dump After AlignmentFromAssumptionsPass on test_macs32_v2i16 ***
; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none)
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv4, %conv1
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv11, %conv7
  %add = add i32 %mul12, %acc
  %add13 = add i32 %add, %mul
  ret i32 %add13
}
; *** IR Dump Before LoopSinkPass on test_macs32_v2i16 ***
; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none)
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv4, %conv1
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv11, %conv7
  %add = add i32 %mul12, %acc
  %add13 = add i32 %add, %mul
  ret i32 %add13
}
; *** IR Dump After LoopSinkPass on test_macs32_v2i16 ***
; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none)
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv4, %conv1
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv11, %conv7
  %add = add i32 %mul12, %acc
  %add13 = add i32 %add, %mul
  ret i32 %add13
}
; *** IR Dump Before InstSimplifyPass on test_macs32_v2i16 ***
; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none)
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv4, %conv1
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv11, %conv7
  %add = add i32 %mul12, %acc
  %add13 = add i32 %add, %mul
  ret i32 %add13
}
; *** IR Dump After InstSimplifyPass on test_macs32_v2i16 ***
; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none)
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv4, %conv1
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv11, %conv7
  %add = add i32 %mul12, %acc
  %add13 = add i32 %add, %mul
  ret i32 %add13
}
; *** IR Dump Before DivRemPairsPass on test_macs32_v2i16 ***
; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none)
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv4, %conv1
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv11, %conv7
  %add = add i32 %mul12, %acc
  %add13 = add i32 %add, %mul
  ret i32 %add13
}
; *** IR Dump After DivRemPairsPass on test_macs32_v2i16 ***
; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none)
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv4, %conv1
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv11, %conv7
  %add = add i32 %mul12, %acc
  %add13 = add i32 %add, %mul
  ret i32 %add13
}
; *** IR Dump Before TailCallElimPass on test_macs32_v2i16 ***
; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none)
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv4, %conv1
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv11, %conv7
  %add = add i32 %mul12, %acc
  %add13 = add i32 %add, %mul
  ret i32 %add13
}
; *** IR Dump After TailCallElimPass on test_macs32_v2i16 ***
; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none)
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv4, %conv1
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv11, %conv7
  %add = add i32 %mul12, %acc
  %add13 = add i32 %add, %mul
  ret i32 %add13
}
; *** IR Dump Before SimplifyCFGPass on test_macs32_v2i16 ***
; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none)
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv4, %conv1
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv11, %conv7
  %add = add i32 %mul12, %acc
  %add13 = add i32 %add, %mul
  ret i32 %add13
}
; *** IR Dump After SimplifyCFGPass on test_macs32_v2i16 ***
; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none)
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv4, %conv1
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv11, %conv7
  %add = add i32 %mul12, %acc
  %add13 = add i32 %add, %mul
  ret i32 %add13
}
; *** IR Dump Before GlobalDCEPass on [module] ***
; ModuleID = 'cecil_test.c'
source_filename = "cecil_test.c"
target datalayout = "e-m:e-p:32:32-i64:64-n32-S128"
target triple = "riscv32-unknown-unknown"

; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none)
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv4, %conv1
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv11, %conv7
  %add = add i32 %mul12, %acc
  %add13 = add i32 %add, %mul
  ret i32 %add13
}

attributes #0 = { mustprogress nofree norecurse nosync nounwind willreturn memory(none) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="generic-rv32" "target-features"="+32bit,+m,+relax,+xseal5testalucvabs16,+xseal5testalucvabs32,+xseal5testalucvabs8,+xseal5testalucvaddnrsi16,+xseal5testalucvaddnrsi32,+xseal5testalucvaddnrui16,+xseal5testalucvaddnrui32,+xseal5testalucvaddns,+xseal5testalucvaddnu,+xseal5testalucvaddrnrsi16,+xseal5testalucvaddrnrsi32,+xseal5testalucvaddrnrui16,+xseal5testalucvaddrnrui32,+xseal5testalucvaddrns,+xseal5testalucvaddrnu,+xseal5testalucvextbs,+xseal5testalucvextbz,+xseal5testalucvexths,+xseal5testalucvexthz,+xseal5testalucvmaxi1216,+xseal5testalucvmaxi1232,+xseal5testalucvmaxi516,+xseal5testalucvmaxi532,+xseal5testalucvmaxs16,+xseal5testalucvmaxs32,+xseal5testalucvmaxs8,+xseal5testalucvmaxu16,+xseal5testalucvmaxu32,+xseal5testalucvmaxu8,+xseal5testalucvmini1216,+xseal5testalucvmini1232,+xseal5testalucvmini516,+xseal5testalucvmini532,+xseal5testalucvmins16,+xseal5testalucvmins32,+xseal5testalucvmins8,+xseal5testalucvminu16,+xseal5testalucvminu32,+xseal5testalucvminu8,+xseal5testalucvsletsi16,+xseal5testalucvsletsi32,+xseal5testalucvsletui16,+xseal5testalucvsletui32,+xseal5testalucvsubnrsi16,+xseal5testalucvsubnrsi32,+xseal5testalucvsubnrui16,+xseal5testalucvsubnrui32,+xseal5testalucvsubns,+xseal5testalucvsubnu,+xseal5testalucvsubrnrsi16,+xseal5testalucvsubrnrsi32,+xseal5testalucvsubrnrui16,+xseal5testalucvsubrnrui32,+xseal5testalucvsubrns,+xseal5testalucvsubrnu,+xseal5testmaccvmachhns,+xseal5testmaccvmachhnu,+xseal5testmaccvmachhrns,+xseal5testmaccvmachhrnu,+xseal5testmaccvmacns,+xseal5testmaccvmacnu,+xseal5testmaccvmacrns,+xseal5testmaccvmacrnu,+xseal5testmaccvmacsi16,+xseal5testmaccvmacsi32,+xseal5testmaccvmacui16,+xseal5testmaccvmacui32,+xseal5testmaccvmsusi16,+xseal5testmaccvmsusi32,+xseal5testmaccvmsuui16,+xseal5testmaccvmsuui32,+xseal5testmaccvmulhhns,+xseal5testmaccvmulhhnu,+xseal5testmaccvmulhhrns,+xseal5testmaccvmulhhrnu,+xseal5testmaccvmulns,+xseal5testmaccvmulnu,+xseal5testmaccvmulrns,+xseal5testmaccvmulrnu,-a,-c,-d,-e,-experimental-zacas,-experimental-zcmop,-experimental-zfbfmin,-experimental-zicfilp,-experimental-zicfiss,-experimental-zimop,-experimental-ztso,-experimental-zvfbfmin,-experimental-zvfbfwma,-f,-h,-smaia,-smepmp,-ssaia,-svinval,-svnapot,-svpbmt,-v,-xcvalu,-xcvbi,-xcvbitmanip,-xcvelw,-xcvmac,-xcvmem,-xcvsimd,-xsfvcp,-xsfvfnrclipxfqf,-xsfvfwmaccqqq,-xsfvqmaccdod,-xsfvqmaccqoq,-xtheadba,-xtheadbb,-xtheadbs,-xtheadcmo,-xtheadcondmov,-xtheadfmemidx,-xtheadmac,-xtheadmemidx,-xtheadmempair,-xtheadsync,-xtheadvdot,-xventanacondops,-za128rs,-za64rs,-zawrs,-zba,-zbb,-zbc,-zbkb,-zbkc,-zbkx,-zbs,-zca,-zcb,-zcd,-zce,-zcf,-zcmp,-zcmt,-zdinx,-zfa,-zfh,-zfhmin,-zfinx,-zhinx,-zhinxmin,-zic64b,-zicbom,-zicbop,-zicboz,-ziccamoa,-ziccif,-zicclsm,-ziccrse,-zicntr,-zicond,-zicsr,-zifencei,-zihintntl,-zihintpause,-zihpm,-zk,-zkn,-zknd,-zkne,-zknh,-zkr,-zks,-zksed,-zksh,-zkt,-zmmul,-zvbb,-zvbc,-zve32f,-zve32x,-zve64d,-zve64f,-zve64x,-zvfh,-zvfhmin,-zvkb,-zvkg,-zvkn,-zvknc,-zvkned,-zvkng,-zvknha,-zvknhb,-zvks,-zvksc,-zvksed,-zvksg,-zvksh,-zvkt,-zvl1024b,-zvl128b,-zvl16384b,-zvl2048b,-zvl256b,-zvl32768b,-zvl32b,-zvl4096b,-zvl512b,-zvl64b,-zvl65536b,-zvl8192b" }

!llvm.module.flags = !{!0, !1, !2}
!llvm.ident = !{!3}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 1, !"target-abi", !"ilp32"}
!2 = !{i32 8, !"SmallDataLimit", i32 8}
!3 = !{!"clang version 18.1.0rc (https://github.com/llvm/llvm-project.git 1acc4e456481e76822c76c850bad3994d4e04b59)"}
; *** IR Dump After GlobalDCEPass on [module] ***
; ModuleID = 'cecil_test.c'
source_filename = "cecil_test.c"
target datalayout = "e-m:e-p:32:32-i64:64-n32-S128"
target triple = "riscv32-unknown-unknown"

; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none)
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv4, %conv1
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv11, %conv7
  %add = add i32 %mul12, %acc
  %add13 = add i32 %add, %mul
  ret i32 %add13
}

attributes #0 = { mustprogress nofree norecurse nosync nounwind willreturn memory(none) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="generic-rv32" "target-features"="+32bit,+m,+relax,+xseal5testalucvabs16,+xseal5testalucvabs32,+xseal5testalucvabs8,+xseal5testalucvaddnrsi16,+xseal5testalucvaddnrsi32,+xseal5testalucvaddnrui16,+xseal5testalucvaddnrui32,+xseal5testalucvaddns,+xseal5testalucvaddnu,+xseal5testalucvaddrnrsi16,+xseal5testalucvaddrnrsi32,+xseal5testalucvaddrnrui16,+xseal5testalucvaddrnrui32,+xseal5testalucvaddrns,+xseal5testalucvaddrnu,+xseal5testalucvextbs,+xseal5testalucvextbz,+xseal5testalucvexths,+xseal5testalucvexthz,+xseal5testalucvmaxi1216,+xseal5testalucvmaxi1232,+xseal5testalucvmaxi516,+xseal5testalucvmaxi532,+xseal5testalucvmaxs16,+xseal5testalucvmaxs32,+xseal5testalucvmaxs8,+xseal5testalucvmaxu16,+xseal5testalucvmaxu32,+xseal5testalucvmaxu8,+xseal5testalucvmini1216,+xseal5testalucvmini1232,+xseal5testalucvmini516,+xseal5testalucvmini532,+xseal5testalucvmins16,+xseal5testalucvmins32,+xseal5testalucvmins8,+xseal5testalucvminu16,+xseal5testalucvminu32,+xseal5testalucvminu8,+xseal5testalucvsletsi16,+xseal5testalucvsletsi32,+xseal5testalucvsletui16,+xseal5testalucvsletui32,+xseal5testalucvsubnrsi16,+xseal5testalucvsubnrsi32,+xseal5testalucvsubnrui16,+xseal5testalucvsubnrui32,+xseal5testalucvsubns,+xseal5testalucvsubnu,+xseal5testalucvsubrnrsi16,+xseal5testalucvsubrnrsi32,+xseal5testalucvsubrnrui16,+xseal5testalucvsubrnrui32,+xseal5testalucvsubrns,+xseal5testalucvsubrnu,+xseal5testmaccvmachhns,+xseal5testmaccvmachhnu,+xseal5testmaccvmachhrns,+xseal5testmaccvmachhrnu,+xseal5testmaccvmacns,+xseal5testmaccvmacnu,+xseal5testmaccvmacrns,+xseal5testmaccvmacrnu,+xseal5testmaccvmacsi16,+xseal5testmaccvmacsi32,+xseal5testmaccvmacui16,+xseal5testmaccvmacui32,+xseal5testmaccvmsusi16,+xseal5testmaccvmsusi32,+xseal5testmaccvmsuui16,+xseal5testmaccvmsuui32,+xseal5testmaccvmulhhns,+xseal5testmaccvmulhhnu,+xseal5testmaccvmulhhrns,+xseal5testmaccvmulhhrnu,+xseal5testmaccvmulns,+xseal5testmaccvmulnu,+xseal5testmaccvmulrns,+xseal5testmaccvmulrnu,-a,-c,-d,-e,-experimental-zacas,-experimental-zcmop,-experimental-zfbfmin,-experimental-zicfilp,-experimental-zicfiss,-experimental-zimop,-experimental-ztso,-experimental-zvfbfmin,-experimental-zvfbfwma,-f,-h,-smaia,-smepmp,-ssaia,-svinval,-svnapot,-svpbmt,-v,-xcvalu,-xcvbi,-xcvbitmanip,-xcvelw,-xcvmac,-xcvmem,-xcvsimd,-xsfvcp,-xsfvfnrclipxfqf,-xsfvfwmaccqqq,-xsfvqmaccdod,-xsfvqmaccqoq,-xtheadba,-xtheadbb,-xtheadbs,-xtheadcmo,-xtheadcondmov,-xtheadfmemidx,-xtheadmac,-xtheadmemidx,-xtheadmempair,-xtheadsync,-xtheadvdot,-xventanacondops,-za128rs,-za64rs,-zawrs,-zba,-zbb,-zbc,-zbkb,-zbkc,-zbkx,-zbs,-zca,-zcb,-zcd,-zce,-zcf,-zcmp,-zcmt,-zdinx,-zfa,-zfh,-zfhmin,-zfinx,-zhinx,-zhinxmin,-zic64b,-zicbom,-zicbop,-zicboz,-ziccamoa,-ziccif,-zicclsm,-ziccrse,-zicntr,-zicond,-zicsr,-zifencei,-zihintntl,-zihintpause,-zihpm,-zk,-zkn,-zknd,-zkne,-zknh,-zkr,-zks,-zksed,-zksh,-zkt,-zmmul,-zvbb,-zvbc,-zve32f,-zve32x,-zve64d,-zve64f,-zve64x,-zvfh,-zvfhmin,-zvkb,-zvkg,-zvkn,-zvknc,-zvkned,-zvkng,-zvknha,-zvknhb,-zvks,-zvksc,-zvksed,-zvksg,-zvksh,-zvkt,-zvl1024b,-zvl128b,-zvl16384b,-zvl2048b,-zvl256b,-zvl32768b,-zvl32b,-zvl4096b,-zvl512b,-zvl64b,-zvl65536b,-zvl8192b" }

!llvm.module.flags = !{!0, !1, !2}
!llvm.ident = !{!3}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 1, !"target-abi", !"ilp32"}
!2 = !{i32 8, !"SmallDataLimit", i32 8}
!3 = !{!"clang version 18.1.0rc (https://github.com/llvm/llvm-project.git 1acc4e456481e76822c76c850bad3994d4e04b59)"}
; *** IR Dump Before ConstantMergePass on [module] ***
; ModuleID = 'cecil_test.c'
source_filename = "cecil_test.c"
target datalayout = "e-m:e-p:32:32-i64:64-n32-S128"
target triple = "riscv32-unknown-unknown"

; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none)
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv4, %conv1
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv11, %conv7
  %add = add i32 %mul12, %acc
  %add13 = add i32 %add, %mul
  ret i32 %add13
}

attributes #0 = { mustprogress nofree norecurse nosync nounwind willreturn memory(none) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="generic-rv32" "target-features"="+32bit,+m,+relax,+xseal5testalucvabs16,+xseal5testalucvabs32,+xseal5testalucvabs8,+xseal5testalucvaddnrsi16,+xseal5testalucvaddnrsi32,+xseal5testalucvaddnrui16,+xseal5testalucvaddnrui32,+xseal5testalucvaddns,+xseal5testalucvaddnu,+xseal5testalucvaddrnrsi16,+xseal5testalucvaddrnrsi32,+xseal5testalucvaddrnrui16,+xseal5testalucvaddrnrui32,+xseal5testalucvaddrns,+xseal5testalucvaddrnu,+xseal5testalucvextbs,+xseal5testalucvextbz,+xseal5testalucvexths,+xseal5testalucvexthz,+xseal5testalucvmaxi1216,+xseal5testalucvmaxi1232,+xseal5testalucvmaxi516,+xseal5testalucvmaxi532,+xseal5testalucvmaxs16,+xseal5testalucvmaxs32,+xseal5testalucvmaxs8,+xseal5testalucvmaxu16,+xseal5testalucvmaxu32,+xseal5testalucvmaxu8,+xseal5testalucvmini1216,+xseal5testalucvmini1232,+xseal5testalucvmini516,+xseal5testalucvmini532,+xseal5testalucvmins16,+xseal5testalucvmins32,+xseal5testalucvmins8,+xseal5testalucvminu16,+xseal5testalucvminu32,+xseal5testalucvminu8,+xseal5testalucvsletsi16,+xseal5testalucvsletsi32,+xseal5testalucvsletui16,+xseal5testalucvsletui32,+xseal5testalucvsubnrsi16,+xseal5testalucvsubnrsi32,+xseal5testalucvsubnrui16,+xseal5testalucvsubnrui32,+xseal5testalucvsubns,+xseal5testalucvsubnu,+xseal5testalucvsubrnrsi16,+xseal5testalucvsubrnrsi32,+xseal5testalucvsubrnrui16,+xseal5testalucvsubrnrui32,+xseal5testalucvsubrns,+xseal5testalucvsubrnu,+xseal5testmaccvmachhns,+xseal5testmaccvmachhnu,+xseal5testmaccvmachhrns,+xseal5testmaccvmachhrnu,+xseal5testmaccvmacns,+xseal5testmaccvmacnu,+xseal5testmaccvmacrns,+xseal5testmaccvmacrnu,+xseal5testmaccvmacsi16,+xseal5testmaccvmacsi32,+xseal5testmaccvmacui16,+xseal5testmaccvmacui32,+xseal5testmaccvmsusi16,+xseal5testmaccvmsusi32,+xseal5testmaccvmsuui16,+xseal5testmaccvmsuui32,+xseal5testmaccvmulhhns,+xseal5testmaccvmulhhnu,+xseal5testmaccvmulhhrns,+xseal5testmaccvmulhhrnu,+xseal5testmaccvmulns,+xseal5testmaccvmulnu,+xseal5testmaccvmulrns,+xseal5testmaccvmulrnu,-a,-c,-d,-e,-experimental-zacas,-experimental-zcmop,-experimental-zfbfmin,-experimental-zicfilp,-experimental-zicfiss,-experimental-zimop,-experimental-ztso,-experimental-zvfbfmin,-experimental-zvfbfwma,-f,-h,-smaia,-smepmp,-ssaia,-svinval,-svnapot,-svpbmt,-v,-xcvalu,-xcvbi,-xcvbitmanip,-xcvelw,-xcvmac,-xcvmem,-xcvsimd,-xsfvcp,-xsfvfnrclipxfqf,-xsfvfwmaccqqq,-xsfvqmaccdod,-xsfvqmaccqoq,-xtheadba,-xtheadbb,-xtheadbs,-xtheadcmo,-xtheadcondmov,-xtheadfmemidx,-xtheadmac,-xtheadmemidx,-xtheadmempair,-xtheadsync,-xtheadvdot,-xventanacondops,-za128rs,-za64rs,-zawrs,-zba,-zbb,-zbc,-zbkb,-zbkc,-zbkx,-zbs,-zca,-zcb,-zcd,-zce,-zcf,-zcmp,-zcmt,-zdinx,-zfa,-zfh,-zfhmin,-zfinx,-zhinx,-zhinxmin,-zic64b,-zicbom,-zicbop,-zicboz,-ziccamoa,-ziccif,-zicclsm,-ziccrse,-zicntr,-zicond,-zicsr,-zifencei,-zihintntl,-zihintpause,-zihpm,-zk,-zkn,-zknd,-zkne,-zknh,-zkr,-zks,-zksed,-zksh,-zkt,-zmmul,-zvbb,-zvbc,-zve32f,-zve32x,-zve64d,-zve64f,-zve64x,-zvfh,-zvfhmin,-zvkb,-zvkg,-zvkn,-zvknc,-zvkned,-zvkng,-zvknha,-zvknhb,-zvks,-zvksc,-zvksed,-zvksg,-zvksh,-zvkt,-zvl1024b,-zvl128b,-zvl16384b,-zvl2048b,-zvl256b,-zvl32768b,-zvl32b,-zvl4096b,-zvl512b,-zvl64b,-zvl65536b,-zvl8192b" }

!llvm.module.flags = !{!0, !1, !2}
!llvm.ident = !{!3}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 1, !"target-abi", !"ilp32"}
!2 = !{i32 8, !"SmallDataLimit", i32 8}
!3 = !{!"clang version 18.1.0rc (https://github.com/llvm/llvm-project.git 1acc4e456481e76822c76c850bad3994d4e04b59)"}
; *** IR Dump After ConstantMergePass on [module] ***
; ModuleID = 'cecil_test.c'
source_filename = "cecil_test.c"
target datalayout = "e-m:e-p:32:32-i64:64-n32-S128"
target triple = "riscv32-unknown-unknown"

; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none)
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv4, %conv1
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv11, %conv7
  %add = add i32 %mul12, %acc
  %add13 = add i32 %add, %mul
  ret i32 %add13
}

attributes #0 = { mustprogress nofree norecurse nosync nounwind willreturn memory(none) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="generic-rv32" "target-features"="+32bit,+m,+relax,+xseal5testalucvabs16,+xseal5testalucvabs32,+xseal5testalucvabs8,+xseal5testalucvaddnrsi16,+xseal5testalucvaddnrsi32,+xseal5testalucvaddnrui16,+xseal5testalucvaddnrui32,+xseal5testalucvaddns,+xseal5testalucvaddnu,+xseal5testalucvaddrnrsi16,+xseal5testalucvaddrnrsi32,+xseal5testalucvaddrnrui16,+xseal5testalucvaddrnrui32,+xseal5testalucvaddrns,+xseal5testalucvaddrnu,+xseal5testalucvextbs,+xseal5testalucvextbz,+xseal5testalucvexths,+xseal5testalucvexthz,+xseal5testalucvmaxi1216,+xseal5testalucvmaxi1232,+xseal5testalucvmaxi516,+xseal5testalucvmaxi532,+xseal5testalucvmaxs16,+xseal5testalucvmaxs32,+xseal5testalucvmaxs8,+xseal5testalucvmaxu16,+xseal5testalucvmaxu32,+xseal5testalucvmaxu8,+xseal5testalucvmini1216,+xseal5testalucvmini1232,+xseal5testalucvmini516,+xseal5testalucvmini532,+xseal5testalucvmins16,+xseal5testalucvmins32,+xseal5testalucvmins8,+xseal5testalucvminu16,+xseal5testalucvminu32,+xseal5testalucvminu8,+xseal5testalucvsletsi16,+xseal5testalucvsletsi32,+xseal5testalucvsletui16,+xseal5testalucvsletui32,+xseal5testalucvsubnrsi16,+xseal5testalucvsubnrsi32,+xseal5testalucvsubnrui16,+xseal5testalucvsubnrui32,+xseal5testalucvsubns,+xseal5testalucvsubnu,+xseal5testalucvsubrnrsi16,+xseal5testalucvsubrnrsi32,+xseal5testalucvsubrnrui16,+xseal5testalucvsubrnrui32,+xseal5testalucvsubrns,+xseal5testalucvsubrnu,+xseal5testmaccvmachhns,+xseal5testmaccvmachhnu,+xseal5testmaccvmachhrns,+xseal5testmaccvmachhrnu,+xseal5testmaccvmacns,+xseal5testmaccvmacnu,+xseal5testmaccvmacrns,+xseal5testmaccvmacrnu,+xseal5testmaccvmacsi16,+xseal5testmaccvmacsi32,+xseal5testmaccvmacui16,+xseal5testmaccvmacui32,+xseal5testmaccvmsusi16,+xseal5testmaccvmsusi32,+xseal5testmaccvmsuui16,+xseal5testmaccvmsuui32,+xseal5testmaccvmulhhns,+xseal5testmaccvmulhhnu,+xseal5testmaccvmulhhrns,+xseal5testmaccvmulhhrnu,+xseal5testmaccvmulns,+xseal5testmaccvmulnu,+xseal5testmaccvmulrns,+xseal5testmaccvmulrnu,-a,-c,-d,-e,-experimental-zacas,-experimental-zcmop,-experimental-zfbfmin,-experimental-zicfilp,-experimental-zicfiss,-experimental-zimop,-experimental-ztso,-experimental-zvfbfmin,-experimental-zvfbfwma,-f,-h,-smaia,-smepmp,-ssaia,-svinval,-svnapot,-svpbmt,-v,-xcvalu,-xcvbi,-xcvbitmanip,-xcvelw,-xcvmac,-xcvmem,-xcvsimd,-xsfvcp,-xsfvfnrclipxfqf,-xsfvfwmaccqqq,-xsfvqmaccdod,-xsfvqmaccqoq,-xtheadba,-xtheadbb,-xtheadbs,-xtheadcmo,-xtheadcondmov,-xtheadfmemidx,-xtheadmac,-xtheadmemidx,-xtheadmempair,-xtheadsync,-xtheadvdot,-xventanacondops,-za128rs,-za64rs,-zawrs,-zba,-zbb,-zbc,-zbkb,-zbkc,-zbkx,-zbs,-zca,-zcb,-zcd,-zce,-zcf,-zcmp,-zcmt,-zdinx,-zfa,-zfh,-zfhmin,-zfinx,-zhinx,-zhinxmin,-zic64b,-zicbom,-zicbop,-zicboz,-ziccamoa,-ziccif,-zicclsm,-ziccrse,-zicntr,-zicond,-zicsr,-zifencei,-zihintntl,-zihintpause,-zihpm,-zk,-zkn,-zknd,-zkne,-zknh,-zkr,-zks,-zksed,-zksh,-zkt,-zmmul,-zvbb,-zvbc,-zve32f,-zve32x,-zve64d,-zve64f,-zve64x,-zvfh,-zvfhmin,-zvkb,-zvkg,-zvkn,-zvknc,-zvkned,-zvkng,-zvknha,-zvknhb,-zvks,-zvksc,-zvksed,-zvksg,-zvksh,-zvkt,-zvl1024b,-zvl128b,-zvl16384b,-zvl2048b,-zvl256b,-zvl32768b,-zvl32b,-zvl4096b,-zvl512b,-zvl64b,-zvl65536b,-zvl8192b" }

!llvm.module.flags = !{!0, !1, !2}
!llvm.ident = !{!3}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 1, !"target-abi", !"ilp32"}
!2 = !{i32 8, !"SmallDataLimit", i32 8}
!3 = !{!"clang version 18.1.0rc (https://github.com/llvm/llvm-project.git 1acc4e456481e76822c76c850bad3994d4e04b59)"}
; *** IR Dump Before CGProfilePass on [module] ***
; ModuleID = 'cecil_test.c'
source_filename = "cecil_test.c"
target datalayout = "e-m:e-p:32:32-i64:64-n32-S128"
target triple = "riscv32-unknown-unknown"

; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none)
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv4, %conv1
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv11, %conv7
  %add = add i32 %mul12, %acc
  %add13 = add i32 %add, %mul
  ret i32 %add13
}

attributes #0 = { mustprogress nofree norecurse nosync nounwind willreturn memory(none) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="generic-rv32" "target-features"="+32bit,+m,+relax,+xseal5testalucvabs16,+xseal5testalucvabs32,+xseal5testalucvabs8,+xseal5testalucvaddnrsi16,+xseal5testalucvaddnrsi32,+xseal5testalucvaddnrui16,+xseal5testalucvaddnrui32,+xseal5testalucvaddns,+xseal5testalucvaddnu,+xseal5testalucvaddrnrsi16,+xseal5testalucvaddrnrsi32,+xseal5testalucvaddrnrui16,+xseal5testalucvaddrnrui32,+xseal5testalucvaddrns,+xseal5testalucvaddrnu,+xseal5testalucvextbs,+xseal5testalucvextbz,+xseal5testalucvexths,+xseal5testalucvexthz,+xseal5testalucvmaxi1216,+xseal5testalucvmaxi1232,+xseal5testalucvmaxi516,+xseal5testalucvmaxi532,+xseal5testalucvmaxs16,+xseal5testalucvmaxs32,+xseal5testalucvmaxs8,+xseal5testalucvmaxu16,+xseal5testalucvmaxu32,+xseal5testalucvmaxu8,+xseal5testalucvmini1216,+xseal5testalucvmini1232,+xseal5testalucvmini516,+xseal5testalucvmini532,+xseal5testalucvmins16,+xseal5testalucvmins32,+xseal5testalucvmins8,+xseal5testalucvminu16,+xseal5testalucvminu32,+xseal5testalucvminu8,+xseal5testalucvsletsi16,+xseal5testalucvsletsi32,+xseal5testalucvsletui16,+xseal5testalucvsletui32,+xseal5testalucvsubnrsi16,+xseal5testalucvsubnrsi32,+xseal5testalucvsubnrui16,+xseal5testalucvsubnrui32,+xseal5testalucvsubns,+xseal5testalucvsubnu,+xseal5testalucvsubrnrsi16,+xseal5testalucvsubrnrsi32,+xseal5testalucvsubrnrui16,+xseal5testalucvsubrnrui32,+xseal5testalucvsubrns,+xseal5testalucvsubrnu,+xseal5testmaccvmachhns,+xseal5testmaccvmachhnu,+xseal5testmaccvmachhrns,+xseal5testmaccvmachhrnu,+xseal5testmaccvmacns,+xseal5testmaccvmacnu,+xseal5testmaccvmacrns,+xseal5testmaccvmacrnu,+xseal5testmaccvmacsi16,+xseal5testmaccvmacsi32,+xseal5testmaccvmacui16,+xseal5testmaccvmacui32,+xseal5testmaccvmsusi16,+xseal5testmaccvmsusi32,+xseal5testmaccvmsuui16,+xseal5testmaccvmsuui32,+xseal5testmaccvmulhhns,+xseal5testmaccvmulhhnu,+xseal5testmaccvmulhhrns,+xseal5testmaccvmulhhrnu,+xseal5testmaccvmulns,+xseal5testmaccvmulnu,+xseal5testmaccvmulrns,+xseal5testmaccvmulrnu,-a,-c,-d,-e,-experimental-zacas,-experimental-zcmop,-experimental-zfbfmin,-experimental-zicfilp,-experimental-zicfiss,-experimental-zimop,-experimental-ztso,-experimental-zvfbfmin,-experimental-zvfbfwma,-f,-h,-smaia,-smepmp,-ssaia,-svinval,-svnapot,-svpbmt,-v,-xcvalu,-xcvbi,-xcvbitmanip,-xcvelw,-xcvmac,-xcvmem,-xcvsimd,-xsfvcp,-xsfvfnrclipxfqf,-xsfvfwmaccqqq,-xsfvqmaccdod,-xsfvqmaccqoq,-xtheadba,-xtheadbb,-xtheadbs,-xtheadcmo,-xtheadcondmov,-xtheadfmemidx,-xtheadmac,-xtheadmemidx,-xtheadmempair,-xtheadsync,-xtheadvdot,-xventanacondops,-za128rs,-za64rs,-zawrs,-zba,-zbb,-zbc,-zbkb,-zbkc,-zbkx,-zbs,-zca,-zcb,-zcd,-zce,-zcf,-zcmp,-zcmt,-zdinx,-zfa,-zfh,-zfhmin,-zfinx,-zhinx,-zhinxmin,-zic64b,-zicbom,-zicbop,-zicboz,-ziccamoa,-ziccif,-zicclsm,-ziccrse,-zicntr,-zicond,-zicsr,-zifencei,-zihintntl,-zihintpause,-zihpm,-zk,-zkn,-zknd,-zkne,-zknh,-zkr,-zks,-zksed,-zksh,-zkt,-zmmul,-zvbb,-zvbc,-zve32f,-zve32x,-zve64d,-zve64f,-zve64x,-zvfh,-zvfhmin,-zvkb,-zvkg,-zvkn,-zvknc,-zvkned,-zvkng,-zvknha,-zvknhb,-zvks,-zvksc,-zvksed,-zvksg,-zvksh,-zvkt,-zvl1024b,-zvl128b,-zvl16384b,-zvl2048b,-zvl256b,-zvl32768b,-zvl32b,-zvl4096b,-zvl512b,-zvl64b,-zvl65536b,-zvl8192b" }

!llvm.module.flags = !{!0, !1, !2}
!llvm.ident = !{!3}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 1, !"target-abi", !"ilp32"}
!2 = !{i32 8, !"SmallDataLimit", i32 8}
!3 = !{!"clang version 18.1.0rc (https://github.com/llvm/llvm-project.git 1acc4e456481e76822c76c850bad3994d4e04b59)"}
; *** IR Dump After CGProfilePass on [module] ***
; ModuleID = 'cecil_test.c'
source_filename = "cecil_test.c"
target datalayout = "e-m:e-p:32:32-i64:64-n32-S128"
target triple = "riscv32-unknown-unknown"

; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none)
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv4, %conv1
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv11, %conv7
  %add = add i32 %mul12, %acc
  %add13 = add i32 %add, %mul
  ret i32 %add13
}

attributes #0 = { mustprogress nofree norecurse nosync nounwind willreturn memory(none) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="generic-rv32" "target-features"="+32bit,+m,+relax,+xseal5testalucvabs16,+xseal5testalucvabs32,+xseal5testalucvabs8,+xseal5testalucvaddnrsi16,+xseal5testalucvaddnrsi32,+xseal5testalucvaddnrui16,+xseal5testalucvaddnrui32,+xseal5testalucvaddns,+xseal5testalucvaddnu,+xseal5testalucvaddrnrsi16,+xseal5testalucvaddrnrsi32,+xseal5testalucvaddrnrui16,+xseal5testalucvaddrnrui32,+xseal5testalucvaddrns,+xseal5testalucvaddrnu,+xseal5testalucvextbs,+xseal5testalucvextbz,+xseal5testalucvexths,+xseal5testalucvexthz,+xseal5testalucvmaxi1216,+xseal5testalucvmaxi1232,+xseal5testalucvmaxi516,+xseal5testalucvmaxi532,+xseal5testalucvmaxs16,+xseal5testalucvmaxs32,+xseal5testalucvmaxs8,+xseal5testalucvmaxu16,+xseal5testalucvmaxu32,+xseal5testalucvmaxu8,+xseal5testalucvmini1216,+xseal5testalucvmini1232,+xseal5testalucvmini516,+xseal5testalucvmini532,+xseal5testalucvmins16,+xseal5testalucvmins32,+xseal5testalucvmins8,+xseal5testalucvminu16,+xseal5testalucvminu32,+xseal5testalucvminu8,+xseal5testalucvsletsi16,+xseal5testalucvsletsi32,+xseal5testalucvsletui16,+xseal5testalucvsletui32,+xseal5testalucvsubnrsi16,+xseal5testalucvsubnrsi32,+xseal5testalucvsubnrui16,+xseal5testalucvsubnrui32,+xseal5testalucvsubns,+xseal5testalucvsubnu,+xseal5testalucvsubrnrsi16,+xseal5testalucvsubrnrsi32,+xseal5testalucvsubrnrui16,+xseal5testalucvsubrnrui32,+xseal5testalucvsubrns,+xseal5testalucvsubrnu,+xseal5testmaccvmachhns,+xseal5testmaccvmachhnu,+xseal5testmaccvmachhrns,+xseal5testmaccvmachhrnu,+xseal5testmaccvmacns,+xseal5testmaccvmacnu,+xseal5testmaccvmacrns,+xseal5testmaccvmacrnu,+xseal5testmaccvmacsi16,+xseal5testmaccvmacsi32,+xseal5testmaccvmacui16,+xseal5testmaccvmacui32,+xseal5testmaccvmsusi16,+xseal5testmaccvmsusi32,+xseal5testmaccvmsuui16,+xseal5testmaccvmsuui32,+xseal5testmaccvmulhhns,+xseal5testmaccvmulhhnu,+xseal5testmaccvmulhhrns,+xseal5testmaccvmulhhrnu,+xseal5testmaccvmulns,+xseal5testmaccvmulnu,+xseal5testmaccvmulrns,+xseal5testmaccvmulrnu,-a,-c,-d,-e,-experimental-zacas,-experimental-zcmop,-experimental-zfbfmin,-experimental-zicfilp,-experimental-zicfiss,-experimental-zimop,-experimental-ztso,-experimental-zvfbfmin,-experimental-zvfbfwma,-f,-h,-smaia,-smepmp,-ssaia,-svinval,-svnapot,-svpbmt,-v,-xcvalu,-xcvbi,-xcvbitmanip,-xcvelw,-xcvmac,-xcvmem,-xcvsimd,-xsfvcp,-xsfvfnrclipxfqf,-xsfvfwmaccqqq,-xsfvqmaccdod,-xsfvqmaccqoq,-xtheadba,-xtheadbb,-xtheadbs,-xtheadcmo,-xtheadcondmov,-xtheadfmemidx,-xtheadmac,-xtheadmemidx,-xtheadmempair,-xtheadsync,-xtheadvdot,-xventanacondops,-za128rs,-za64rs,-zawrs,-zba,-zbb,-zbc,-zbkb,-zbkc,-zbkx,-zbs,-zca,-zcb,-zcd,-zce,-zcf,-zcmp,-zcmt,-zdinx,-zfa,-zfh,-zfhmin,-zfinx,-zhinx,-zhinxmin,-zic64b,-zicbom,-zicbop,-zicboz,-ziccamoa,-ziccif,-zicclsm,-ziccrse,-zicntr,-zicond,-zicsr,-zifencei,-zihintntl,-zihintpause,-zihpm,-zk,-zkn,-zknd,-zkne,-zknh,-zkr,-zks,-zksed,-zksh,-zkt,-zmmul,-zvbb,-zvbc,-zve32f,-zve32x,-zve64d,-zve64f,-zve64x,-zvfh,-zvfhmin,-zvkb,-zvkg,-zvkn,-zvknc,-zvkned,-zvkng,-zvknha,-zvknhb,-zvks,-zvksc,-zvksed,-zvksg,-zvksh,-zvkt,-zvl1024b,-zvl128b,-zvl16384b,-zvl2048b,-zvl256b,-zvl32768b,-zvl32b,-zvl4096b,-zvl512b,-zvl64b,-zvl65536b,-zvl8192b" }

!llvm.module.flags = !{!0, !1, !2}
!llvm.ident = !{!3}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 1, !"target-abi", !"ilp32"}
!2 = !{i32 8, !"SmallDataLimit", i32 8}
!3 = !{!"clang version 18.1.0rc (https://github.com/llvm/llvm-project.git 1acc4e456481e76822c76c850bad3994d4e04b59)"}
; *** IR Dump Before RelLookupTableConverterPass on [module] ***
; ModuleID = 'cecil_test.c'
source_filename = "cecil_test.c"
target datalayout = "e-m:e-p:32:32-i64:64-n32-S128"
target triple = "riscv32-unknown-unknown"

; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none)
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv4, %conv1
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv11, %conv7
  %add = add i32 %mul12, %acc
  %add13 = add i32 %add, %mul
  ret i32 %add13
}

attributes #0 = { mustprogress nofree norecurse nosync nounwind willreturn memory(none) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="generic-rv32" "target-features"="+32bit,+m,+relax,+xseal5testalucvabs16,+xseal5testalucvabs32,+xseal5testalucvabs8,+xseal5testalucvaddnrsi16,+xseal5testalucvaddnrsi32,+xseal5testalucvaddnrui16,+xseal5testalucvaddnrui32,+xseal5testalucvaddns,+xseal5testalucvaddnu,+xseal5testalucvaddrnrsi16,+xseal5testalucvaddrnrsi32,+xseal5testalucvaddrnrui16,+xseal5testalucvaddrnrui32,+xseal5testalucvaddrns,+xseal5testalucvaddrnu,+xseal5testalucvextbs,+xseal5testalucvextbz,+xseal5testalucvexths,+xseal5testalucvexthz,+xseal5testalucvmaxi1216,+xseal5testalucvmaxi1232,+xseal5testalucvmaxi516,+xseal5testalucvmaxi532,+xseal5testalucvmaxs16,+xseal5testalucvmaxs32,+xseal5testalucvmaxs8,+xseal5testalucvmaxu16,+xseal5testalucvmaxu32,+xseal5testalucvmaxu8,+xseal5testalucvmini1216,+xseal5testalucvmini1232,+xseal5testalucvmini516,+xseal5testalucvmini532,+xseal5testalucvmins16,+xseal5testalucvmins32,+xseal5testalucvmins8,+xseal5testalucvminu16,+xseal5testalucvminu32,+xseal5testalucvminu8,+xseal5testalucvsletsi16,+xseal5testalucvsletsi32,+xseal5testalucvsletui16,+xseal5testalucvsletui32,+xseal5testalucvsubnrsi16,+xseal5testalucvsubnrsi32,+xseal5testalucvsubnrui16,+xseal5testalucvsubnrui32,+xseal5testalucvsubns,+xseal5testalucvsubnu,+xseal5testalucvsubrnrsi16,+xseal5testalucvsubrnrsi32,+xseal5testalucvsubrnrui16,+xseal5testalucvsubrnrui32,+xseal5testalucvsubrns,+xseal5testalucvsubrnu,+xseal5testmaccvmachhns,+xseal5testmaccvmachhnu,+xseal5testmaccvmachhrns,+xseal5testmaccvmachhrnu,+xseal5testmaccvmacns,+xseal5testmaccvmacnu,+xseal5testmaccvmacrns,+xseal5testmaccvmacrnu,+xseal5testmaccvmacsi16,+xseal5testmaccvmacsi32,+xseal5testmaccvmacui16,+xseal5testmaccvmacui32,+xseal5testmaccvmsusi16,+xseal5testmaccvmsusi32,+xseal5testmaccvmsuui16,+xseal5testmaccvmsuui32,+xseal5testmaccvmulhhns,+xseal5testmaccvmulhhnu,+xseal5testmaccvmulhhrns,+xseal5testmaccvmulhhrnu,+xseal5testmaccvmulns,+xseal5testmaccvmulnu,+xseal5testmaccvmulrns,+xseal5testmaccvmulrnu,-a,-c,-d,-e,-experimental-zacas,-experimental-zcmop,-experimental-zfbfmin,-experimental-zicfilp,-experimental-zicfiss,-experimental-zimop,-experimental-ztso,-experimental-zvfbfmin,-experimental-zvfbfwma,-f,-h,-smaia,-smepmp,-ssaia,-svinval,-svnapot,-svpbmt,-v,-xcvalu,-xcvbi,-xcvbitmanip,-xcvelw,-xcvmac,-xcvmem,-xcvsimd,-xsfvcp,-xsfvfnrclipxfqf,-xsfvfwmaccqqq,-xsfvqmaccdod,-xsfvqmaccqoq,-xtheadba,-xtheadbb,-xtheadbs,-xtheadcmo,-xtheadcondmov,-xtheadfmemidx,-xtheadmac,-xtheadmemidx,-xtheadmempair,-xtheadsync,-xtheadvdot,-xventanacondops,-za128rs,-za64rs,-zawrs,-zba,-zbb,-zbc,-zbkb,-zbkc,-zbkx,-zbs,-zca,-zcb,-zcd,-zce,-zcf,-zcmp,-zcmt,-zdinx,-zfa,-zfh,-zfhmin,-zfinx,-zhinx,-zhinxmin,-zic64b,-zicbom,-zicbop,-zicboz,-ziccamoa,-ziccif,-zicclsm,-ziccrse,-zicntr,-zicond,-zicsr,-zifencei,-zihintntl,-zihintpause,-zihpm,-zk,-zkn,-zknd,-zkne,-zknh,-zkr,-zks,-zksed,-zksh,-zkt,-zmmul,-zvbb,-zvbc,-zve32f,-zve32x,-zve64d,-zve64f,-zve64x,-zvfh,-zvfhmin,-zvkb,-zvkg,-zvkn,-zvknc,-zvkned,-zvkng,-zvknha,-zvknhb,-zvks,-zvksc,-zvksed,-zvksg,-zvksh,-zvkt,-zvl1024b,-zvl128b,-zvl16384b,-zvl2048b,-zvl256b,-zvl32768b,-zvl32b,-zvl4096b,-zvl512b,-zvl64b,-zvl65536b,-zvl8192b" }

!llvm.module.flags = !{!0, !1, !2}
!llvm.ident = !{!3}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 1, !"target-abi", !"ilp32"}
!2 = !{i32 8, !"SmallDataLimit", i32 8}
!3 = !{!"clang version 18.1.0rc (https://github.com/llvm/llvm-project.git 1acc4e456481e76822c76c850bad3994d4e04b59)"}
; *** IR Dump After RelLookupTableConverterPass on [module] ***
; ModuleID = 'cecil_test.c'
source_filename = "cecil_test.c"
target datalayout = "e-m:e-p:32:32-i64:64-n32-S128"
target triple = "riscv32-unknown-unknown"

; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none)
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv4, %conv1
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv11, %conv7
  %add = add i32 %mul12, %acc
  %add13 = add i32 %add, %mul
  ret i32 %add13
}

attributes #0 = { mustprogress nofree norecurse nosync nounwind willreturn memory(none) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="generic-rv32" "target-features"="+32bit,+m,+relax,+xseal5testalucvabs16,+xseal5testalucvabs32,+xseal5testalucvabs8,+xseal5testalucvaddnrsi16,+xseal5testalucvaddnrsi32,+xseal5testalucvaddnrui16,+xseal5testalucvaddnrui32,+xseal5testalucvaddns,+xseal5testalucvaddnu,+xseal5testalucvaddrnrsi16,+xseal5testalucvaddrnrsi32,+xseal5testalucvaddrnrui16,+xseal5testalucvaddrnrui32,+xseal5testalucvaddrns,+xseal5testalucvaddrnu,+xseal5testalucvextbs,+xseal5testalucvextbz,+xseal5testalucvexths,+xseal5testalucvexthz,+xseal5testalucvmaxi1216,+xseal5testalucvmaxi1232,+xseal5testalucvmaxi516,+xseal5testalucvmaxi532,+xseal5testalucvmaxs16,+xseal5testalucvmaxs32,+xseal5testalucvmaxs8,+xseal5testalucvmaxu16,+xseal5testalucvmaxu32,+xseal5testalucvmaxu8,+xseal5testalucvmini1216,+xseal5testalucvmini1232,+xseal5testalucvmini516,+xseal5testalucvmini532,+xseal5testalucvmins16,+xseal5testalucvmins32,+xseal5testalucvmins8,+xseal5testalucvminu16,+xseal5testalucvminu32,+xseal5testalucvminu8,+xseal5testalucvsletsi16,+xseal5testalucvsletsi32,+xseal5testalucvsletui16,+xseal5testalucvsletui32,+xseal5testalucvsubnrsi16,+xseal5testalucvsubnrsi32,+xseal5testalucvsubnrui16,+xseal5testalucvsubnrui32,+xseal5testalucvsubns,+xseal5testalucvsubnu,+xseal5testalucvsubrnrsi16,+xseal5testalucvsubrnrsi32,+xseal5testalucvsubrnrui16,+xseal5testalucvsubrnrui32,+xseal5testalucvsubrns,+xseal5testalucvsubrnu,+xseal5testmaccvmachhns,+xseal5testmaccvmachhnu,+xseal5testmaccvmachhrns,+xseal5testmaccvmachhrnu,+xseal5testmaccvmacns,+xseal5testmaccvmacnu,+xseal5testmaccvmacrns,+xseal5testmaccvmacrnu,+xseal5testmaccvmacsi16,+xseal5testmaccvmacsi32,+xseal5testmaccvmacui16,+xseal5testmaccvmacui32,+xseal5testmaccvmsusi16,+xseal5testmaccvmsusi32,+xseal5testmaccvmsuui16,+xseal5testmaccvmsuui32,+xseal5testmaccvmulhhns,+xseal5testmaccvmulhhnu,+xseal5testmaccvmulhhrns,+xseal5testmaccvmulhhrnu,+xseal5testmaccvmulns,+xseal5testmaccvmulnu,+xseal5testmaccvmulrns,+xseal5testmaccvmulrnu,-a,-c,-d,-e,-experimental-zacas,-experimental-zcmop,-experimental-zfbfmin,-experimental-zicfilp,-experimental-zicfiss,-experimental-zimop,-experimental-ztso,-experimental-zvfbfmin,-experimental-zvfbfwma,-f,-h,-smaia,-smepmp,-ssaia,-svinval,-svnapot,-svpbmt,-v,-xcvalu,-xcvbi,-xcvbitmanip,-xcvelw,-xcvmac,-xcvmem,-xcvsimd,-xsfvcp,-xsfvfnrclipxfqf,-xsfvfwmaccqqq,-xsfvqmaccdod,-xsfvqmaccqoq,-xtheadba,-xtheadbb,-xtheadbs,-xtheadcmo,-xtheadcondmov,-xtheadfmemidx,-xtheadmac,-xtheadmemidx,-xtheadmempair,-xtheadsync,-xtheadvdot,-xventanacondops,-za128rs,-za64rs,-zawrs,-zba,-zbb,-zbc,-zbkb,-zbkc,-zbkx,-zbs,-zca,-zcb,-zcd,-zce,-zcf,-zcmp,-zcmt,-zdinx,-zfa,-zfh,-zfhmin,-zfinx,-zhinx,-zhinxmin,-zic64b,-zicbom,-zicbop,-zicboz,-ziccamoa,-ziccif,-zicclsm,-ziccrse,-zicntr,-zicond,-zicsr,-zifencei,-zihintntl,-zihintpause,-zihpm,-zk,-zkn,-zknd,-zkne,-zknh,-zkr,-zks,-zksed,-zksh,-zkt,-zmmul,-zvbb,-zvbc,-zve32f,-zve32x,-zve64d,-zve64f,-zve64x,-zvfh,-zvfhmin,-zvkb,-zvkg,-zvkn,-zvknc,-zvkned,-zvkng,-zvknha,-zvknhb,-zvks,-zvksc,-zvksed,-zvksg,-zvksh,-zvkt,-zvl1024b,-zvl128b,-zvl16384b,-zvl2048b,-zvl256b,-zvl32768b,-zvl32b,-zvl4096b,-zvl512b,-zvl64b,-zvl65536b,-zvl8192b" }

!llvm.module.flags = !{!0, !1, !2}
!llvm.ident = !{!3}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 1, !"target-abi", !"ilp32"}
!2 = !{i32 8, !"SmallDataLimit", i32 8}
!3 = !{!"clang version 18.1.0rc (https://github.com/llvm/llvm-project.git 1acc4e456481e76822c76c850bad3994d4e04b59)"}
; *** IR Dump Before AnnotationRemarksPass on test_macs32_v2i16 ***
; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none)
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv4, %conv1
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv11, %conv7
  %add = add i32 %mul12, %acc
  %add13 = add i32 %add, %mul
  ret i32 %add13
}
; *** IR Dump After AnnotationRemarksPass on test_macs32_v2i16 ***
; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none)
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv4, %conv1
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv11, %conv7
  %add = add i32 %mul12, %acc
  %add13 = add i32 %add, %mul
  ret i32 %add13
}
*** IR Dump Before ObjC ARC contraction (objc-arc-contract) ***
; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none)
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv4, %conv1
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv11, %conv7
  %add = add i32 %mul12, %acc
  %add13 = add i32 %add, %mul
  ret i32 %add13
}
**** ObjCARC Contract ****
Visiting:   %sext = shl i32 %x, 16
Visiting:   %conv1 = ashr exact i32 %sext, 16
Visiting:   %sext18 = shl i32 %y, 16
Visiting:   %conv4 = ashr exact i32 %sext18, 16
Visiting:   %mul = mul nsw i32 %conv4, %conv1
Visiting:   %conv7 = ashr i32 %x, 16
Visiting:   %conv11 = ashr i32 %y, 16
Visiting:   %mul12 = mul nsw i32 %conv11, %conv7
Visiting:   %add = add i32 %mul12, %acc
Visiting:   %add13 = add i32 %add, %mul
Visiting:   ret i32 %add13
*** IR Dump After ObjC ARC contraction (objc-arc-contract) ***
; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none)
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv4, %conv1
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv11, %conv7
  %add = add i32 %mul12, %acc
  %add13 = add i32 %add, %mul
  ret i32 %add13
}
*** IR Dump Before Pre-ISel Intrinsic Lowering (pre-isel-intrinsic-lowering) ***
; ModuleID = 'cecil_test.c'
source_filename = "cecil_test.c"
target datalayout = "e-m:e-p:32:32-i64:64-n32-S128"
target triple = "riscv32-unknown-unknown"

; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none)
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv4, %conv1
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv11, %conv7
  %add = add i32 %mul12, %acc
  %add13 = add i32 %add, %mul
  ret i32 %add13
}

attributes #0 = { mustprogress nofree norecurse nosync nounwind willreturn memory(none) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="generic-rv32" "target-features"="+32bit,+m,+relax,+xseal5testalucvabs16,+xseal5testalucvabs32,+xseal5testalucvabs8,+xseal5testalucvaddnrsi16,+xseal5testalucvaddnrsi32,+xseal5testalucvaddnrui16,+xseal5testalucvaddnrui32,+xseal5testalucvaddns,+xseal5testalucvaddnu,+xseal5testalucvaddrnrsi16,+xseal5testalucvaddrnrsi32,+xseal5testalucvaddrnrui16,+xseal5testalucvaddrnrui32,+xseal5testalucvaddrns,+xseal5testalucvaddrnu,+xseal5testalucvextbs,+xseal5testalucvextbz,+xseal5testalucvexths,+xseal5testalucvexthz,+xseal5testalucvmaxi1216,+xseal5testalucvmaxi1232,+xseal5testalucvmaxi516,+xseal5testalucvmaxi532,+xseal5testalucvmaxs16,+xseal5testalucvmaxs32,+xseal5testalucvmaxs8,+xseal5testalucvmaxu16,+xseal5testalucvmaxu32,+xseal5testalucvmaxu8,+xseal5testalucvmini1216,+xseal5testalucvmini1232,+xseal5testalucvmini516,+xseal5testalucvmini532,+xseal5testalucvmins16,+xseal5testalucvmins32,+xseal5testalucvmins8,+xseal5testalucvminu16,+xseal5testalucvminu32,+xseal5testalucvminu8,+xseal5testalucvsletsi16,+xseal5testalucvsletsi32,+xseal5testalucvsletui16,+xseal5testalucvsletui32,+xseal5testalucvsubnrsi16,+xseal5testalucvsubnrsi32,+xseal5testalucvsubnrui16,+xseal5testalucvsubnrui32,+xseal5testalucvsubns,+xseal5testalucvsubnu,+xseal5testalucvsubrnrsi16,+xseal5testalucvsubrnrsi32,+xseal5testalucvsubrnrui16,+xseal5testalucvsubrnrui32,+xseal5testalucvsubrns,+xseal5testalucvsubrnu,+xseal5testmaccvmachhns,+xseal5testmaccvmachhnu,+xseal5testmaccvmachhrns,+xseal5testmaccvmachhrnu,+xseal5testmaccvmacns,+xseal5testmaccvmacnu,+xseal5testmaccvmacrns,+xseal5testmaccvmacrnu,+xseal5testmaccvmacsi16,+xseal5testmaccvmacsi32,+xseal5testmaccvmacui16,+xseal5testmaccvmacui32,+xseal5testmaccvmsusi16,+xseal5testmaccvmsusi32,+xseal5testmaccvmsuui16,+xseal5testmaccvmsuui32,+xseal5testmaccvmulhhns,+xseal5testmaccvmulhhnu,+xseal5testmaccvmulhhrns,+xseal5testmaccvmulhhrnu,+xseal5testmaccvmulns,+xseal5testmaccvmulnu,+xseal5testmaccvmulrns,+xseal5testmaccvmulrnu,-a,-c,-d,-e,-experimental-zacas,-experimental-zcmop,-experimental-zfbfmin,-experimental-zicfilp,-experimental-zicfiss,-experimental-zimop,-experimental-ztso,-experimental-zvfbfmin,-experimental-zvfbfwma,-f,-h,-smaia,-smepmp,-ssaia,-svinval,-svnapot,-svpbmt,-v,-xcvalu,-xcvbi,-xcvbitmanip,-xcvelw,-xcvmac,-xcvmem,-xcvsimd,-xsfvcp,-xsfvfnrclipxfqf,-xsfvfwmaccqqq,-xsfvqmaccdod,-xsfvqmaccqoq,-xtheadba,-xtheadbb,-xtheadbs,-xtheadcmo,-xtheadcondmov,-xtheadfmemidx,-xtheadmac,-xtheadmemidx,-xtheadmempair,-xtheadsync,-xtheadvdot,-xventanacondops,-za128rs,-za64rs,-zawrs,-zba,-zbb,-zbc,-zbkb,-zbkc,-zbkx,-zbs,-zca,-zcb,-zcd,-zce,-zcf,-zcmp,-zcmt,-zdinx,-zfa,-zfh,-zfhmin,-zfinx,-zhinx,-zhinxmin,-zic64b,-zicbom,-zicbop,-zicboz,-ziccamoa,-ziccif,-zicclsm,-ziccrse,-zicntr,-zicond,-zicsr,-zifencei,-zihintntl,-zihintpause,-zihpm,-zk,-zkn,-zknd,-zkne,-zknh,-zkr,-zks,-zksed,-zksh,-zkt,-zmmul,-zvbb,-zvbc,-zve32f,-zve32x,-zve64d,-zve64f,-zve64x,-zvfh,-zvfhmin,-zvkb,-zvkg,-zvkn,-zvknc,-zvkned,-zvkng,-zvknha,-zvknhb,-zvks,-zvksc,-zvksed,-zvksg,-zvksh,-zvkt,-zvl1024b,-zvl128b,-zvl16384b,-zvl2048b,-zvl256b,-zvl32768b,-zvl32b,-zvl4096b,-zvl512b,-zvl64b,-zvl65536b,-zvl8192b" }

!llvm.module.flags = !{!0, !1, !2}
!llvm.ident = !{!3}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 1, !"target-abi", !"ilp32"}
!2 = !{i32 8, !"SmallDataLimit", i32 8}
!3 = !{!"clang version 18.1.0rc (https://github.com/llvm/llvm-project.git 1acc4e456481e76822c76c850bad3994d4e04b59)"}
*** IR Dump After Pre-ISel Intrinsic Lowering (pre-isel-intrinsic-lowering) ***
; ModuleID = 'cecil_test.c'
source_filename = "cecil_test.c"
target datalayout = "e-m:e-p:32:32-i64:64-n32-S128"
target triple = "riscv32-unknown-unknown"

; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none)
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv4, %conv1
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv11, %conv7
  %add = add i32 %mul12, %acc
  %add13 = add i32 %add, %mul
  ret i32 %add13
}

attributes #0 = { mustprogress nofree norecurse nosync nounwind willreturn memory(none) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="generic-rv32" "target-features"="+32bit,+m,+relax,+xseal5testalucvabs16,+xseal5testalucvabs32,+xseal5testalucvabs8,+xseal5testalucvaddnrsi16,+xseal5testalucvaddnrsi32,+xseal5testalucvaddnrui16,+xseal5testalucvaddnrui32,+xseal5testalucvaddns,+xseal5testalucvaddnu,+xseal5testalucvaddrnrsi16,+xseal5testalucvaddrnrsi32,+xseal5testalucvaddrnrui16,+xseal5testalucvaddrnrui32,+xseal5testalucvaddrns,+xseal5testalucvaddrnu,+xseal5testalucvextbs,+xseal5testalucvextbz,+xseal5testalucvexths,+xseal5testalucvexthz,+xseal5testalucvmaxi1216,+xseal5testalucvmaxi1232,+xseal5testalucvmaxi516,+xseal5testalucvmaxi532,+xseal5testalucvmaxs16,+xseal5testalucvmaxs32,+xseal5testalucvmaxs8,+xseal5testalucvmaxu16,+xseal5testalucvmaxu32,+xseal5testalucvmaxu8,+xseal5testalucvmini1216,+xseal5testalucvmini1232,+xseal5testalucvmini516,+xseal5testalucvmini532,+xseal5testalucvmins16,+xseal5testalucvmins32,+xseal5testalucvmins8,+xseal5testalucvminu16,+xseal5testalucvminu32,+xseal5testalucvminu8,+xseal5testalucvsletsi16,+xseal5testalucvsletsi32,+xseal5testalucvsletui16,+xseal5testalucvsletui32,+xseal5testalucvsubnrsi16,+xseal5testalucvsubnrsi32,+xseal5testalucvsubnrui16,+xseal5testalucvsubnrui32,+xseal5testalucvsubns,+xseal5testalucvsubnu,+xseal5testalucvsubrnrsi16,+xseal5testalucvsubrnrsi32,+xseal5testalucvsubrnrui16,+xseal5testalucvsubrnrui32,+xseal5testalucvsubrns,+xseal5testalucvsubrnu,+xseal5testmaccvmachhns,+xseal5testmaccvmachhnu,+xseal5testmaccvmachhrns,+xseal5testmaccvmachhrnu,+xseal5testmaccvmacns,+xseal5testmaccvmacnu,+xseal5testmaccvmacrns,+xseal5testmaccvmacrnu,+xseal5testmaccvmacsi16,+xseal5testmaccvmacsi32,+xseal5testmaccvmacui16,+xseal5testmaccvmacui32,+xseal5testmaccvmsusi16,+xseal5testmaccvmsusi32,+xseal5testmaccvmsuui16,+xseal5testmaccvmsuui32,+xseal5testmaccvmulhhns,+xseal5testmaccvmulhhnu,+xseal5testmaccvmulhhrns,+xseal5testmaccvmulhhrnu,+xseal5testmaccvmulns,+xseal5testmaccvmulnu,+xseal5testmaccvmulrns,+xseal5testmaccvmulrnu,-a,-c,-d,-e,-experimental-zacas,-experimental-zcmop,-experimental-zfbfmin,-experimental-zicfilp,-experimental-zicfiss,-experimental-zimop,-experimental-ztso,-experimental-zvfbfmin,-experimental-zvfbfwma,-f,-h,-smaia,-smepmp,-ssaia,-svinval,-svnapot,-svpbmt,-v,-xcvalu,-xcvbi,-xcvbitmanip,-xcvelw,-xcvmac,-xcvmem,-xcvsimd,-xsfvcp,-xsfvfnrclipxfqf,-xsfvfwmaccqqq,-xsfvqmaccdod,-xsfvqmaccqoq,-xtheadba,-xtheadbb,-xtheadbs,-xtheadcmo,-xtheadcondmov,-xtheadfmemidx,-xtheadmac,-xtheadmemidx,-xtheadmempair,-xtheadsync,-xtheadvdot,-xventanacondops,-za128rs,-za64rs,-zawrs,-zba,-zbb,-zbc,-zbkb,-zbkc,-zbkx,-zbs,-zca,-zcb,-zcd,-zce,-zcf,-zcmp,-zcmt,-zdinx,-zfa,-zfh,-zfhmin,-zfinx,-zhinx,-zhinxmin,-zic64b,-zicbom,-zicbop,-zicboz,-ziccamoa,-ziccif,-zicclsm,-ziccrse,-zicntr,-zicond,-zicsr,-zifencei,-zihintntl,-zihintpause,-zihpm,-zk,-zkn,-zknd,-zkne,-zknh,-zkr,-zks,-zksed,-zksh,-zkt,-zmmul,-zvbb,-zvbc,-zve32f,-zve32x,-zve64d,-zve64f,-zve64x,-zvfh,-zvfhmin,-zvkb,-zvkg,-zvkn,-zvknc,-zvkned,-zvkng,-zvknha,-zvknhb,-zvks,-zvksc,-zvksed,-zvksg,-zvksh,-zvkt,-zvl1024b,-zvl128b,-zvl16384b,-zvl2048b,-zvl256b,-zvl32768b,-zvl32b,-zvl4096b,-zvl512b,-zvl64b,-zvl65536b,-zvl8192b" }

!llvm.module.flags = !{!0, !1, !2}
!llvm.ident = !{!3}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 1, !"target-abi", !"ilp32"}
!2 = !{i32 8, !"SmallDataLimit", i32 8}
!3 = !{!"clang version 18.1.0rc (https://github.com/llvm/llvm-project.git 1acc4e456481e76822c76c850bad3994d4e04b59)"}
*** IR Dump Before Expand large div/rem (expand-large-div-rem) ***
; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none)
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv4, %conv1
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv11, %conv7
  %add = add i32 %mul12, %acc
  %add13 = add i32 %add, %mul
  ret i32 %add13
}
*** IR Dump After Expand large div/rem (expand-large-div-rem) ***
; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none)
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv4, %conv1
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv11, %conv7
  %add = add i32 %mul12, %acc
  %add13 = add i32 %add, %mul
  ret i32 %add13
}
*** IR Dump Before Expand large fp convert (expand-large-fp-convert) ***
; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none)
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv4, %conv1
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv11, %conv7
  %add = add i32 %mul12, %acc
  %add13 = add i32 %add, %mul
  ret i32 %add13
}
*** IR Dump After Expand large fp convert (expand-large-fp-convert) ***
; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none)
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv4, %conv1
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv11, %conv7
  %add = add i32 %mul12, %acc
  %add13 = add i32 %add, %mul
  ret i32 %add13
}
*** IR Dump Before Expand Atomic instructions (atomic-expand) ***
; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none)
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv4, %conv1
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv11, %conv7
  %add = add i32 %mul12, %acc
  %add13 = add i32 %add, %mul
  ret i32 %add13
}
*** IR Dump After Expand Atomic instructions (atomic-expand) ***
; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none)
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv4, %conv1
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv11, %conv7
  %add = add i32 %mul12, %acc
  %add13 = add i32 %add, %mul
  ret i32 %add13
}
*** IR Dump Before Canonicalize natural loops (loop-simplify) ***
; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none)
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv4, %conv1
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv11, %conv7
  %add = add i32 %mul12, %acc
  %add13 = add i32 %add, %mul
  ret i32 %add13
}
*** IR Dump After Canonicalize natural loops (loop-simplify) ***
; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none)
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv4, %conv1
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv11, %conv7
  %add = add i32 %mul12, %acc
  %add13 = add i32 %add, %mul
  ret i32 %add13
}
*** IR Dump Before Loop Data Prefetch (loop-data-prefetch) ***
; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none)
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv4, %conv1
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv11, %conv7
  %add = add i32 %mul12, %acc
  %add13 = add i32 %add, %mul
  ret i32 %add13
}
Please set both PrefetchDistance and CacheLineSize for loop data prefetch.
*** IR Dump After Loop Data Prefetch (loop-data-prefetch) ***
; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none)
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv4, %conv1
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv11, %conv7
  %add = add i32 %mul12, %acc
  %add13 = add i32 %add, %mul
  ret i32 %add13
}
*** IR Dump Before RISC-V gather/scatter lowering (riscv-gather-scatter-lowering) ***
; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none)
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv4, %conv1
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv11, %conv7
  %add = add i32 %mul12, %acc
  %add13 = add i32 %add, %mul
  ret i32 %add13
}
*** IR Dump After RISC-V gather/scatter lowering (riscv-gather-scatter-lowering) ***
; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none)
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv4, %conv1
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv11, %conv7
  %add = add i32 %mul12, %acc
  %add13 = add i32 %add, %mul
  ret i32 %add13
}
*** IR Dump Before Interleaved Access Pass (interleaved-access) ***
; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none)
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv4, %conv1
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv11, %conv7
  %add = add i32 %mul12, %acc
  %add13 = add i32 %add, %mul
  ret i32 %add13
}
*** Interleaved Access Pass: test_macs32_v2i16
*** IR Dump After Interleaved Access Pass (interleaved-access) ***
; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none)
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv4, %conv1
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv11, %conv7
  %add = add i32 %mul12, %acc
  %add13 = add i32 %add, %mul
  ret i32 %add13
}
*** IR Dump Before RISC-V CodeGenPrepare (riscv-codegenprepare) ***
; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none)
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv4, %conv1
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv11, %conv7
  %add = add i32 %mul12, %acc
  %add13 = add i32 %add, %mul
  ret i32 %add13
}
*** IR Dump After RISC-V CodeGenPrepare (riscv-codegenprepare) ***
; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none)
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv4, %conv1
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv11, %conv7
  %add = add i32 %mul12, %acc
  %add13 = add i32 %add, %mul
  ret i32 %add13
}
*** IR Dump Before Module Verifier (verify) ***
; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none)
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv4, %conv1
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv11, %conv7
  %add = add i32 %mul12, %acc
  %add13 = add i32 %add, %mul
  ret i32 %add13
}
*** IR Dump After Module Verifier (verify) ***
; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none)
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv4, %conv1
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv11, %conv7
  %add = add i32 %mul12, %acc
  %add13 = add i32 %add, %mul
  ret i32 %add13
}
*** IR Dump Before Canonicalize natural loops (loop-simplify) ***
; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none)
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv4, %conv1
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv11, %conv7
  %add = add i32 %mul12, %acc
  %add13 = add i32 %add, %mul
  ret i32 %add13
}
*** IR Dump After Canonicalize natural loops (loop-simplify) ***
; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none)
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv4, %conv1
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv11, %conv7
  %add = add i32 %mul12, %acc
  %add13 = add i32 %add, %mul
  ret i32 %add13
}
*** IR Dump Before Merge contiguous icmps into a memcmp (mergeicmps) ***
; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none)
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv4, %conv1
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv11, %conv7
  %add = add i32 %mul12, %acc
  %add13 = add i32 %add, %mul
  ret i32 %add13
}
MergeICmpsLegacyPass: test_macs32_v2i16
*** IR Dump After Merge contiguous icmps into a memcmp (mergeicmps) ***
; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none)
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv4, %conv1
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv11, %conv7
  %add = add i32 %mul12, %acc
  %add13 = add i32 %add, %mul
  ret i32 %add13
}
*** IR Dump Before Expand memcmp() to load/stores (expand-memcmp) ***
; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none)
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv4, %conv1
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv11, %conv7
  %add = add i32 %mul12, %acc
  %add13 = add i32 %add, %mul
  ret i32 %add13
}
*** IR Dump After Expand memcmp() to load/stores (expand-memcmp) ***
; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none)
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv4, %conv1
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv11, %conv7
  %add = add i32 %mul12, %acc
  %add13 = add i32 %add, %mul
  ret i32 %add13
}
*** IR Dump Before Lower Garbage Collection Instructions (gc-lowering) ***
; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none)
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv4, %conv1
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv11, %conv7
  %add = add i32 %mul12, %acc
  %add13 = add i32 %add, %mul
  ret i32 %add13
}
*** IR Dump After Lower Garbage Collection Instructions (gc-lowering) ***
; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none)
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv4, %conv1
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv11, %conv7
  %add = add i32 %mul12, %acc
  %add13 = add i32 %add, %mul
  ret i32 %add13
}
*** IR Dump Before Shadow Stack GC Lowering (shadow-stack-gc-lowering) ***
; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none)
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv4, %conv1
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv11, %conv7
  %add = add i32 %mul12, %acc
  %add13 = add i32 %add, %mul
  ret i32 %add13
}
*** IR Dump After Shadow Stack GC Lowering (shadow-stack-gc-lowering) ***
; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none)
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv4, %conv1
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv11, %conv7
  %add = add i32 %mul12, %acc
  %add13 = add i32 %add, %mul
  ret i32 %add13
}
*** IR Dump Before Lower constant intrinsics (lower-constant-intrinsics) ***
; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none)
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv4, %conv1
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv11, %conv7
  %add = add i32 %mul12, %acc
  %add13 = add i32 %add, %mul
  ret i32 %add13
}
*** IR Dump After Lower constant intrinsics (lower-constant-intrinsics) ***
; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none)
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv4, %conv1
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv11, %conv7
  %add = add i32 %mul12, %acc
  %add13 = add i32 %add, %mul
  ret i32 %add13
}
*** IR Dump Before Remove unreachable blocks from the CFG (unreachableblockelim) ***
; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none)
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv4, %conv1
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv11, %conv7
  %add = add i32 %mul12, %acc
  %add13 = add i32 %add, %mul
  ret i32 %add13
}
*** IR Dump After Remove unreachable blocks from the CFG (unreachableblockelim) ***
; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none)
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv4, %conv1
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv11, %conv7
  %add = add i32 %mul12, %acc
  %add13 = add i32 %add, %mul
  ret i32 %add13
}
		Looking for trivial roots
Found a new trivial root: %entry
Last visited node: %entry
		Looking for non-trivial roots
Total: 1, Num: 2
Discovered CFG nodes:
0: nullptr
1: nullptr
2: %entry
Found roots: %entry 
---- Branch Probability Info : test_macs32_v2i16 ----

Computing probabilities for entry

block-frequency: test_macs32_v2i16
==================================
reverse-post-order-traversal
 - 0: entry
loop-detection
compute-mass-in-function
 - node: entry
  => mass:  ffffffffffffffff
float-to-int: min = 1.0, max = 1.0, factor = 18014398509481984.0
 - entry: float = 1.0, scaled = 18014398509481984.0, int = 18014398509481984
block-frequency-info: test_macs32_v2i16
 - entry: float = 1.0, int = 18014398509481984

*** IR Dump Before Constant Hoisting (consthoist) ***
; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none)
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv4, %conv1
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv11, %conv7
  %add = add i32 %mul12, %acc
  %add13 = add i32 %add, %mul
  ret i32 %add13
}
********** Begin Constant Hoisting **********
********** Function: test_macs32_v2i16
********** End Constant Hoisting **********
*** IR Dump After Constant Hoisting (consthoist) ***
; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none)
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv4, %conv1
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv11, %conv7
  %add = add i32 %mul12, %acc
  %add13 = add i32 %add, %mul
  ret i32 %add13
}
*** IR Dump Before Replace intrinsics with calls to vector library (replace-with-veclib) ***
; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none)
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv4, %conv1
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv11, %conv7
  %add = add i32 %mul12, %acc
  %add13 = add i32 %add, %mul
  ret i32 %add13
}
*** IR Dump After Replace intrinsics with calls to vector library (replace-with-veclib) ***
; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none)
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv4, %conv1
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv11, %conv7
  %add = add i32 %mul12, %acc
  %add13 = add i32 %add, %mul
  ret i32 %add13
}
*** IR Dump Before Partially inline calls to library functions (partially-inline-libcalls) ***
; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none)
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv4, %conv1
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv11, %conv7
  %add = add i32 %mul12, %acc
  %add13 = add i32 %add, %mul
  ret i32 %add13
}
*** IR Dump After Partially inline calls to library functions (partially-inline-libcalls) ***
; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none)
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv4, %conv1
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv11, %conv7
  %add = add i32 %mul12, %acc
  %add13 = add i32 %add, %mul
  ret i32 %add13
}
*** IR Dump Before Expand vector predication intrinsics (expandvp) ***
; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none)
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv4, %conv1
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv11, %conv7
  %add = add i32 %mul12, %acc
  %add13 = add i32 %add, %mul
  ret i32 %add13
}
*** IR Dump After Expand vector predication intrinsics (expandvp) ***
; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none)
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv4, %conv1
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv11, %conv7
  %add = add i32 %mul12, %acc
  %add13 = add i32 %add, %mul
  ret i32 %add13
}
*** IR Dump Before Scalarize Masked Memory Intrinsics (scalarize-masked-mem-intrin) ***
; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none)
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv4, %conv1
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv11, %conv7
  %add = add i32 %mul12, %acc
  %add13 = add i32 %add, %mul
  ret i32 %add13
}
*** IR Dump After Scalarize Masked Memory Intrinsics (scalarize-masked-mem-intrin) ***
; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none)
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv4, %conv1
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv11, %conv7
  %add = add i32 %mul12, %acc
  %add13 = add i32 %add, %mul
  ret i32 %add13
}
*** IR Dump Before Expand reduction intrinsics (expand-reductions) ***
; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none)
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv4, %conv1
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv11, %conv7
  %add = add i32 %mul12, %acc
  %add13 = add i32 %add, %mul
  ret i32 %add13
}
*** IR Dump After Expand reduction intrinsics (expand-reductions) ***
; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none)
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv4, %conv1
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv11, %conv7
  %add = add i32 %mul12, %acc
  %add13 = add i32 %add, %mul
  ret i32 %add13
}
*** IR Dump Before TLS Variable Hoist (tlshoist) ***
; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none)
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv4, %conv1
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv11, %conv7
  %add = add i32 %mul12, %acc
  %add13 = add i32 %add, %mul
  ret i32 %add13
}
********** Begin TLS Variable Hoist **********
********** Function: test_macs32_v2i16
********** End TLS Variable Hoist **********
*** IR Dump After TLS Variable Hoist (tlshoist) ***
; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none)
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv4, %conv1
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv11, %conv7
  %add = add i32 %mul12, %acc
  %add13 = add i32 %add, %mul
  ret i32 %add13
}
*** IR Dump Before CodeGen Prepare (codegenprepare) ***
; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none)
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv4, %conv1
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv11, %conv7
  %add = add i32 %mul12, %acc
  %add13 = add i32 %add, %mul
  ret i32 %add13
}
---- Branch Probability Info : test_macs32_v2i16 ----

		Looking for trivial roots
Found a new trivial root: %entry
Last visited node: %entry
		Looking for non-trivial roots
Total: 1, Num: 2
Discovered CFG nodes:
0: nullptr
1: nullptr
2: %entry
Found roots: %entry 
Computing probabilities for entry

block-frequency: test_macs32_v2i16
==================================
reverse-post-order-traversal
 - 0: entry
loop-detection
compute-mass-in-function
 - node: entry
  => mass:  ffffffffffffffff
float-to-int: min = 1.0, max = 1.0, factor = 18014398509481984.0
 - entry: float = 1.0, scaled = 18014398509481984.0, int = 18014398509481984
block-frequency-info: test_macs32_v2i16
 - entry: float = 1.0, int = 18014398509481984

*** IR Dump After CodeGen Prepare (codegenprepare) ***
; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none)
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv4, %conv1
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv11, %conv7
  %add = add i32 %mul12, %acc
  %add13 = add i32 %add, %mul
  ret i32 %add13
}
*** IR Dump Before Exception handling preparation (dwarf-eh-prepare) ***
; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none)
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv4, %conv1
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv11, %conv7
  %add = add i32 %mul12, %acc
  %add13 = add i32 %add, %mul
  ret i32 %add13
}
*** IR Dump After Exception handling preparation (dwarf-eh-prepare) ***
; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none)
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv4, %conv1
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv11, %conv7
  %add = add i32 %mul12, %acc
  %add13 = add i32 %add, %mul
  ret i32 %add13
}
*** IR Dump Before A No-Op Barrier Pass (barrier) ***
; ModuleID = 'cecil_test.c'
source_filename = "cecil_test.c"
target datalayout = "e-m:e-p:32:32-i64:64-n32-S128"
target triple = "riscv32-unknown-unknown"

; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none)
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv4, %conv1
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv11, %conv7
  %add = add i32 %mul12, %acc
  %add13 = add i32 %add, %mul
  ret i32 %add13
}

attributes #0 = { mustprogress nofree norecurse nosync nounwind willreturn memory(none) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="generic-rv32" "target-features"="+32bit,+m,+relax,+xseal5testalucvabs16,+xseal5testalucvabs32,+xseal5testalucvabs8,+xseal5testalucvaddnrsi16,+xseal5testalucvaddnrsi32,+xseal5testalucvaddnrui16,+xseal5testalucvaddnrui32,+xseal5testalucvaddns,+xseal5testalucvaddnu,+xseal5testalucvaddrnrsi16,+xseal5testalucvaddrnrsi32,+xseal5testalucvaddrnrui16,+xseal5testalucvaddrnrui32,+xseal5testalucvaddrns,+xseal5testalucvaddrnu,+xseal5testalucvextbs,+xseal5testalucvextbz,+xseal5testalucvexths,+xseal5testalucvexthz,+xseal5testalucvmaxi1216,+xseal5testalucvmaxi1232,+xseal5testalucvmaxi516,+xseal5testalucvmaxi532,+xseal5testalucvmaxs16,+xseal5testalucvmaxs32,+xseal5testalucvmaxs8,+xseal5testalucvmaxu16,+xseal5testalucvmaxu32,+xseal5testalucvmaxu8,+xseal5testalucvmini1216,+xseal5testalucvmini1232,+xseal5testalucvmini516,+xseal5testalucvmini532,+xseal5testalucvmins16,+xseal5testalucvmins32,+xseal5testalucvmins8,+xseal5testalucvminu16,+xseal5testalucvminu32,+xseal5testalucvminu8,+xseal5testalucvsletsi16,+xseal5testalucvsletsi32,+xseal5testalucvsletui16,+xseal5testalucvsletui32,+xseal5testalucvsubnrsi16,+xseal5testalucvsubnrsi32,+xseal5testalucvsubnrui16,+xseal5testalucvsubnrui32,+xseal5testalucvsubns,+xseal5testalucvsubnu,+xseal5testalucvsubrnrsi16,+xseal5testalucvsubrnrsi32,+xseal5testalucvsubrnrui16,+xseal5testalucvsubrnrui32,+xseal5testalucvsubrns,+xseal5testalucvsubrnu,+xseal5testmaccvmachhns,+xseal5testmaccvmachhnu,+xseal5testmaccvmachhrns,+xseal5testmaccvmachhrnu,+xseal5testmaccvmacns,+xseal5testmaccvmacnu,+xseal5testmaccvmacrns,+xseal5testmaccvmacrnu,+xseal5testmaccvmacsi16,+xseal5testmaccvmacsi32,+xseal5testmaccvmacui16,+xseal5testmaccvmacui32,+xseal5testmaccvmsusi16,+xseal5testmaccvmsusi32,+xseal5testmaccvmsuui16,+xseal5testmaccvmsuui32,+xseal5testmaccvmulhhns,+xseal5testmaccvmulhhnu,+xseal5testmaccvmulhhrns,+xseal5testmaccvmulhhrnu,+xseal5testmaccvmulns,+xseal5testmaccvmulnu,+xseal5testmaccvmulrns,+xseal5testmaccvmulrnu,-a,-c,-d,-e,-experimental-zacas,-experimental-zcmop,-experimental-zfbfmin,-experimental-zicfilp,-experimental-zicfiss,-experimental-zimop,-experimental-ztso,-experimental-zvfbfmin,-experimental-zvfbfwma,-f,-h,-smaia,-smepmp,-ssaia,-svinval,-svnapot,-svpbmt,-v,-xcvalu,-xcvbi,-xcvbitmanip,-xcvelw,-xcvmac,-xcvmem,-xcvsimd,-xsfvcp,-xsfvfnrclipxfqf,-xsfvfwmaccqqq,-xsfvqmaccdod,-xsfvqmaccqoq,-xtheadba,-xtheadbb,-xtheadbs,-xtheadcmo,-xtheadcondmov,-xtheadfmemidx,-xtheadmac,-xtheadmemidx,-xtheadmempair,-xtheadsync,-xtheadvdot,-xventanacondops,-za128rs,-za64rs,-zawrs,-zba,-zbb,-zbc,-zbkb,-zbkc,-zbkx,-zbs,-zca,-zcb,-zcd,-zce,-zcf,-zcmp,-zcmt,-zdinx,-zfa,-zfh,-zfhmin,-zfinx,-zhinx,-zhinxmin,-zic64b,-zicbom,-zicbop,-zicboz,-ziccamoa,-ziccif,-zicclsm,-ziccrse,-zicntr,-zicond,-zicsr,-zifencei,-zihintntl,-zihintpause,-zihpm,-zk,-zkn,-zknd,-zkne,-zknh,-zkr,-zks,-zksed,-zksh,-zkt,-zmmul,-zvbb,-zvbc,-zve32f,-zve32x,-zve64d,-zve64f,-zve64x,-zvfh,-zvfhmin,-zvkb,-zvkg,-zvkn,-zvknc,-zvkned,-zvkng,-zvknha,-zvknhb,-zvks,-zvksc,-zvksed,-zvksg,-zvksh,-zvkt,-zvl1024b,-zvl128b,-zvl16384b,-zvl2048b,-zvl256b,-zvl32768b,-zvl32b,-zvl4096b,-zvl512b,-zvl64b,-zvl65536b,-zvl8192b" }

!llvm.module.flags = !{!0, !1, !2}
!llvm.ident = !{!3}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 1, !"target-abi", !"ilp32"}
!2 = !{i32 8, !"SmallDataLimit", i32 8}
!3 = !{!"clang version 18.1.0rc (https://github.com/llvm/llvm-project.git 1acc4e456481e76822c76c850bad3994d4e04b59)"}
*** IR Dump After A No-Op Barrier Pass (barrier) ***
; ModuleID = 'cecil_test.c'
source_filename = "cecil_test.c"
target datalayout = "e-m:e-p:32:32-i64:64-n32-S128"
target triple = "riscv32-unknown-unknown"

; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none)
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv4, %conv1
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv11, %conv7
  %add = add i32 %mul12, %acc
  %add13 = add i32 %add, %mul
  ret i32 %add13
}

attributes #0 = { mustprogress nofree norecurse nosync nounwind willreturn memory(none) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="generic-rv32" "target-features"="+32bit,+m,+relax,+xseal5testalucvabs16,+xseal5testalucvabs32,+xseal5testalucvabs8,+xseal5testalucvaddnrsi16,+xseal5testalucvaddnrsi32,+xseal5testalucvaddnrui16,+xseal5testalucvaddnrui32,+xseal5testalucvaddns,+xseal5testalucvaddnu,+xseal5testalucvaddrnrsi16,+xseal5testalucvaddrnrsi32,+xseal5testalucvaddrnrui16,+xseal5testalucvaddrnrui32,+xseal5testalucvaddrns,+xseal5testalucvaddrnu,+xseal5testalucvextbs,+xseal5testalucvextbz,+xseal5testalucvexths,+xseal5testalucvexthz,+xseal5testalucvmaxi1216,+xseal5testalucvmaxi1232,+xseal5testalucvmaxi516,+xseal5testalucvmaxi532,+xseal5testalucvmaxs16,+xseal5testalucvmaxs32,+xseal5testalucvmaxs8,+xseal5testalucvmaxu16,+xseal5testalucvmaxu32,+xseal5testalucvmaxu8,+xseal5testalucvmini1216,+xseal5testalucvmini1232,+xseal5testalucvmini516,+xseal5testalucvmini532,+xseal5testalucvmins16,+xseal5testalucvmins32,+xseal5testalucvmins8,+xseal5testalucvminu16,+xseal5testalucvminu32,+xseal5testalucvminu8,+xseal5testalucvsletsi16,+xseal5testalucvsletsi32,+xseal5testalucvsletui16,+xseal5testalucvsletui32,+xseal5testalucvsubnrsi16,+xseal5testalucvsubnrsi32,+xseal5testalucvsubnrui16,+xseal5testalucvsubnrui32,+xseal5testalucvsubns,+xseal5testalucvsubnu,+xseal5testalucvsubrnrsi16,+xseal5testalucvsubrnrsi32,+xseal5testalucvsubrnrui16,+xseal5testalucvsubrnrui32,+xseal5testalucvsubrns,+xseal5testalucvsubrnu,+xseal5testmaccvmachhns,+xseal5testmaccvmachhnu,+xseal5testmaccvmachhrns,+xseal5testmaccvmachhrnu,+xseal5testmaccvmacns,+xseal5testmaccvmacnu,+xseal5testmaccvmacrns,+xseal5testmaccvmacrnu,+xseal5testmaccvmacsi16,+xseal5testmaccvmacsi32,+xseal5testmaccvmacui16,+xseal5testmaccvmacui32,+xseal5testmaccvmsusi16,+xseal5testmaccvmsusi32,+xseal5testmaccvmsuui16,+xseal5testmaccvmsuui32,+xseal5testmaccvmulhhns,+xseal5testmaccvmulhhnu,+xseal5testmaccvmulhhrns,+xseal5testmaccvmulhhrnu,+xseal5testmaccvmulns,+xseal5testmaccvmulnu,+xseal5testmaccvmulrns,+xseal5testmaccvmulrnu,-a,-c,-d,-e,-experimental-zacas,-experimental-zcmop,-experimental-zfbfmin,-experimental-zicfilp,-experimental-zicfiss,-experimental-zimop,-experimental-ztso,-experimental-zvfbfmin,-experimental-zvfbfwma,-f,-h,-smaia,-smepmp,-ssaia,-svinval,-svnapot,-svpbmt,-v,-xcvalu,-xcvbi,-xcvbitmanip,-xcvelw,-xcvmac,-xcvmem,-xcvsimd,-xsfvcp,-xsfvfnrclipxfqf,-xsfvfwmaccqqq,-xsfvqmaccdod,-xsfvqmaccqoq,-xtheadba,-xtheadbb,-xtheadbs,-xtheadcmo,-xtheadcondmov,-xtheadfmemidx,-xtheadmac,-xtheadmemidx,-xtheadmempair,-xtheadsync,-xtheadvdot,-xventanacondops,-za128rs,-za64rs,-zawrs,-zba,-zbb,-zbc,-zbkb,-zbkc,-zbkx,-zbs,-zca,-zcb,-zcd,-zce,-zcf,-zcmp,-zcmt,-zdinx,-zfa,-zfh,-zfhmin,-zfinx,-zhinx,-zhinxmin,-zic64b,-zicbom,-zicbop,-zicboz,-ziccamoa,-ziccif,-zicclsm,-ziccrse,-zicntr,-zicond,-zicsr,-zifencei,-zihintntl,-zihintpause,-zihpm,-zk,-zkn,-zknd,-zkne,-zknh,-zkr,-zks,-zksed,-zksh,-zkt,-zmmul,-zvbb,-zvbc,-zve32f,-zve32x,-zve64d,-zve64f,-zve64x,-zvfh,-zvfhmin,-zvkb,-zvkg,-zvkn,-zvknc,-zvkned,-zvkng,-zvknha,-zvknhb,-zvks,-zvksc,-zvksed,-zvksg,-zvksh,-zvkt,-zvl1024b,-zvl128b,-zvl16384b,-zvl2048b,-zvl256b,-zvl32768b,-zvl32b,-zvl4096b,-zvl512b,-zvl64b,-zvl65536b,-zvl8192b" }

!llvm.module.flags = !{!0, !1, !2}
!llvm.ident = !{!3}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 1, !"target-abi", !"ilp32"}
!2 = !{i32 8, !"SmallDataLimit", i32 8}
!3 = !{!"clang version 18.1.0rc (https://github.com/llvm/llvm-project.git 1acc4e456481e76822c76c850bad3994d4e04b59)"}
*** IR Dump Before Prepare callbr (callbrprepare) ***
; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none)
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv4, %conv1
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv11, %conv7
  %add = add i32 %mul12, %acc
  %add13 = add i32 %add, %mul
  ret i32 %add13
}
*** IR Dump After Prepare callbr (callbrprepare) ***
; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none)
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv4, %conv1
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv11, %conv7
  %add = add i32 %mul12, %acc
  %add13 = add i32 %add, %mul
  ret i32 %add13
}
*** IR Dump Before Safe Stack instrumentation pass (safe-stack) ***
; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none)
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv4, %conv1
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv11, %conv7
  %add = add i32 %mul12, %acc
  %add13 = add i32 %add, %mul
  ret i32 %add13
}
[SafeStack] Function: test_macs32_v2i16
[SafeStack]     safestack is not requested for this function
*** IR Dump After Safe Stack instrumentation pass (safe-stack) ***
; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none)
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv4, %conv1
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv11, %conv7
  %add = add i32 %mul12, %acc
  %add13 = add i32 %add, %mul
  ret i32 %add13
}
*** IR Dump Before Module Verifier (verify) ***
; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none)
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv4, %conv1
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv11, %conv7
  %add = add i32 %mul12, %acc
  %add13 = add i32 %add, %mul
  ret i32 %add13
}
*** IR Dump After Module Verifier (verify) ***
; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none)
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv4, %conv1
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv11, %conv7
  %add = add i32 %mul12, %acc
  %add13 = add i32 %add, %mul
  ret i32 %add13
}
		Looking for trivial roots
Found a new trivial root: %entry
Last visited node: %entry
		Looking for non-trivial roots
Total: 1, Num: 2
Discovered CFG nodes:
0: nullptr
1: nullptr
2: %entry
Found roots: %entry 
---- Branch Probability Info : test_macs32_v2i16 ----

Computing probabilities for entry
# *** IR Dump Before IRTranslator (irtranslator) ***:
# Machine code for function test_macs32_v2i16: IsSSA, TracksLiveness

# End machine code for function test_macs32_v2i16.

Checking DILocation from   %sext = shl i32 %x, 16 was copied to G_CONSTANT
Checking DILocation from   %sext = shl i32 %x, 16 was copied to G_SHL
Checking DILocation from   %conv1 = ashr exact i32 %sext, 16 was copied to G_ASHR
Checking DILocation from   %sext18 = shl i32 %y, 16 was copied to G_SHL
Checking DILocation from   %conv4 = ashr exact i32 %sext18, 16 was copied to G_ASHR
Checking DILocation from   %mul = mul nsw i32 %conv4, %conv1 was copied to G_MUL
Checking DILocation from   %conv7 = ashr i32 %x, 16 was copied to G_ASHR
Checking DILocation from   %conv11 = ashr i32 %y, 16 was copied to G_ASHR
Checking DILocation from   %mul12 = mul nsw i32 %conv11, %conv7 was copied to G_MUL
Checking DILocation from   %add = add i32 %mul12, %acc was copied to G_ADD
Checking DILocation from   %add13 = add i32 %add, %mul was copied to G_ADD
Checking DILocation from   ret i32 %add13 was copied to COPY
Checking DILocation from   ret i32 %add13 was copied to PseudoRET implicit $x10
# *** IR Dump After IRTranslator (irtranslator) ***:
# Machine code for function test_macs32_v2i16: IsSSA, TracksLiveness
Function Live Ins: $x10, $x11, $x12

bb.1.entry:
  liveins: $x10, $x11, $x12
  %0:_(s32) = COPY $x10
  %1:_(s32) = COPY $x11
  %2:_(s32) = COPY $x12
  %3:_(s32) = G_CONSTANT i32 16
  %4:_(s32) = G_SHL %1:_, %3:_(s32)
  %5:_(s32) = exact G_ASHR %4:_, %3:_(s32)
  %6:_(s32) = G_SHL %2:_, %3:_(s32)
  %7:_(s32) = exact G_ASHR %6:_, %3:_(s32)
  %8:_(s32) = nsw G_MUL %7:_, %5:_
  %9:_(s32) = G_ASHR %1:_, %3:_(s32)
  %10:_(s32) = G_ASHR %2:_, %3:_(s32)
  %11:_(s32) = nsw G_MUL %10:_, %9:_
  %12:_(s32) = G_ADD %11:_, %0:_
  %13:_(s32) = G_ADD %12:_, %8:_
  $x10 = COPY %13:_(s32)
  PseudoRET implicit $x10

# End machine code for function test_macs32_v2i16.

# *** IR Dump Before RISCVPreLegalizerCombiner (riscv-prelegalizer-combiner) ***:
# Machine code for function test_macs32_v2i16: IsSSA, TracksLiveness
Function Live Ins: $x10, $x11, $x12

bb.1.entry:
  liveins: $x10, $x11, $x12
  %0:_(s32) = COPY $x10
  %1:_(s32) = COPY $x11
  %2:_(s32) = COPY $x12
  %3:_(s32) = G_CONSTANT i32 16
  %4:_(s32) = G_SHL %1:_, %3:_(s32)
  %5:_(s32) = exact G_ASHR %4:_, %3:_(s32)
  %6:_(s32) = G_SHL %2:_, %3:_(s32)
  %7:_(s32) = exact G_ASHR %6:_, %3:_(s32)
  %8:_(s32) = nsw G_MUL %7:_, %5:_
  %9:_(s32) = G_ASHR %1:_, %3:_(s32)
  %10:_(s32) = G_ASHR %2:_, %3:_(s32)
  %11:_(s32) = nsw G_MUL %10:_, %9:_
  %12:_(s32) = G_ADD %11:_, %0:_
  %13:_(s32) = G_ADD %12:_, %8:_
  $x10 = COPY %13:_(s32)
  PseudoRET implicit $x10

# End machine code for function test_macs32_v2i16.

Generic MI Combiner for: test_macs32_v2i16

Try combining %0:_(s32) = COPY $x10
10: GIM_SwitchOpcode(MIs[0], [19, 228), Default=5125, JumpTable...) // Got=19
847: Begin try-block
854: GIM_CheckSimplePredicate(Predicate=1)
858: GIM_CheckCxxPredicate(MIs[0], Predicate=1)
858: Rejected
862: Resume at 862 (1 try-blocks remain)
863: GIM_Reject
863: Rejected
5125: Resume at 5125 (0 try-blocks remain)
5126: GIM_Reject
5126: Rejected

Try combining %1:_(s32) = COPY $x11
10: GIM_SwitchOpcode(MIs[0], [19, 228), Default=5125, JumpTable...) // Got=19
847: Begin try-block
854: GIM_CheckSimplePredicate(Predicate=1)
858: GIM_CheckCxxPredicate(MIs[0], Predicate=1)
858: Rejected
862: Resume at 862 (1 try-blocks remain)
863: GIM_Reject
863: Rejected
5125: Resume at 5125 (0 try-blocks remain)
5126: GIM_Reject
5126: Rejected

Try combining %2:_(s32) = COPY $x12
10: GIM_SwitchOpcode(MIs[0], [19, 228), Default=5125, JumpTable...) // Got=19
847: Begin try-block
854: GIM_CheckSimplePredicate(Predicate=1)
858: GIM_CheckCxxPredicate(MIs[0], Predicate=1)
858: Rejected
862: Resume at 862 (1 try-blocks remain)
863: GIM_Reject
863: Rejected
5125: Resume at 5125 (0 try-blocks remain)
5126: GIM_Reject
5126: Rejected

Try combining %3:_(s32) = G_CONSTANT i32 16
10: GIM_SwitchOpcode(MIs[0], [19, 228), Default=5125, JumpTable...) // Got=120
5126: GIM_Reject
5126: Rejected

Try combining %4:_(s32) = G_SHL %1:_, %3:_(s32)
10: GIM_SwitchOpcode(MIs[0], [19, 228), Default=5125, JumpTable...) // Got=127
2736: Begin try-block
2743: GIM_CheckSimplePredicate(Predicate=15)
2747: GIM_CheckCxxPredicate(MIs[0], Predicate=11)
2747: Rejected
2751: Resume at 2751 (1 try-blocks remain)
2752: Begin try-block
2759: GIM_CheckSimplePredicate(Predicate=16)
2763: GIM_CheckCxxPredicate(MIs[0], Predicate=12)
2763: Rejected
2767: Resume at 2767 (1 try-blocks remain)
2768: Begin try-block
2775: GIM_CheckSimplePredicate(Predicate=45)
2779: GIM_CheckCxxPredicate(MIs[0], Predicate=32)
2779: Rejected
2783: Resume at 2783 (1 try-blocks remain)
2784: Begin try-block
2791: GIM_CheckSimplePredicate(Predicate=90)
2795: GIM_CheckCxxPredicate(MIs[0], Predicate=69)
2795: Rejected
2799: Resume at 2799 (1 try-blocks remain)
2800: Begin try-block
2807: GIM_CheckSimplePredicate(Predicate=91)
2811: GIM_CheckCxxPredicate(MIs[0], Predicate=70)
2811: Rejected
2815: Resume at 2815 (1 try-blocks remain)
2816: Begin try-block
2823: GIM_CheckSimplePredicate(Predicate=99)
2827: GIM_CheckCxxPredicate(MIs[0], Predicate=76)
2827: Rejected
2831: Resume at 2831 (1 try-blocks remain)
2832: Begin try-block
2839: GIM_CheckSimplePredicate(Predicate=104)
2843: GIM_CheckCxxPredicate(MIs[0], Predicate=81)
2843: Rejected
2847: Resume at 2847 (1 try-blocks remain)
2848: Begin try-block
2855: GIM_CheckSimplePredicate(Predicate=122)
2859: GIM_CheckCxxPredicate(MIs[0], Predicate=98)
2859: Rejected
2863: Resume at 2863 (1 try-blocks remain)
2864: Begin try-block
2871: GIM_CheckSimplePredicate(Predicate=25)
2875: GIM_CheckConstantInt(MIs[0]->getOperand(2), Value=0)
2875: Rejected
2888: Resume at 2888 (1 try-blocks remain)
2889: Begin try-block
2896: GIM_CheckSimplePredicate(Predicate=51)
2900: GIM_CheckCxxPredicate(MIs[0], Predicate=38)
2900: Rejected
2904: Resume at 2904 (1 try-blocks remain)
2905: GIM_Reject
2905: Rejected
5125: Resume at 5125 (0 try-blocks remain)
5126: GIM_Reject
5126: Rejected

Try combining %5:_(s32) = exact G_ASHR %4:_, %3:_(s32)
10: GIM_SwitchOpcode(MIs[0], [19, 228), Default=5125, JumpTable...) // Got=129
3060: Begin try-block
3067: GIM_CheckSimplePredicate(Predicate=16)
3071: GIM_CheckCxxPredicate(MIs[0], Predicate=12)
3071: Rejected
3075: Resume at 3075 (1 try-blocks remain)
3076: Begin try-block
3083: GIM_CheckSimplePredicate(Predicate=45)
3087: GIM_CheckCxxPredicate(MIs[0], Predicate=32)
3087: Rejected
3091: Resume at 3091 (1 try-blocks remain)
3092: Begin try-block
3099: GIM_CheckSimplePredicate(Predicate=49)
3103: GIM_CheckCxxPredicate(MIs[0], Predicate=36)
3106: GIR_CustomAction(FnID=25)
Creating: G_SEXT_INREG

Creating: G_SEXT_INREG

Erasing: %5:_(s32) = exact G_ASHR %4:_, %3:_(s32)

3107: GIR_Done
Created: %5:_(s32) = G_SEXT_INREG %1:_, 16

Try combining %5:_(s32) = G_SEXT_INREG %1:_, 16
10: GIM_SwitchOpcode(MIs[0], [19, 228), Default=5125, JumpTable...) // Got=125
2622: Begin try-block
2629: GIM_CheckSimplePredicate(Predicate=50)
2633: GIM_CheckCxxPredicate(MIs[0], Predicate=37)
2633: Rejected
2637: Resume at 2637 (1 try-blocks remain)
2638: Begin try-block
2645: GIM_CheckSimplePredicate(Predicate=57)
2649: GIM_CheckCxxPredicate(MIs[0], Predicate=43)
2649: Rejected
2653: Resume at 2653 (1 try-blocks remain)
2654: Begin try-block
2661: GIM_CheckSimplePredicate(Predicate=100)
2665: GIM_CheckCxxPredicate(MIs[0], Predicate=77)
Applying legalizer ruleset to: Opcode=269, Tys={s32, s32, }, MMOs={}
.. fallback to legacy rules (no rules defined)
.. (legacy) Type 0 Action=NotFound, LLT_invalid
2665: Rejected
2669: Resume at 2669 (1 try-blocks remain)
2670: Begin try-block
2677: GIM_CheckSimplePredicate(Predicate=63)
2681: GIM_CheckCxxPredicate(MIs[0], Predicate=49)
[0] Compute known bits: %1:_(s32) = COPY $x11
[0] Computed for: %1:_(s32) = COPY $x11
[0] Known: 0x0
[0] Zero: 0x0
[0] One:  0x0
2681: Rejected
2685: Resume at 2685 (1 try-blocks remain)
2686: GIM_Reject
2686: Rejected
5125: Resume at 5125 (0 try-blocks remain)
5126: GIM_Reject
5126: Rejected

Try combining %6:_(s32) = G_SHL %2:_, %3:_(s32)
10: GIM_SwitchOpcode(MIs[0], [19, 228), Default=5125, JumpTable...) // Got=127
2736: Begin try-block
2743: GIM_CheckSimplePredicate(Predicate=15)
2747: GIM_CheckCxxPredicate(MIs[0], Predicate=11)
2747: Rejected
2751: Resume at 2751 (1 try-blocks remain)
2752: Begin try-block
2759: GIM_CheckSimplePredicate(Predicate=16)
2763: GIM_CheckCxxPredicate(MIs[0], Predicate=12)
2763: Rejected
2767: Resume at 2767 (1 try-blocks remain)
2768: Begin try-block
2775: GIM_CheckSimplePredicate(Predicate=45)
2779: GIM_CheckCxxPredicate(MIs[0], Predicate=32)
2779: Rejected
2783: Resume at 2783 (1 try-blocks remain)
2784: Begin try-block
2791: GIM_CheckSimplePredicate(Predicate=90)
2795: GIM_CheckCxxPredicate(MIs[0], Predicate=69)
2795: Rejected
2799: Resume at 2799 (1 try-blocks remain)
2800: Begin try-block
2807: GIM_CheckSimplePredicate(Predicate=91)
2811: GIM_CheckCxxPredicate(MIs[0], Predicate=70)
2811: Rejected
2815: Resume at 2815 (1 try-blocks remain)
2816: Begin try-block
2823: GIM_CheckSimplePredicate(Predicate=99)
2827: GIM_CheckCxxPredicate(MIs[0], Predicate=76)
2827: Rejected
2831: Resume at 2831 (1 try-blocks remain)
2832: Begin try-block
2839: GIM_CheckSimplePredicate(Predicate=104)
2843: GIM_CheckCxxPredicate(MIs[0], Predicate=81)
2843: Rejected
2847: Resume at 2847 (1 try-blocks remain)
2848: Begin try-block
2855: GIM_CheckSimplePredicate(Predicate=122)
2859: GIM_CheckCxxPredicate(MIs[0], Predicate=98)
2859: Rejected
2863: Resume at 2863 (1 try-blocks remain)
2864: Begin try-block
2871: GIM_CheckSimplePredicate(Predicate=25)
2875: GIM_CheckConstantInt(MIs[0]->getOperand(2), Value=0)
2875: Rejected
2888: Resume at 2888 (1 try-blocks remain)
2889: Begin try-block
2896: GIM_CheckSimplePredicate(Predicate=51)
2900: GIM_CheckCxxPredicate(MIs[0], Predicate=38)
2900: Rejected
2904: Resume at 2904 (1 try-blocks remain)
2905: GIM_Reject
2905: Rejected
5125: Resume at 5125 (0 try-blocks remain)
5126: GIM_Reject
5126: Rejected

Try combining %7:_(s32) = exact G_ASHR %6:_, %3:_(s32)
10: GIM_SwitchOpcode(MIs[0], [19, 228), Default=5125, JumpTable...) // Got=129
3060: Begin try-block
3067: GIM_CheckSimplePredicate(Predicate=16)
3071: GIM_CheckCxxPredicate(MIs[0], Predicate=12)
3071: Rejected
3075: Resume at 3075 (1 try-blocks remain)
3076: Begin try-block
3083: GIM_CheckSimplePredicate(Predicate=45)
3087: GIM_CheckCxxPredicate(MIs[0], Predicate=32)
3087: Rejected
3091: Resume at 3091 (1 try-blocks remain)
3092: Begin try-block
3099: GIM_CheckSimplePredicate(Predicate=49)
3103: GIM_CheckCxxPredicate(MIs[0], Predicate=36)
3106: GIR_CustomAction(FnID=25)
Creating: G_SEXT_INREG

Creating: G_SEXT_INREG

Erasing: %7:_(s32) = exact G_ASHR %6:_, %3:_(s32)

3107: GIR_Done
Created: %7:_(s32) = G_SEXT_INREG %2:_, 16

Try combining %7:_(s32) = G_SEXT_INREG %2:_, 16
10: GIM_SwitchOpcode(MIs[0], [19, 228), Default=5125, JumpTable...) // Got=125
2622: Begin try-block
2629: GIM_CheckSimplePredicate(Predicate=50)
2633: GIM_CheckCxxPredicate(MIs[0], Predicate=37)
2633: Rejected
2637: Resume at 2637 (1 try-blocks remain)
2638: Begin try-block
2645: GIM_CheckSimplePredicate(Predicate=57)
2649: GIM_CheckCxxPredicate(MIs[0], Predicate=43)
2649: Rejected
2653: Resume at 2653 (1 try-blocks remain)
2654: Begin try-block
2661: GIM_CheckSimplePredicate(Predicate=100)
2665: GIM_CheckCxxPredicate(MIs[0], Predicate=77)
Applying legalizer ruleset to: Opcode=269, Tys={s32, s32, }, MMOs={}
.. fallback to legacy rules (no rules defined)
.. (legacy) Type 0 Action=NotFound, LLT_invalid
2665: Rejected
2669: Resume at 2669 (1 try-blocks remain)
2670: Begin try-block
2677: GIM_CheckSimplePredicate(Predicate=63)
2681: GIM_CheckCxxPredicate(MIs[0], Predicate=49)
[0] Compute known bits: %2:_(s32) = COPY $x12
[0] Computed for: %2:_(s32) = COPY $x12
[0] Known: 0x0
[0] Zero: 0x0
[0] One:  0x0
2681: Rejected
2685: Resume at 2685 (1 try-blocks remain)
2686: GIM_Reject
2686: Rejected
5125: Resume at 5125 (0 try-blocks remain)
5126: GIM_Reject
5126: Rejected

Try combining %8:_(s32) = nsw G_MUL %7:_, %5:_
10: GIM_SwitchOpcode(MIs[0], [19, 228), Default=5125, JumpTable...) // Got=49
1164: Begin try-block
1171: GIM_CheckSimplePredicate(Predicate=13)
1175: GIM_CheckCxxPredicate(MIs[0], Predicate=10)
1175: Rejected
1179: Resume at 1179 (1 try-blocks remain)
1180: Begin try-block
1187: GIM_CheckSimplePredicate(Predicate=104)
1191: GIM_CheckCxxPredicate(MIs[0], Predicate=81)
1191: Rejected
1195: Resume at 1195 (1 try-blocks remain)
1196: Begin try-block
1203: GIM_CheckSimplePredicate(Predicate=127)
1207: GIM_CheckCxxPredicate(MIs[0], Predicate=103)
1207: Rejected
1211: Resume at 1211 (1 try-blocks remain)
1212: Begin try-block
1219: GIM_CheckSimplePredicate(Predicate=4)
1223: GIM_RecordRegType(MIs[0]->getOperand(0), TypeIdx=-1)
1227: GIM_CheckConstantInt(MIs[0]->getOperand(2), Value=18446744073709551615)
1227: Rejected
1258: Resume at 1258 (1 try-blocks remain)
1259: Begin try-block
1266: GIM_CheckSimplePredicate(Predicate=28)
1270: GIM_CheckConstantInt(MIs[0]->getOperand(2), Value=0)
1270: Rejected
1283: Resume at 1283 (1 try-blocks remain)
1284: Begin try-block
1291: GIM_CheckSimplePredicate(Predicate=33)
1295: GIM_CheckConstantInt(MIs[0]->getOperand(2), Value=1)
1295: Rejected
1308: Resume at 1308 (1 try-blocks remain)
1309: Begin try-block
1316: GIM_CheckSimplePredicate(Predicate=2)
1320: GIM_CheckCxxPredicate(MIs[0], Predicate=2)
1320: Rejected
1324: Resume at 1324 (1 try-blocks remain)
1325: GIM_Reject
1325: Rejected
5125: Resume at 5125 (0 try-blocks remain)
5126: GIM_Reject
5126: Rejected

Try combining %9:_(s32) = G_ASHR %1:_, %3:_(s32)
10: GIM_SwitchOpcode(MIs[0], [19, 228), Default=5125, JumpTable...) // Got=129
3060: Begin try-block
3067: GIM_CheckSimplePredicate(Predicate=16)
3071: GIM_CheckCxxPredicate(MIs[0], Predicate=12)
3071: Rejected
3075: Resume at 3075 (1 try-blocks remain)
3076: Begin try-block
3083: GIM_CheckSimplePredicate(Predicate=45)
3087: GIM_CheckCxxPredicate(MIs[0], Predicate=32)
3087: Rejected
3091: Resume at 3091 (1 try-blocks remain)
3092: Begin try-block
3099: GIM_CheckSimplePredicate(Predicate=49)
3103: GIM_CheckCxxPredicate(MIs[0], Predicate=36)
3103: Rejected
3107: Resume at 3107 (1 try-blocks remain)
3108: Begin try-block
3115: GIM_CheckSimplePredicate(Predicate=90)
3119: GIM_CheckCxxPredicate(MIs[0], Predicate=69)
3119: Rejected
3123: Resume at 3123 (1 try-blocks remain)
3124: Begin try-block
3131: GIM_CheckSimplePredicate(Predicate=91)
3135: GIM_CheckCxxPredicate(MIs[0], Predicate=70)
3135: Rejected
3139: Resume at 3139 (1 try-blocks remain)
3140: Begin try-block
3147: GIM_CheckSimplePredicate(Predicate=102)
3151: GIM_CheckCxxPredicate(MIs[0], Predicate=79)
Applying legalizer ruleset to: Opcode=269, Tys={s32, s32, }, MMOs={}
.. fallback to legacy rules (no rules defined)
.. (legacy) Type 0 Action=NotFound, LLT_invalid
3151: Rejected
3155: Resume at 3155 (1 try-blocks remain)
3156: Begin try-block
3163: GIM_CheckSimplePredicate(Predicate=103)
3167: GIM_CheckCxxPredicate(MIs[0], Predicate=80)
Applying legalizer ruleset to: Opcode=270, Tys={s32, s32, }, MMOs={}
.. fallback to legacy rules (no rules defined)
.. (legacy) Type 0 Action=NotFound, LLT_invalid
3167: Rejected
3171: Resume at 3171 (1 try-blocks remain)
3172: Begin try-block
3179: GIM_CheckSimplePredicate(Predicate=104)
3183: GIM_CheckCxxPredicate(MIs[0], Predicate=81)
3183: Rejected
3187: Resume at 3187 (1 try-blocks remain)
3188: Begin try-block
3195: GIM_CheckSimplePredicate(Predicate=122)
3199: GIM_CheckCxxPredicate(MIs[0], Predicate=98)
3199: Rejected
3203: Resume at 3203 (1 try-blocks remain)
3204: Begin try-block
3211: GIM_CheckSimplePredicate(Predicate=25)
3215: GIM_CheckConstantInt(MIs[0]->getOperand(2), Value=0)
3215: Rejected
3228: Resume at 3228 (1 try-blocks remain)
3229: GIM_Reject
3229: Rejected
5125: Resume at 5125 (0 try-blocks remain)
5126: GIM_Reject
5126: Rejected

Try combining %10:_(s32) = G_ASHR %2:_, %3:_(s32)
10: GIM_SwitchOpcode(MIs[0], [19, 228), Default=5125, JumpTable...) // Got=129
3060: Begin try-block
3067: GIM_CheckSimplePredicate(Predicate=16)
3071: GIM_CheckCxxPredicate(MIs[0], Predicate=12)
3071: Rejected
3075: Resume at 3075 (1 try-blocks remain)
3076: Begin try-block
3083: GIM_CheckSimplePredicate(Predicate=45)
3087: GIM_CheckCxxPredicate(MIs[0], Predicate=32)
3087: Rejected
3091: Resume at 3091 (1 try-blocks remain)
3092: Begin try-block
3099: GIM_CheckSimplePredicate(Predicate=49)
3103: GIM_CheckCxxPredicate(MIs[0], Predicate=36)
3103: Rejected
3107: Resume at 3107 (1 try-blocks remain)
3108: Begin try-block
3115: GIM_CheckSimplePredicate(Predicate=90)
3119: GIM_CheckCxxPredicate(MIs[0], Predicate=69)
3119: Rejected
3123: Resume at 3123 (1 try-blocks remain)
3124: Begin try-block
3131: GIM_CheckSimplePredicate(Predicate=91)
3135: GIM_CheckCxxPredicate(MIs[0], Predicate=70)
3135: Rejected
3139: Resume at 3139 (1 try-blocks remain)
3140: Begin try-block
3147: GIM_CheckSimplePredicate(Predicate=102)
3151: GIM_CheckCxxPredicate(MIs[0], Predicate=79)
Applying legalizer ruleset to: Opcode=269, Tys={s32, s32, }, MMOs={}
.. fallback to legacy rules (no rules defined)
.. (legacy) Type 0 Action=NotFound, LLT_invalid
3151: Rejected
3155: Resume at 3155 (1 try-blocks remain)
3156: Begin try-block
3163: GIM_CheckSimplePredicate(Predicate=103)
3167: GIM_CheckCxxPredicate(MIs[0], Predicate=80)
Applying legalizer ruleset to: Opcode=270, Tys={s32, s32, }, MMOs={}
.. fallback to legacy rules (no rules defined)
.. (legacy) Type 0 Action=NotFound, LLT_invalid
3167: Rejected
3171: Resume at 3171 (1 try-blocks remain)
3172: Begin try-block
3179: GIM_CheckSimplePredicate(Predicate=104)
3183: GIM_CheckCxxPredicate(MIs[0], Predicate=81)
3183: Rejected
3187: Resume at 3187 (1 try-blocks remain)
3188: Begin try-block
3195: GIM_CheckSimplePredicate(Predicate=122)
3199: GIM_CheckCxxPredicate(MIs[0], Predicate=98)
3199: Rejected
3203: Resume at 3203 (1 try-blocks remain)
3204: Begin try-block
3211: GIM_CheckSimplePredicate(Predicate=25)
3215: GIM_CheckConstantInt(MIs[0]->getOperand(2), Value=0)
3215: Rejected
3228: Resume at 3228 (1 try-blocks remain)
3229: GIM_Reject
3229: Rejected
5125: Resume at 5125 (0 try-blocks remain)
5126: GIM_Reject
5126: Rejected

Try combining %11:_(s32) = nsw G_MUL %10:_, %9:_
10: GIM_SwitchOpcode(MIs[0], [19, 228), Default=5125, JumpTable...) // Got=49
1164: Begin try-block
1171: GIM_CheckSimplePredicate(Predicate=13)
1175: GIM_CheckCxxPredicate(MIs[0], Predicate=10)
1175: Rejected
1179: Resume at 1179 (1 try-blocks remain)
1180: Begin try-block
1187: GIM_CheckSimplePredicate(Predicate=104)
1191: GIM_CheckCxxPredicate(MIs[0], Predicate=81)
1191: Rejected
1195: Resume at 1195 (1 try-blocks remain)
1196: Begin try-block
1203: GIM_CheckSimplePredicate(Predicate=127)
1207: GIM_CheckCxxPredicate(MIs[0], Predicate=103)
1207: Rejected
1211: Resume at 1211 (1 try-blocks remain)
1212: Begin try-block
1219: GIM_CheckSimplePredicate(Predicate=4)
1223: GIM_RecordRegType(MIs[0]->getOperand(0), TypeIdx=-1)
1227: GIM_CheckConstantInt(MIs[0]->getOperand(2), Value=18446744073709551615)
1227: Rejected
1258: Resume at 1258 (1 try-blocks remain)
1259: Begin try-block
1266: GIM_CheckSimplePredicate(Predicate=28)
1270: GIM_CheckConstantInt(MIs[0]->getOperand(2), Value=0)
1270: Rejected
1283: Resume at 1283 (1 try-blocks remain)
1284: Begin try-block
1291: GIM_CheckSimplePredicate(Predicate=33)
1295: GIM_CheckConstantInt(MIs[0]->getOperand(2), Value=1)
1295: Rejected
1308: Resume at 1308 (1 try-blocks remain)
1309: Begin try-block
1316: GIM_CheckSimplePredicate(Predicate=2)
1320: GIM_CheckCxxPredicate(MIs[0], Predicate=2)
1320: Rejected
1324: Resume at 1324 (1 try-blocks remain)
1325: GIM_Reject
1325: Rejected
5125: Resume at 5125 (0 try-blocks remain)
5126: GIM_Reject
5126: Rejected

Try combining %12:_(s32) = G_ADD %11:_, %0:_
10: GIM_SwitchOpcode(MIs[0], [19, 228), Default=5125, JumpTable...) // Got=47
864: Begin try-block
871: GIM_CheckSimplePredicate(Predicate=3)
875: GIM_CheckCxxPredicate(MIs[0], Predicate=3)
875: Rejected
879: Resume at 879 (1 try-blocks remain)
880: Begin try-block
887: GIM_CheckSimplePredicate(Predicate=18)
891: GIM_CheckCxxPredicate(MIs[0], Predicate=10)
891: Rejected
895: Resume at 895 (1 try-blocks remain)
896: Begin try-block
903: GIM_CheckSimplePredicate(Predicate=43)
907: GIM_CheckCxxPredicate(MIs[0], Predicate=30)
907: Rejected
911: Resume at 911 (1 try-blocks remain)
912: Begin try-block
919: GIM_CheckSimplePredicate(Predicate=104)
923: GIM_CheckCxxPredicate(MIs[0], Predicate=81)
923: Rejected
927: Resume at 927 (1 try-blocks remain)
928: Begin try-block
935: GIM_CheckSimplePredicate(Predicate=122)
939: GIM_CheckCxxPredicate(MIs[0], Predicate=98)
939: Rejected
943: Resume at 943 (1 try-blocks remain)
944: Begin try-block
951: GIM_CheckSimplePredicate(Predicate=127)
955: GIM_CheckCxxPredicate(MIs[0], Predicate=103)
955: Rejected
959: Resume at 959 (1 try-blocks remain)
960: Begin try-block
967: GIM_CheckSimplePredicate(Predicate=35)
971: MIs[1] = GIM_RecordInsn(0, 1)
975: GIM_CheckOpcode(MIs[1], ExpectedOpcode=48) // Got=49
975: Rejected
995: Resume at 995 (1 try-blocks remain)
996: Begin try-block
1003: GIM_CheckSimplePredicate(Predicate=35)
1007: MIs[1] = GIM_RecordInsn(0, 2)
1011: GIM_CheckOpcode(MIs[1], ExpectedOpcode=48) // Got=19
1011: Rejected
1031: Resume at 1031 (1 try-blocks remain)
1032: Begin try-block
1039: GIM_CheckSimplePredicate(Predicate=25)
1043: GIM_CheckConstantInt(MIs[0]->getOperand(2), Value=0)
1043: Rejected
1056: Resume at 1056 (1 try-blocks remain)
1057: Begin try-block
1064: GIM_CheckSimplePredicate(Predicate=47)
1068: GIM_CheckCxxPredicate(MIs[0], Predicate=34)
1068: Rejected
1072: Resume at 1072 (1 try-blocks remain)
1073: GIM_Reject
1073: Rejected
5125: Resume at 5125 (0 try-blocks remain)
5126: GIM_Reject
5126: Rejected

Try combining %13:_(s32) = G_ADD %12:_, %8:_
10: GIM_SwitchOpcode(MIs[0], [19, 228), Default=5125, JumpTable...) // Got=47
864: Begin try-block
871: GIM_CheckSimplePredicate(Predicate=3)
875: GIM_CheckCxxPredicate(MIs[0], Predicate=3)
875: Rejected
879: Resume at 879 (1 try-blocks remain)
880: Begin try-block
887: GIM_CheckSimplePredicate(Predicate=18)
891: GIM_CheckCxxPredicate(MIs[0], Predicate=10)
891: Rejected
895: Resume at 895 (1 try-blocks remain)
896: Begin try-block
903: GIM_CheckSimplePredicate(Predicate=43)
907: GIM_CheckCxxPredicate(MIs[0], Predicate=30)
907: Rejected
911: Resume at 911 (1 try-blocks remain)
912: Begin try-block
919: GIM_CheckSimplePredicate(Predicate=104)
923: GIM_CheckCxxPredicate(MIs[0], Predicate=81)
923: Rejected
927: Resume at 927 (1 try-blocks remain)
928: Begin try-block
935: GIM_CheckSimplePredicate(Predicate=122)
939: GIM_CheckCxxPredicate(MIs[0], Predicate=98)
939: Rejected
943: Resume at 943 (1 try-blocks remain)
944: Begin try-block
951: GIM_CheckSimplePredicate(Predicate=127)
955: GIM_CheckCxxPredicate(MIs[0], Predicate=103)
955: Rejected
959: Resume at 959 (1 try-blocks remain)
960: Begin try-block
967: GIM_CheckSimplePredicate(Predicate=35)
971: MIs[1] = GIM_RecordInsn(0, 1)
975: GIM_CheckOpcode(MIs[1], ExpectedOpcode=48) // Got=47
975: Rejected
995: Resume at 995 (1 try-blocks remain)
996: Begin try-block
1003: GIM_CheckSimplePredicate(Predicate=35)
1007: MIs[1] = GIM_RecordInsn(0, 2)
1011: GIM_CheckOpcode(MIs[1], ExpectedOpcode=48) // Got=49
1011: Rejected
1031: Resume at 1031 (1 try-blocks remain)
1032: Begin try-block
1039: GIM_CheckSimplePredicate(Predicate=25)
1043: GIM_CheckConstantInt(MIs[0]->getOperand(2), Value=0)
1043: Rejected
1056: Resume at 1056 (1 try-blocks remain)
1057: Begin try-block
1064: GIM_CheckSimplePredicate(Predicate=47)
1068: GIM_CheckCxxPredicate(MIs[0], Predicate=34)
1068: Rejected
1072: Resume at 1072 (1 try-blocks remain)
1073: GIM_Reject
1073: Rejected
5125: Resume at 5125 (0 try-blocks remain)
5126: GIM_Reject
5126: Rejected

Try combining $x10 = COPY %13:_(s32)
10: GIM_SwitchOpcode(MIs[0], [19, 228), Default=5125, JumpTable...) // Got=19
847: Begin try-block
854: GIM_CheckSimplePredicate(Predicate=1)
858: GIM_CheckCxxPredicate(MIs[0], Predicate=1)
858: Rejected
862: Resume at 862 (1 try-blocks remain)
863: GIM_Reject
863: Rejected
5125: Resume at 5125 (0 try-blocks remain)
5126: GIM_Reject
5126: Rejected

Try combining PseudoRET implicit $x10
10: GIM_SwitchOpcode(MIs[0], [19, 228), Default=5125, JumpTable...) // Got=377
5126: GIM_Reject
5126: Rejected
%6:_(s32) = G_SHL %2:_, %3:_(s32)
Is dead; erasing.
Erasing: %6:_(s32) = G_SHL %2:_, %3:_(s32)

%4:_(s32) = G_SHL %1:_, %3:_(s32)
Is dead; erasing.
Erasing: %4:_(s32) = G_SHL %1:_, %3:_(s32)


Try combining %0:_(s32) = COPY $x10
10: GIM_SwitchOpcode(MIs[0], [19, 228), Default=5125, JumpTable...) // Got=19
847: Begin try-block
854: GIM_CheckSimplePredicate(Predicate=1)
858: GIM_CheckCxxPredicate(MIs[0], Predicate=1)
858: Rejected
862: Resume at 862 (1 try-blocks remain)
863: GIM_Reject
863: Rejected
5125: Resume at 5125 (0 try-blocks remain)
5126: GIM_Reject
5126: Rejected

Try combining %1:_(s32) = COPY $x11
10: GIM_SwitchOpcode(MIs[0], [19, 228), Default=5125, JumpTable...) // Got=19
847: Begin try-block
854: GIM_CheckSimplePredicate(Predicate=1)
858: GIM_CheckCxxPredicate(MIs[0], Predicate=1)
858: Rejected
862: Resume at 862 (1 try-blocks remain)
863: GIM_Reject
863: Rejected
5125: Resume at 5125 (0 try-blocks remain)
5126: GIM_Reject
5126: Rejected

Try combining %2:_(s32) = COPY $x12
10: GIM_SwitchOpcode(MIs[0], [19, 228), Default=5125, JumpTable...) // Got=19
847: Begin try-block
854: GIM_CheckSimplePredicate(Predicate=1)
858: GIM_CheckCxxPredicate(MIs[0], Predicate=1)
858: Rejected
862: Resume at 862 (1 try-blocks remain)
863: GIM_Reject
863: Rejected
5125: Resume at 5125 (0 try-blocks remain)
5126: GIM_Reject
5126: Rejected

Try combining %3:_(s32) = G_CONSTANT i32 16
10: GIM_SwitchOpcode(MIs[0], [19, 228), Default=5125, JumpTable...) // Got=120
5126: GIM_Reject
5126: Rejected

Try combining %5:_(s32) = G_SEXT_INREG %1:_, 16
10: GIM_SwitchOpcode(MIs[0], [19, 228), Default=5125, JumpTable...) // Got=125
2622: Begin try-block
2629: GIM_CheckSimplePredicate(Predicate=50)
2633: GIM_CheckCxxPredicate(MIs[0], Predicate=37)
2633: Rejected
2637: Resume at 2637 (1 try-blocks remain)
2638: Begin try-block
2645: GIM_CheckSimplePredicate(Predicate=57)
2649: GIM_CheckCxxPredicate(MIs[0], Predicate=43)
2649: Rejected
2653: Resume at 2653 (1 try-blocks remain)
2654: Begin try-block
2661: GIM_CheckSimplePredicate(Predicate=100)
2665: GIM_CheckCxxPredicate(MIs[0], Predicate=77)
Applying legalizer ruleset to: Opcode=269, Tys={s32, s32, }, MMOs={}
.. fallback to legacy rules (no rules defined)
.. (legacy) Type 0 Action=NotFound, LLT_invalid
2665: Rejected
2669: Resume at 2669 (1 try-blocks remain)
2670: Begin try-block
2677: GIM_CheckSimplePredicate(Predicate=63)
2681: GIM_CheckCxxPredicate(MIs[0], Predicate=49)
[0] Compute known bits: %1:_(s32) = COPY $x11
[0] Computed for: %1:_(s32) = COPY $x11
[0] Known: 0x0
[0] Zero: 0x0
[0] One:  0x0
2681: Rejected
2685: Resume at 2685 (1 try-blocks remain)
2686: GIM_Reject
2686: Rejected
5125: Resume at 5125 (0 try-blocks remain)
5126: GIM_Reject
5126: Rejected

Try combining %7:_(s32) = G_SEXT_INREG %2:_, 16
10: GIM_SwitchOpcode(MIs[0], [19, 228), Default=5125, JumpTable...) // Got=125
2622: Begin try-block
2629: GIM_CheckSimplePredicate(Predicate=50)
2633: GIM_CheckCxxPredicate(MIs[0], Predicate=37)
2633: Rejected
2637: Resume at 2637 (1 try-blocks remain)
2638: Begin try-block
2645: GIM_CheckSimplePredicate(Predicate=57)
2649: GIM_CheckCxxPredicate(MIs[0], Predicate=43)
2649: Rejected
2653: Resume at 2653 (1 try-blocks remain)
2654: Begin try-block
2661: GIM_CheckSimplePredicate(Predicate=100)
2665: GIM_CheckCxxPredicate(MIs[0], Predicate=77)
Applying legalizer ruleset to: Opcode=269, Tys={s32, s32, }, MMOs={}
.. fallback to legacy rules (no rules defined)
.. (legacy) Type 0 Action=NotFound, LLT_invalid
2665: Rejected
2669: Resume at 2669 (1 try-blocks remain)
2670: Begin try-block
2677: GIM_CheckSimplePredicate(Predicate=63)
2681: GIM_CheckCxxPredicate(MIs[0], Predicate=49)
[0] Compute known bits: %2:_(s32) = COPY $x12
[0] Computed for: %2:_(s32) = COPY $x12
[0] Known: 0x0
[0] Zero: 0x0
[0] One:  0x0
2681: Rejected
2685: Resume at 2685 (1 try-blocks remain)
2686: GIM_Reject
2686: Rejected
5125: Resume at 5125 (0 try-blocks remain)
5126: GIM_Reject
5126: Rejected

Try combining %8:_(s32) = nsw G_MUL %7:_, %5:_
10: GIM_SwitchOpcode(MIs[0], [19, 228), Default=5125, JumpTable...) // Got=49
1164: Begin try-block
1171: GIM_CheckSimplePredicate(Predicate=13)
1175: GIM_CheckCxxPredicate(MIs[0], Predicate=10)
1175: Rejected
1179: Resume at 1179 (1 try-blocks remain)
1180: Begin try-block
1187: GIM_CheckSimplePredicate(Predicate=104)
1191: GIM_CheckCxxPredicate(MIs[0], Predicate=81)
1191: Rejected
1195: Resume at 1195 (1 try-blocks remain)
1196: Begin try-block
1203: GIM_CheckSimplePredicate(Predicate=127)
1207: GIM_CheckCxxPredicate(MIs[0], Predicate=103)
1207: Rejected
1211: Resume at 1211 (1 try-blocks remain)
1212: Begin try-block
1219: GIM_CheckSimplePredicate(Predicate=4)
1223: GIM_RecordRegType(MIs[0]->getOperand(0), TypeIdx=-1)
1227: GIM_CheckConstantInt(MIs[0]->getOperand(2), Value=18446744073709551615)
1227: Rejected
1258: Resume at 1258 (1 try-blocks remain)
1259: Begin try-block
1266: GIM_CheckSimplePredicate(Predicate=28)
1270: GIM_CheckConstantInt(MIs[0]->getOperand(2), Value=0)
1270: Rejected
1283: Resume at 1283 (1 try-blocks remain)
1284: Begin try-block
1291: GIM_CheckSimplePredicate(Predicate=33)
1295: GIM_CheckConstantInt(MIs[0]->getOperand(2), Value=1)
1295: Rejected
1308: Resume at 1308 (1 try-blocks remain)
1309: Begin try-block
1316: GIM_CheckSimplePredicate(Predicate=2)
1320: GIM_CheckCxxPredicate(MIs[0], Predicate=2)
1320: Rejected
1324: Resume at 1324 (1 try-blocks remain)
1325: GIM_Reject
1325: Rejected
5125: Resume at 5125 (0 try-blocks remain)
5126: GIM_Reject
5126: Rejected

Try combining %9:_(s32) = G_ASHR %1:_, %3:_(s32)
10: GIM_SwitchOpcode(MIs[0], [19, 228), Default=5125, JumpTable...) // Got=129
3060: Begin try-block
3067: GIM_CheckSimplePredicate(Predicate=16)
3071: GIM_CheckCxxPredicate(MIs[0], Predicate=12)
3071: Rejected
3075: Resume at 3075 (1 try-blocks remain)
3076: Begin try-block
3083: GIM_CheckSimplePredicate(Predicate=45)
3087: GIM_CheckCxxPredicate(MIs[0], Predicate=32)
3087: Rejected
3091: Resume at 3091 (1 try-blocks remain)
3092: Begin try-block
3099: GIM_CheckSimplePredicate(Predicate=49)
3103: GIM_CheckCxxPredicate(MIs[0], Predicate=36)
3103: Rejected
3107: Resume at 3107 (1 try-blocks remain)
3108: Begin try-block
3115: GIM_CheckSimplePredicate(Predicate=90)
3119: GIM_CheckCxxPredicate(MIs[0], Predicate=69)
3119: Rejected
3123: Resume at 3123 (1 try-blocks remain)
3124: Begin try-block
3131: GIM_CheckSimplePredicate(Predicate=91)
3135: GIM_CheckCxxPredicate(MIs[0], Predicate=70)
3135: Rejected
3139: Resume at 3139 (1 try-blocks remain)
3140: Begin try-block
3147: GIM_CheckSimplePredicate(Predicate=102)
3151: GIM_CheckCxxPredicate(MIs[0], Predicate=79)
Applying legalizer ruleset to: Opcode=269, Tys={s32, s32, }, MMOs={}
.. fallback to legacy rules (no rules defined)
.. (legacy) Type 0 Action=NotFound, LLT_invalid
3151: Rejected
3155: Resume at 3155 (1 try-blocks remain)
3156: Begin try-block
3163: GIM_CheckSimplePredicate(Predicate=103)
3167: GIM_CheckCxxPredicate(MIs[0], Predicate=80)
Applying legalizer ruleset to: Opcode=270, Tys={s32, s32, }, MMOs={}
.. fallback to legacy rules (no rules defined)
.. (legacy) Type 0 Action=NotFound, LLT_invalid
3167: Rejected
3171: Resume at 3171 (1 try-blocks remain)
3172: Begin try-block
3179: GIM_CheckSimplePredicate(Predicate=104)
3183: GIM_CheckCxxPredicate(MIs[0], Predicate=81)
3183: Rejected
3187: Resume at 3187 (1 try-blocks remain)
3188: Begin try-block
3195: GIM_CheckSimplePredicate(Predicate=122)
3199: GIM_CheckCxxPredicate(MIs[0], Predicate=98)
3199: Rejected
3203: Resume at 3203 (1 try-blocks remain)
3204: Begin try-block
3211: GIM_CheckSimplePredicate(Predicate=25)
3215: GIM_CheckConstantInt(MIs[0]->getOperand(2), Value=0)
3215: Rejected
3228: Resume at 3228 (1 try-blocks remain)
3229: GIM_Reject
3229: Rejected
5125: Resume at 5125 (0 try-blocks remain)
5126: GIM_Reject
5126: Rejected

Try combining %10:_(s32) = G_ASHR %2:_, %3:_(s32)
10: GIM_SwitchOpcode(MIs[0], [19, 228), Default=5125, JumpTable...) // Got=129
3060: Begin try-block
3067: GIM_CheckSimplePredicate(Predicate=16)
3071: GIM_CheckCxxPredicate(MIs[0], Predicate=12)
3071: Rejected
3075: Resume at 3075 (1 try-blocks remain)
3076: Begin try-block
3083: GIM_CheckSimplePredicate(Predicate=45)
3087: GIM_CheckCxxPredicate(MIs[0], Predicate=32)
3087: Rejected
3091: Resume at 3091 (1 try-blocks remain)
3092: Begin try-block
3099: GIM_CheckSimplePredicate(Predicate=49)
3103: GIM_CheckCxxPredicate(MIs[0], Predicate=36)
3103: Rejected
3107: Resume at 3107 (1 try-blocks remain)
3108: Begin try-block
3115: GIM_CheckSimplePredicate(Predicate=90)
3119: GIM_CheckCxxPredicate(MIs[0], Predicate=69)
3119: Rejected
3123: Resume at 3123 (1 try-blocks remain)
3124: Begin try-block
3131: GIM_CheckSimplePredicate(Predicate=91)
3135: GIM_CheckCxxPredicate(MIs[0], Predicate=70)
3135: Rejected
3139: Resume at 3139 (1 try-blocks remain)
3140: Begin try-block
3147: GIM_CheckSimplePredicate(Predicate=102)
3151: GIM_CheckCxxPredicate(MIs[0], Predicate=79)
Applying legalizer ruleset to: Opcode=269, Tys={s32, s32, }, MMOs={}
.. fallback to legacy rules (no rules defined)
.. (legacy) Type 0 Action=NotFound, LLT_invalid
3151: Rejected
3155: Resume at 3155 (1 try-blocks remain)
3156: Begin try-block
3163: GIM_CheckSimplePredicate(Predicate=103)
3167: GIM_CheckCxxPredicate(MIs[0], Predicate=80)
Applying legalizer ruleset to: Opcode=270, Tys={s32, s32, }, MMOs={}
.. fallback to legacy rules (no rules defined)
.. (legacy) Type 0 Action=NotFound, LLT_invalid
3167: Rejected
3171: Resume at 3171 (1 try-blocks remain)
3172: Begin try-block
3179: GIM_CheckSimplePredicate(Predicate=104)
3183: GIM_CheckCxxPredicate(MIs[0], Predicate=81)
3183: Rejected
3187: Resume at 3187 (1 try-blocks remain)
3188: Begin try-block
3195: GIM_CheckSimplePredicate(Predicate=122)
3199: GIM_CheckCxxPredicate(MIs[0], Predicate=98)
3199: Rejected
3203: Resume at 3203 (1 try-blocks remain)
3204: Begin try-block
3211: GIM_CheckSimplePredicate(Predicate=25)
3215: GIM_CheckConstantInt(MIs[0]->getOperand(2), Value=0)
3215: Rejected
3228: Resume at 3228 (1 try-blocks remain)
3229: GIM_Reject
3229: Rejected
5125: Resume at 5125 (0 try-blocks remain)
5126: GIM_Reject
5126: Rejected

Try combining %11:_(s32) = nsw G_MUL %10:_, %9:_
10: GIM_SwitchOpcode(MIs[0], [19, 228), Default=5125, JumpTable...) // Got=49
1164: Begin try-block
1171: GIM_CheckSimplePredicate(Predicate=13)
1175: GIM_CheckCxxPredicate(MIs[0], Predicate=10)
1175: Rejected
1179: Resume at 1179 (1 try-blocks remain)
1180: Begin try-block
1187: GIM_CheckSimplePredicate(Predicate=104)
1191: GIM_CheckCxxPredicate(MIs[0], Predicate=81)
1191: Rejected
1195: Resume at 1195 (1 try-blocks remain)
1196: Begin try-block
1203: GIM_CheckSimplePredicate(Predicate=127)
1207: GIM_CheckCxxPredicate(MIs[0], Predicate=103)
1207: Rejected
1211: Resume at 1211 (1 try-blocks remain)
1212: Begin try-block
1219: GIM_CheckSimplePredicate(Predicate=4)
1223: GIM_RecordRegType(MIs[0]->getOperand(0), TypeIdx=-1)
1227: GIM_CheckConstantInt(MIs[0]->getOperand(2), Value=18446744073709551615)
1227: Rejected
1258: Resume at 1258 (1 try-blocks remain)
1259: Begin try-block
1266: GIM_CheckSimplePredicate(Predicate=28)
1270: GIM_CheckConstantInt(MIs[0]->getOperand(2), Value=0)
1270: Rejected
1283: Resume at 1283 (1 try-blocks remain)
1284: Begin try-block
1291: GIM_CheckSimplePredicate(Predicate=33)
1295: GIM_CheckConstantInt(MIs[0]->getOperand(2), Value=1)
1295: Rejected
1308: Resume at 1308 (1 try-blocks remain)
1309: Begin try-block
1316: GIM_CheckSimplePredicate(Predicate=2)
1320: GIM_CheckCxxPredicate(MIs[0], Predicate=2)
1320: Rejected
1324: Resume at 1324 (1 try-blocks remain)
1325: GIM_Reject
1325: Rejected
5125: Resume at 5125 (0 try-blocks remain)
5126: GIM_Reject
5126: Rejected

Try combining %12:_(s32) = G_ADD %11:_, %0:_
10: GIM_SwitchOpcode(MIs[0], [19, 228), Default=5125, JumpTable...) // Got=47
864: Begin try-block
871: GIM_CheckSimplePredicate(Predicate=3)
875: GIM_CheckCxxPredicate(MIs[0], Predicate=3)
875: Rejected
879: Resume at 879 (1 try-blocks remain)
880: Begin try-block
887: GIM_CheckSimplePredicate(Predicate=18)
891: GIM_CheckCxxPredicate(MIs[0], Predicate=10)
891: Rejected
895: Resume at 895 (1 try-blocks remain)
896: Begin try-block
903: GIM_CheckSimplePredicate(Predicate=43)
907: GIM_CheckCxxPredicate(MIs[0], Predicate=30)
907: Rejected
911: Resume at 911 (1 try-blocks remain)
912: Begin try-block
919: GIM_CheckSimplePredicate(Predicate=104)
923: GIM_CheckCxxPredicate(MIs[0], Predicate=81)
923: Rejected
927: Resume at 927 (1 try-blocks remain)
928: Begin try-block
935: GIM_CheckSimplePredicate(Predicate=122)
939: GIM_CheckCxxPredicate(MIs[0], Predicate=98)
939: Rejected
943: Resume at 943 (1 try-blocks remain)
944: Begin try-block
951: GIM_CheckSimplePredicate(Predicate=127)
955: GIM_CheckCxxPredicate(MIs[0], Predicate=103)
955: Rejected
959: Resume at 959 (1 try-blocks remain)
960: Begin try-block
967: GIM_CheckSimplePredicate(Predicate=35)
971: MIs[1] = GIM_RecordInsn(0, 1)
975: GIM_CheckOpcode(MIs[1], ExpectedOpcode=48) // Got=49
975: Rejected
995: Resume at 995 (1 try-blocks remain)
996: Begin try-block
1003: GIM_CheckSimplePredicate(Predicate=35)
1007: MIs[1] = GIM_RecordInsn(0, 2)
1011: GIM_CheckOpcode(MIs[1], ExpectedOpcode=48) // Got=19
1011: Rejected
1031: Resume at 1031 (1 try-blocks remain)
1032: Begin try-block
1039: GIM_CheckSimplePredicate(Predicate=25)
1043: GIM_CheckConstantInt(MIs[0]->getOperand(2), Value=0)
1043: Rejected
1056: Resume at 1056 (1 try-blocks remain)
1057: Begin try-block
1064: GIM_CheckSimplePredicate(Predicate=47)
1068: GIM_CheckCxxPredicate(MIs[0], Predicate=34)
1068: Rejected
1072: Resume at 1072 (1 try-blocks remain)
1073: GIM_Reject
1073: Rejected
5125: Resume at 5125 (0 try-blocks remain)
5126: GIM_Reject
5126: Rejected

Try combining %13:_(s32) = G_ADD %12:_, %8:_
10: GIM_SwitchOpcode(MIs[0], [19, 228), Default=5125, JumpTable...) // Got=47
864: Begin try-block
871: GIM_CheckSimplePredicate(Predicate=3)
875: GIM_CheckCxxPredicate(MIs[0], Predicate=3)
875: Rejected
879: Resume at 879 (1 try-blocks remain)
880: Begin try-block
887: GIM_CheckSimplePredicate(Predicate=18)
891: GIM_CheckCxxPredicate(MIs[0], Predicate=10)
891: Rejected
895: Resume at 895 (1 try-blocks remain)
896: Begin try-block
903: GIM_CheckSimplePredicate(Predicate=43)
907: GIM_CheckCxxPredicate(MIs[0], Predicate=30)
907: Rejected
911: Resume at 911 (1 try-blocks remain)
912: Begin try-block
919: GIM_CheckSimplePredicate(Predicate=104)
923: GIM_CheckCxxPredicate(MIs[0], Predicate=81)
923: Rejected
927: Resume at 927 (1 try-blocks remain)
928: Begin try-block
935: GIM_CheckSimplePredicate(Predicate=122)
939: GIM_CheckCxxPredicate(MIs[0], Predicate=98)
939: Rejected
943: Resume at 943 (1 try-blocks remain)
944: Begin try-block
951: GIM_CheckSimplePredicate(Predicate=127)
955: GIM_CheckCxxPredicate(MIs[0], Predicate=103)
955: Rejected
959: Resume at 959 (1 try-blocks remain)
960: Begin try-block
967: GIM_CheckSimplePredicate(Predicate=35)
971: MIs[1] = GIM_RecordInsn(0, 1)
975: GIM_CheckOpcode(MIs[1], ExpectedOpcode=48) // Got=47
975: Rejected
995: Resume at 995 (1 try-blocks remain)
996: Begin try-block
1003: GIM_CheckSimplePredicate(Predicate=35)
1007: MIs[1] = GIM_RecordInsn(0, 2)
1011: GIM_CheckOpcode(MIs[1], ExpectedOpcode=48) // Got=49
1011: Rejected
1031: Resume at 1031 (1 try-blocks remain)
1032: Begin try-block
1039: GIM_CheckSimplePredicate(Predicate=25)
1043: GIM_CheckConstantInt(MIs[0]->getOperand(2), Value=0)
1043: Rejected
1056: Resume at 1056 (1 try-blocks remain)
1057: Begin try-block
1064: GIM_CheckSimplePredicate(Predicate=47)
1068: GIM_CheckCxxPredicate(MIs[0], Predicate=34)
1068: Rejected
1072: Resume at 1072 (1 try-blocks remain)
1073: GIM_Reject
1073: Rejected
5125: Resume at 5125 (0 try-blocks remain)
5126: GIM_Reject
5126: Rejected

Try combining $x10 = COPY %13:_(s32)
10: GIM_SwitchOpcode(MIs[0], [19, 228), Default=5125, JumpTable...) // Got=19
847: Begin try-block
854: GIM_CheckSimplePredicate(Predicate=1)
858: GIM_CheckCxxPredicate(MIs[0], Predicate=1)
858: Rejected
862: Resume at 862 (1 try-blocks remain)
863: GIM_Reject
863: Rejected
5125: Resume at 5125 (0 try-blocks remain)
5126: GIM_Reject
5126: Rejected

Try combining PseudoRET implicit $x10
10: GIM_SwitchOpcode(MIs[0], [19, 228), Default=5125, JumpTable...) // Got=377
5126: GIM_Reject
5126: Rejected
# *** IR Dump After RISCVPreLegalizerCombiner (riscv-prelegalizer-combiner) ***:
# Machine code for function test_macs32_v2i16: IsSSA, TracksLiveness
Function Live Ins: $x10, $x11, $x12

bb.1.entry:
  liveins: $x10, $x11, $x12
  %0:_(s32) = COPY $x10
  %1:_(s32) = COPY $x11
  %2:_(s32) = COPY $x12
  %3:_(s32) = G_CONSTANT i32 16
  %5:_(s32) = G_SEXT_INREG %1:_, 16
  %7:_(s32) = G_SEXT_INREG %2:_, 16
  %8:_(s32) = nsw G_MUL %7:_, %5:_
  %9:_(s32) = G_ASHR %1:_, %3:_(s32)
  %10:_(s32) = G_ASHR %2:_, %3:_(s32)
  %11:_(s32) = nsw G_MUL %10:_, %9:_
  %12:_(s32) = G_ADD %11:_, %0:_
  %13:_(s32) = G_ADD %12:_, %8:_
  $x10 = COPY %13:_(s32)
  PseudoRET implicit $x10

# End machine code for function test_macs32_v2i16.

# *** IR Dump Before Legalizer (legalizer) ***:
# Machine code for function test_macs32_v2i16: IsSSA, TracksLiveness
Function Live Ins: $x10, $x11, $x12

bb.1.entry:
  liveins: $x10, $x11, $x12
  %0:_(s32) = COPY $x10
  %1:_(s32) = COPY $x11
  %2:_(s32) = COPY $x12
  %3:_(s32) = G_CONSTANT i32 16
  %5:_(s32) = G_SEXT_INREG %1:_, 16
  %7:_(s32) = G_SEXT_INREG %2:_, 16
  %8:_(s32) = nsw G_MUL %7:_, %5:_
  %9:_(s32) = G_ASHR %1:_, %3:_(s32)
  %10:_(s32) = G_ASHR %2:_, %3:_(s32)
  %11:_(s32) = nsw G_MUL %10:_, %9:_
  %12:_(s32) = G_ADD %11:_, %0:_
  %13:_(s32) = G_ADD %12:_, %8:_
  $x10 = COPY %13:_(s32)
  PseudoRET implicit $x10

# End machine code for function test_macs32_v2i16.

Legalize Machine IR for: test_macs32_v2i16
=== New Iteration ===
Legalizing: %13:_(s32) = G_ADD %12:_, %8:_
Applying legalizer ruleset to: Opcode=47, Tys={s32, }, MMOs={}
.. match
.. .. Legal, 0, LLT_invalid
.. Already legal
.. No debug info was present
Legalizing: %12:_(s32) = G_ADD %11:_, %0:_
Applying legalizer ruleset to: Opcode=47, Tys={s32, }, MMOs={}
.. match
.. .. Legal, 0, LLT_invalid
.. Already legal
.. No debug info was present
Legalizing: %11:_(s32) = nsw G_MUL %10:_, %9:_
Applying legalizer ruleset to: Opcode=49, Tys={s32, }, MMOs={}
.. match
.. .. Legal, 0, LLT_invalid
.. Already legal
.. No debug info was present
Legalizing: %10:_(s32) = G_ASHR %2:_, %3:_(s32)
Applying legalizer ruleset to: Opcode=129, Tys={s32, s32, }, MMOs={}
.. match
.. .. Legal, 0, LLT_invalid
.. Already legal
.. No debug info was present
Legalizing: %9:_(s32) = G_ASHR %1:_, %3:_(s32)
Applying legalizer ruleset to: Opcode=129, Tys={s32, s32, }, MMOs={}
.. match
.. .. Legal, 0, LLT_invalid
.. Already legal
.. No debug info was present
Legalizing: %8:_(s32) = nsw G_MUL %7:_, %5:_
Applying legalizer ruleset to: Opcode=49, Tys={s32, }, MMOs={}
.. match
.. .. Legal, 0, LLT_invalid
.. Already legal
.. No debug info was present
Legalizing: %7:_(s32) = G_SEXT_INREG %2:_, 16
Applying legalizer ruleset to: Opcode=125, Tys={s32, }, MMOs={}
.. no match
.. match
.. .. Lower, 0, LLT_invalid
.. Lower
.. .. Erasing: %7:_(s32) = G_SEXT_INREG %2:_, 16
.. .. New MI: %15:_(s32) = G_CONSTANT i32 16
.. .. New MI: %14:_(s32) = G_SHL %2:_, %15:_(s32)
.. .. New MI: %7:_(s32) = G_ASHR %14:_, %15:_(s32)
.. No debug info was present
Legalizing: %7:_(s32) = G_ASHR %14:_, %15:_(s32)
Applying legalizer ruleset to: Opcode=129, Tys={s32, s32, }, MMOs={}
.. match
.. .. Legal, 0, LLT_invalid
.. Already legal
.. No debug info was present
Legalizing: %14:_(s32) = G_SHL %2:_, %15:_(s32)
.. opcode 127 is aliased to 129
Applying legalizer ruleset to: Opcode=127, Tys={s32, s32, }, MMOs={}
.. match
.. .. Legal, 0, LLT_invalid
.. Already legal
.. No debug info was present
Legalizing: %15:_(s32) = G_CONSTANT i32 16
Applying legalizer ruleset to: Opcode=120, Tys={s32, }, MMOs={}
.. match
.. .. Legal, 0, LLT_invalid
.. Already legal
.. No debug info was present
Legalizing: %5:_(s32) = G_SEXT_INREG %1:_, 16
Applying legalizer ruleset to: Opcode=125, Tys={s32, }, MMOs={}
.. no match
.. match
.. .. Lower, 0, LLT_invalid
.. Lower
.. .. Erasing: %5:_(s32) = G_SEXT_INREG %1:_, 16
.. .. New MI: %17:_(s32) = G_CONSTANT i32 16
.. .. New MI: %16:_(s32) = G_SHL %1:_, %17:_(s32)
.. .. New MI: %5:_(s32) = G_ASHR %16:_, %17:_(s32)
.. No debug info was present
Legalizing: %5:_(s32) = G_ASHR %16:_, %17:_(s32)
Applying legalizer ruleset to: Opcode=129, Tys={s32, s32, }, MMOs={}
.. match
.. .. Legal, 0, LLT_invalid
.. Already legal
.. No debug info was present
Legalizing: %16:_(s32) = G_SHL %1:_, %17:_(s32)
.. opcode 127 is aliased to 129
Applying legalizer ruleset to: Opcode=127, Tys={s32, s32, }, MMOs={}
.. match
.. .. Legal, 0, LLT_invalid
.. Already legal
.. No debug info was present
Legalizing: %17:_(s32) = G_CONSTANT i32 16
Applying legalizer ruleset to: Opcode=120, Tys={s32, }, MMOs={}
.. match
.. .. Legal, 0, LLT_invalid
.. Already legal
.. No debug info was present
Legalizing: %3:_(s32) = G_CONSTANT i32 16
Applying legalizer ruleset to: Opcode=120, Tys={s32, }, MMOs={}
.. match
.. .. Legal, 0, LLT_invalid
.. Already legal
.. No debug info was present
.. No debug info was present
# *** IR Dump After Legalizer (legalizer) ***:
# Machine code for function test_macs32_v2i16: IsSSA, TracksLiveness, Legalized
Function Live Ins: $x10, $x11, $x12

bb.1.entry:
  liveins: $x10, $x11, $x12
  %0:_(s32) = COPY $x10
  %1:_(s32) = COPY $x11
  %2:_(s32) = COPY $x12
  %3:_(s32) = G_CONSTANT i32 16
  %17:_(s32) = G_CONSTANT i32 16
  %16:_(s32) = G_SHL %1:_, %17:_(s32)
  %5:_(s32) = G_ASHR %16:_, %17:_(s32)
  %15:_(s32) = G_CONSTANT i32 16
  %14:_(s32) = G_SHL %2:_, %15:_(s32)
  %7:_(s32) = G_ASHR %14:_, %15:_(s32)
  %8:_(s32) = nsw G_MUL %7:_, %5:_
  %9:_(s32) = G_ASHR %1:_, %3:_(s32)
  %10:_(s32) = G_ASHR %2:_, %3:_(s32)
  %11:_(s32) = nsw G_MUL %10:_, %9:_
  %12:_(s32) = G_ADD %11:_, %0:_
  %13:_(s32) = G_ADD %12:_, %8:_
  $x10 = COPY %13:_(s32)
  PseudoRET implicit $x10

# End machine code for function test_macs32_v2i16.

# *** IR Dump Before RISCVPostLegalizerCombiner (riscv-postlegalizer-combiner) ***:
# Machine code for function test_macs32_v2i16: IsSSA, TracksLiveness, Legalized
Function Live Ins: $x10, $x11, $x12

bb.1.entry:
  liveins: $x10, $x11, $x12
  %0:_(s32) = COPY $x10
  %1:_(s32) = COPY $x11
  %2:_(s32) = COPY $x12
  %3:_(s32) = G_CONSTANT i32 16
  %17:_(s32) = G_CONSTANT i32 16
  %16:_(s32) = G_SHL %1:_, %17:_(s32)
  %5:_(s32) = G_ASHR %16:_, %17:_(s32)
  %15:_(s32) = G_CONSTANT i32 16
  %14:_(s32) = G_SHL %2:_, %15:_(s32)
  %7:_(s32) = G_ASHR %14:_, %15:_(s32)
  %8:_(s32) = nsw G_MUL %7:_, %5:_
  %9:_(s32) = G_ASHR %1:_, %3:_(s32)
  %10:_(s32) = G_ASHR %2:_, %3:_(s32)
  %11:_(s32) = nsw G_MUL %10:_, %9:_
  %12:_(s32) = G_ADD %11:_, %0:_
  %13:_(s32) = G_ADD %12:_, %8:_
  $x10 = COPY %13:_(s32)
  PseudoRET implicit $x10

# End machine code for function test_macs32_v2i16.

Generic MI Combiner for: test_macs32_v2i16

Try combining %0:_(s32) = COPY $x10
10: GIM_SwitchOpcode(MIs[0], [47, 204), Default=1441, JumpTable...) // Got=19
1442: GIM_Reject
1442: Rejected

Try combining %1:_(s32) = COPY $x11
10: GIM_SwitchOpcode(MIs[0], [47, 204), Default=1441, JumpTable...) // Got=19
1442: GIM_Reject
1442: Rejected

Try combining %2:_(s32) = COPY $x12
10: GIM_SwitchOpcode(MIs[0], [47, 204), Default=1441, JumpTable...) // Got=19
1442: GIM_Reject
1442: Rejected

Try combining %3:_(s32) = G_CONSTANT i32 16
10: GIM_SwitchOpcode(MIs[0], [47, 204), Default=1441, JumpTable...) // Got=120
1442: GIM_Reject
1442: Rejected

Try combining %17:_(s32) = G_CONSTANT i32 16
10: GIM_SwitchOpcode(MIs[0], [47, 204), Default=1441, JumpTable...) // Got=120
1442: GIM_Reject
1442: Rejected

Try combining %16:_(s32) = G_SHL %1:_, %17:_(s32)
10: GIM_SwitchOpcode(MIs[0], [47, 204), Default=1441, JumpTable...) // Got=127
1158: Begin try-block
1165: GIM_CheckSimplePredicate(Predicate=3)
1169: GIM_CheckConstantInt(MIs[0]->getOperand(2), Value=0)
1169: Rejected
1182: Resume at 1182 (1 try-blocks remain)
1183: GIM_Reject
1183: Rejected
1441: Resume at 1441 (0 try-blocks remain)
1442: GIM_Reject
1442: Rejected

Try combining %5:_(s32) = G_ASHR %16:_, %17:_(s32)
10: GIM_SwitchOpcode(MIs[0], [47, 204), Default=1441, JumpTable...) // Got=129
1210: Begin try-block
1217: GIM_CheckSimplePredicate(Predicate=3)
1221: GIM_CheckConstantInt(MIs[0]->getOperand(2), Value=0)
1221: Rejected
1234: Resume at 1234 (1 try-blocks remain)
1235: GIM_Reject
1235: Rejected
1441: Resume at 1441 (0 try-blocks remain)
1442: GIM_Reject
1442: Rejected

Try combining %15:_(s32) = G_CONSTANT i32 16
10: GIM_SwitchOpcode(MIs[0], [47, 204), Default=1441, JumpTable...) // Got=120
1442: GIM_Reject
1442: Rejected

Try combining %14:_(s32) = G_SHL %2:_, %15:_(s32)
10: GIM_SwitchOpcode(MIs[0], [47, 204), Default=1441, JumpTable...) // Got=127
1158: Begin try-block
1165: GIM_CheckSimplePredicate(Predicate=3)
1169: GIM_CheckConstantInt(MIs[0]->getOperand(2), Value=0)
1169: Rejected
1182: Resume at 1182 (1 try-blocks remain)
1183: GIM_Reject
1183: Rejected
1441: Resume at 1441 (0 try-blocks remain)
1442: GIM_Reject
1442: Rejected

Try combining %7:_(s32) = G_ASHR %14:_, %15:_(s32)
10: GIM_SwitchOpcode(MIs[0], [47, 204), Default=1441, JumpTable...) // Got=129
1210: Begin try-block
1217: GIM_CheckSimplePredicate(Predicate=3)
1221: GIM_CheckConstantInt(MIs[0]->getOperand(2), Value=0)
1221: Rejected
1234: Resume at 1234 (1 try-blocks remain)
1235: GIM_Reject
1235: Rejected
1441: Resume at 1441 (0 try-blocks remain)
1442: GIM_Reject
1442: Rejected

Try combining %8:_(s32) = nsw G_MUL %7:_, %5:_
10: GIM_SwitchOpcode(MIs[0], [47, 204), Default=1441, JumpTable...) // Got=49
763: Begin try-block
770: GIM_CheckSimplePredicate(Predicate=6)
774: GIM_CheckConstantInt(MIs[0]->getOperand(2), Value=0)
774: Rejected
787: Resume at 787 (1 try-blocks remain)
788: Begin try-block
795: GIM_CheckSimplePredicate(Predicate=11)
799: GIM_CheckConstantInt(MIs[0]->getOperand(2), Value=1)
799: Rejected
812: Resume at 812 (1 try-blocks remain)
813: GIM_Reject
813: Rejected
1441: Resume at 1441 (0 try-blocks remain)
1442: GIM_Reject
1442: Rejected

Try combining %9:_(s32) = G_ASHR %1:_, %3:_(s32)
10: GIM_SwitchOpcode(MIs[0], [47, 204), Default=1441, JumpTable...) // Got=129
1210: Begin try-block
1217: GIM_CheckSimplePredicate(Predicate=3)
1221: GIM_CheckConstantInt(MIs[0]->getOperand(2), Value=0)
1221: Rejected
1234: Resume at 1234 (1 try-blocks remain)
1235: GIM_Reject
1235: Rejected
1441: Resume at 1441 (0 try-blocks remain)
1442: GIM_Reject
1442: Rejected

Try combining %10:_(s32) = G_ASHR %2:_, %3:_(s32)
10: GIM_SwitchOpcode(MIs[0], [47, 204), Default=1441, JumpTable...) // Got=129
1210: Begin try-block
1217: GIM_CheckSimplePredicate(Predicate=3)
1221: GIM_CheckConstantInt(MIs[0]->getOperand(2), Value=0)
1221: Rejected
1234: Resume at 1234 (1 try-blocks remain)
1235: GIM_Reject
1235: Rejected
1441: Resume at 1441 (0 try-blocks remain)
1442: GIM_Reject
1442: Rejected

Try combining %11:_(s32) = nsw G_MUL %10:_, %9:_
10: GIM_SwitchOpcode(MIs[0], [47, 204), Default=1441, JumpTable...) // Got=49
763: Begin try-block
770: GIM_CheckSimplePredicate(Predicate=6)
774: GIM_CheckConstantInt(MIs[0]->getOperand(2), Value=0)
774: Rejected
787: Resume at 787 (1 try-blocks remain)
788: Begin try-block
795: GIM_CheckSimplePredicate(Predicate=11)
799: GIM_CheckConstantInt(MIs[0]->getOperand(2), Value=1)
799: Rejected
812: Resume at 812 (1 try-blocks remain)
813: GIM_Reject
813: Rejected
1441: Resume at 1441 (0 try-blocks remain)
1442: GIM_Reject
1442: Rejected

Try combining %12:_(s32) = G_ADD %11:_, %0:_
10: GIM_SwitchOpcode(MIs[0], [47, 204), Default=1441, JumpTable...) // Got=47
639: Begin try-block
646: GIM_CheckSimplePredicate(Predicate=13)
650: MIs[1] = GIM_RecordInsn(0, 1)
654: GIM_CheckOpcode(MIs[1], ExpectedOpcode=48) // Got=49
654: Rejected
674: Resume at 674 (1 try-blocks remain)
675: Begin try-block
682: GIM_CheckSimplePredicate(Predicate=13)
686: MIs[1] = GIM_RecordInsn(0, 2)
690: GIM_CheckOpcode(MIs[1], ExpectedOpcode=48) // Got=19
690: Rejected
710: Resume at 710 (1 try-blocks remain)
711: Begin try-block
718: GIM_CheckSimplePredicate(Predicate=3)
722: GIM_CheckConstantInt(MIs[0]->getOperand(2), Value=0)
722: Rejected
735: Resume at 735 (1 try-blocks remain)
736: GIM_Reject
736: Rejected
1441: Resume at 1441 (0 try-blocks remain)
1442: GIM_Reject
1442: Rejected

Try combining %13:_(s32) = G_ADD %12:_, %8:_
10: GIM_SwitchOpcode(MIs[0], [47, 204), Default=1441, JumpTable...) // Got=47
639: Begin try-block
646: GIM_CheckSimplePredicate(Predicate=13)
650: MIs[1] = GIM_RecordInsn(0, 1)
654: GIM_CheckOpcode(MIs[1], ExpectedOpcode=48) // Got=47
654: Rejected
674: Resume at 674 (1 try-blocks remain)
675: Begin try-block
682: GIM_CheckSimplePredicate(Predicate=13)
686: MIs[1] = GIM_RecordInsn(0, 2)
690: GIM_CheckOpcode(MIs[1], ExpectedOpcode=48) // Got=49
690: Rejected
710: Resume at 710 (1 try-blocks remain)
711: Begin try-block
718: GIM_CheckSimplePredicate(Predicate=3)
722: GIM_CheckConstantInt(MIs[0]->getOperand(2), Value=0)
722: Rejected
735: Resume at 735 (1 try-blocks remain)
736: GIM_Reject
736: Rejected
1441: Resume at 1441 (0 try-blocks remain)
1442: GIM_Reject
1442: Rejected

Try combining $x10 = COPY %13:_(s32)
10: GIM_SwitchOpcode(MIs[0], [47, 204), Default=1441, JumpTable...) // Got=19
1442: GIM_Reject
1442: Rejected

Try combining PseudoRET implicit $x10
10: GIM_SwitchOpcode(MIs[0], [47, 204), Default=1441, JumpTable...) // Got=377
1442: GIM_Reject
1442: Rejected
# *** IR Dump After RISCVPostLegalizerCombiner (riscv-postlegalizer-combiner) ***:
# Machine code for function test_macs32_v2i16: IsSSA, TracksLiveness, Legalized
Function Live Ins: $x10, $x11, $x12

bb.1.entry:
  liveins: $x10, $x11, $x12
  %0:_(s32) = COPY $x10
  %1:_(s32) = COPY $x11
  %2:_(s32) = COPY $x12
  %3:_(s32) = G_CONSTANT i32 16
  %17:_(s32) = G_CONSTANT i32 16
  %16:_(s32) = G_SHL %1:_, %17:_(s32)
  %5:_(s32) = G_ASHR %16:_, %17:_(s32)
  %15:_(s32) = G_CONSTANT i32 16
  %14:_(s32) = G_SHL %2:_, %15:_(s32)
  %7:_(s32) = G_ASHR %14:_, %15:_(s32)
  %8:_(s32) = nsw G_MUL %7:_, %5:_
  %9:_(s32) = G_ASHR %1:_, %3:_(s32)
  %10:_(s32) = G_ASHR %2:_, %3:_(s32)
  %11:_(s32) = nsw G_MUL %10:_, %9:_
  %12:_(s32) = G_ADD %11:_, %0:_
  %13:_(s32) = G_ADD %12:_, %8:_
  $x10 = COPY %13:_(s32)
  PseudoRET implicit $x10

# End machine code for function test_macs32_v2i16.

# *** IR Dump Before RegBankSelect (regbankselect) ***:
# Machine code for function test_macs32_v2i16: IsSSA, TracksLiveness, Legalized
Function Live Ins: $x10, $x11, $x12

bb.1.entry:
  liveins: $x10, $x11, $x12
  %0:_(s32) = COPY $x10
  %1:_(s32) = COPY $x11
  %2:_(s32) = COPY $x12
  %3:_(s32) = G_CONSTANT i32 16
  %17:_(s32) = G_CONSTANT i32 16
  %16:_(s32) = G_SHL %1:_, %17:_(s32)
  %5:_(s32) = G_ASHR %16:_, %17:_(s32)
  %15:_(s32) = G_CONSTANT i32 16
  %14:_(s32) = G_SHL %2:_, %15:_(s32)
  %7:_(s32) = G_ASHR %14:_, %15:_(s32)
  %8:_(s32) = nsw G_MUL %7:_, %5:_
  %9:_(s32) = G_ASHR %1:_, %3:_(s32)
  %10:_(s32) = G_ASHR %2:_, %3:_(s32)
  %11:_(s32) = nsw G_MUL %10:_, %9:_
  %12:_(s32) = G_ADD %11:_, %0:_
  %13:_(s32) = G_ADD %12:_, %8:_
  $x10 = COPY %13:_(s32)
  PseudoRET implicit $x10

# End machine code for function test_macs32_v2i16.

Assign register banks for: test_macs32_v2i16
Applying legalizer ruleset to: Opcode=120, Tys={s32, }, MMOs={}
.. match
.. .. Legal, 0, LLT_invalid
Applying legalizer ruleset to: Opcode=120, Tys={s32, }, MMOs={}
.. match
.. .. Legal, 0, LLT_invalid
.. opcode 127 is aliased to 129
Applying legalizer ruleset to: Opcode=127, Tys={s32, s32, }, MMOs={}
.. match
.. .. Legal, 0, LLT_invalid
Applying legalizer ruleset to: Opcode=129, Tys={s32, s32, }, MMOs={}
.. match
.. .. Legal, 0, LLT_invalid
Applying legalizer ruleset to: Opcode=120, Tys={s32, }, MMOs={}
.. match
.. .. Legal, 0, LLT_invalid
.. opcode 127 is aliased to 129
Applying legalizer ruleset to: Opcode=127, Tys={s32, s32, }, MMOs={}
.. match
.. .. Legal, 0, LLT_invalid
Applying legalizer ruleset to: Opcode=129, Tys={s32, s32, }, MMOs={}
.. match
.. .. Legal, 0, LLT_invalid
Applying legalizer ruleset to: Opcode=49, Tys={s32, }, MMOs={}
.. match
.. .. Legal, 0, LLT_invalid
Applying legalizer ruleset to: Opcode=129, Tys={s32, s32, }, MMOs={}
.. match
.. .. Legal, 0, LLT_invalid
Applying legalizer ruleset to: Opcode=129, Tys={s32, s32, }, MMOs={}
.. match
.. .. Legal, 0, LLT_invalid
Applying legalizer ruleset to: Opcode=49, Tys={s32, }, MMOs={}
.. match
.. .. Legal, 0, LLT_invalid
Applying legalizer ruleset to: Opcode=47, Tys={s32, }, MMOs={}
.. match
.. .. Legal, 0, LLT_invalid
Applying legalizer ruleset to: Opcode=47, Tys={s32, }, MMOs={}
.. match
.. .. Legal, 0, LLT_invalid
Assign: %0:_(s32) = COPY $x10
Evaluating mapping cost for: %0:_(s32) = COPY $x10
With: ID: 4294967295 Cost: 1 Mapping: { Idx: 0 Map: #BreakDown: 1 [[0, 31], RegBank = GPRB]}
Opd0
Does assignment already match: none against GPRB
=> is free (simple assignment).
Total cost is: 1 * 1 + 0
Best Mapping: ID: 4294967295 Cost: 1 Mapping: { Idx: 0 Map: #BreakDown: 1 [[0, 31], RegBank = GPRB]}
Actual mapping of the operands: Mapping ID: 4294967295 Operand Mapping: 
Applying default-like mapping
OpIdx 0 has not been repaired, nothing to be done
Assign: %1:_(s32) = COPY $x11
Evaluating mapping cost for: %1:_(s32) = COPY $x11
With: ID: 4294967295 Cost: 1 Mapping: { Idx: 0 Map: #BreakDown: 1 [[0, 31], RegBank = GPRB]}
Opd0
Does assignment already match: none against GPRB
=> is free (simple assignment).
Total cost is: 1 * 1 + 0
Best Mapping: ID: 4294967295 Cost: 1 Mapping: { Idx: 0 Map: #BreakDown: 1 [[0, 31], RegBank = GPRB]}
Actual mapping of the operands: Mapping ID: 4294967295 Operand Mapping: 
Applying default-like mapping
OpIdx 0 has not been repaired, nothing to be done
Assign: %2:_(s32) = COPY $x12
Evaluating mapping cost for: %2:_(s32) = COPY $x12
With: ID: 4294967295 Cost: 1 Mapping: { Idx: 0 Map: #BreakDown: 1 [[0, 31], RegBank = GPRB]}
Opd0
Does assignment already match: none against GPRB
=> is free (simple assignment).
Total cost is: 1 * 1 + 0
Best Mapping: ID: 4294967295 Cost: 1 Mapping: { Idx: 0 Map: #BreakDown: 1 [[0, 31], RegBank = GPRB]}
Actual mapping of the operands: Mapping ID: 4294967295 Operand Mapping: 
Applying default-like mapping
OpIdx 0 has not been repaired, nothing to be done
Assign: %3:_(s32) = G_CONSTANT i32 16
Evaluating mapping cost for: %3:_(s32) = G_CONSTANT i32 16
With: ID: 4294967295 Cost: 1 Mapping: { Idx: 0 Map: #BreakDown: 1 [[0, 31], RegBank = GPRB]}, { Idx: 1 Map: #BreakDown: 0 }
Opd0
Does assignment already match: none against GPRB
=> is free (simple assignment).
Total cost is: 1 * 1 + 0
Best Mapping: ID: 4294967295 Cost: 1 Mapping: { Idx: 0 Map: #BreakDown: 1 [[0, 31], RegBank = GPRB]}, { Idx: 1 Map: #BreakDown: 0 }
Actual mapping of the operands: Mapping ID: 4294967295 Operand Mapping: 
Applying default-like mapping
OpIdx 0 has not been repaired, nothing to be done
OpIdx 1 is not a register, nothing to be done
Assign: %17:_(s32) = G_CONSTANT i32 16
Evaluating mapping cost for: %17:_(s32) = G_CONSTANT i32 16
With: ID: 4294967295 Cost: 1 Mapping: { Idx: 0 Map: #BreakDown: 1 [[0, 31], RegBank = GPRB]}, { Idx: 1 Map: #BreakDown: 0 }
Opd0
Does assignment already match: none against GPRB
=> is free (simple assignment).
Total cost is: 1 * 1 + 0
Best Mapping: ID: 4294967295 Cost: 1 Mapping: { Idx: 0 Map: #BreakDown: 1 [[0, 31], RegBank = GPRB]}, { Idx: 1 Map: #BreakDown: 0 }
Actual mapping of the operands: Mapping ID: 4294967295 Operand Mapping: 
Applying default-like mapping
OpIdx 0 has not been repaired, nothing to be done
OpIdx 1 is not a register, nothing to be done
Assign: %16:_(s32) = G_SHL %1:gprb, %17:gprb(s32)
Evaluating mapping cost for: %16:_(s32) = G_SHL %1:gprb, %17:gprb(s32)
With: ID: 4294967295 Cost: 1 Mapping: { Idx: 0 Map: #BreakDown: 1 [[0, 31], RegBank = GPRB]}, { Idx: 1 Map: #BreakDown: 1 [[0, 31], RegBank = GPRB]}, { Idx: 2 Map: #BreakDown: 1 [[0, 31], RegBank = GPRB]}
Opd0
Does assignment already match: none against GPRB
=> is free (simple assignment).
Opd1
Does assignment already match: GPRB against GPRB
=> is free (match).
Opd2
Does assignment already match: GPRB against GPRB
=> is free (match).
Total cost is: 1 * 1 + 0
Best Mapping: ID: 4294967295 Cost: 1 Mapping: { Idx: 0 Map: #BreakDown: 1 [[0, 31], RegBank = GPRB]}, { Idx: 1 Map: #BreakDown: 1 [[0, 31], RegBank = GPRB]}, { Idx: 2 Map: #BreakDown: 1 [[0, 31], RegBank = GPRB]}
Actual mapping of the operands: Mapping ID: 4294967295 Operand Mapping: 
Applying default-like mapping
OpIdx 0 has not been repaired, nothing to be done
OpIdx 1 has not been repaired, nothing to be done
OpIdx 2 has not been repaired, nothing to be done
Assign: %5:_(s32) = G_ASHR %16:gprb, %17:gprb(s32)
Evaluating mapping cost for: %5:_(s32) = G_ASHR %16:gprb, %17:gprb(s32)
With: ID: 4294967295 Cost: 1 Mapping: { Idx: 0 Map: #BreakDown: 1 [[0, 31], RegBank = GPRB]}, { Idx: 1 Map: #BreakDown: 1 [[0, 31], RegBank = GPRB]}, { Idx: 2 Map: #BreakDown: 1 [[0, 31], RegBank = GPRB]}
Opd0
Does assignment already match: none against GPRB
=> is free (simple assignment).
Opd1
Does assignment already match: GPRB against GPRB
=> is free (match).
Opd2
Does assignment already match: GPRB against GPRB
=> is free (match).
Total cost is: 1 * 1 + 0
Best Mapping: ID: 4294967295 Cost: 1 Mapping: { Idx: 0 Map: #BreakDown: 1 [[0, 31], RegBank = GPRB]}, { Idx: 1 Map: #BreakDown: 1 [[0, 31], RegBank = GPRB]}, { Idx: 2 Map: #BreakDown: 1 [[0, 31], RegBank = GPRB]}
Actual mapping of the operands: Mapping ID: 4294967295 Operand Mapping: 
Applying default-like mapping
OpIdx 0 has not been repaired, nothing to be done
OpIdx 1 has not been repaired, nothing to be done
OpIdx 2 has not been repaired, nothing to be done
Assign: %15:_(s32) = G_CONSTANT i32 16
Evaluating mapping cost for: %15:_(s32) = G_CONSTANT i32 16
With: ID: 4294967295 Cost: 1 Mapping: { Idx: 0 Map: #BreakDown: 1 [[0, 31], RegBank = GPRB]}, { Idx: 1 Map: #BreakDown: 0 }
Opd0
Does assignment already match: none against GPRB
=> is free (simple assignment).
Total cost is: 1 * 1 + 0
Best Mapping: ID: 4294967295 Cost: 1 Mapping: { Idx: 0 Map: #BreakDown: 1 [[0, 31], RegBank = GPRB]}, { Idx: 1 Map: #BreakDown: 0 }
Actual mapping of the operands: Mapping ID: 4294967295 Operand Mapping: 
Applying default-like mapping
OpIdx 0 has not been repaired, nothing to be done
OpIdx 1 is not a register, nothing to be done
Assign: %14:_(s32) = G_SHL %2:gprb, %15:gprb(s32)
Evaluating mapping cost for: %14:_(s32) = G_SHL %2:gprb, %15:gprb(s32)
With: ID: 4294967295 Cost: 1 Mapping: { Idx: 0 Map: #BreakDown: 1 [[0, 31], RegBank = GPRB]}, { Idx: 1 Map: #BreakDown: 1 [[0, 31], RegBank = GPRB]}, { Idx: 2 Map: #BreakDown: 1 [[0, 31], RegBank = GPRB]}
Opd0
Does assignment already match: none against GPRB
=> is free (simple assignment).
Opd1
Does assignment already match: GPRB against GPRB
=> is free (match).
Opd2
Does assignment already match: GPRB against GPRB
=> is free (match).
Total cost is: 1 * 1 + 0
Best Mapping: ID: 4294967295 Cost: 1 Mapping: { Idx: 0 Map: #BreakDown: 1 [[0, 31], RegBank = GPRB]}, { Idx: 1 Map: #BreakDown: 1 [[0, 31], RegBank = GPRB]}, { Idx: 2 Map: #BreakDown: 1 [[0, 31], RegBank = GPRB]}
Actual mapping of the operands: Mapping ID: 4294967295 Operand Mapping: 
Applying default-like mapping
OpIdx 0 has not been repaired, nothing to be done
OpIdx 1 has not been repaired, nothing to be done
OpIdx 2 has not been repaired, nothing to be done
Assign: %7:_(s32) = G_ASHR %14:gprb, %15:gprb(s32)
Evaluating mapping cost for: %7:_(s32) = G_ASHR %14:gprb, %15:gprb(s32)
With: ID: 4294967295 Cost: 1 Mapping: { Idx: 0 Map: #BreakDown: 1 [[0, 31], RegBank = GPRB]}, { Idx: 1 Map: #BreakDown: 1 [[0, 31], RegBank = GPRB]}, { Idx: 2 Map: #BreakDown: 1 [[0, 31], RegBank = GPRB]}
Opd0
Does assignment already match: none against GPRB
=> is free (simple assignment).
Opd1
Does assignment already match: GPRB against GPRB
=> is free (match).
Opd2
Does assignment already match: GPRB against GPRB
=> is free (match).
Total cost is: 1 * 1 + 0
Best Mapping: ID: 4294967295 Cost: 1 Mapping: { Idx: 0 Map: #BreakDown: 1 [[0, 31], RegBank = GPRB]}, { Idx: 1 Map: #BreakDown: 1 [[0, 31], RegBank = GPRB]}, { Idx: 2 Map: #BreakDown: 1 [[0, 31], RegBank = GPRB]}
Actual mapping of the operands: Mapping ID: 4294967295 Operand Mapping: 
Applying default-like mapping
OpIdx 0 has not been repaired, nothing to be done
OpIdx 1 has not been repaired, nothing to be done
OpIdx 2 has not been repaired, nothing to be done
Assign: %8:_(s32) = nsw G_MUL %7:gprb, %5:gprb
Evaluating mapping cost for: %8:_(s32) = nsw G_MUL %7:gprb, %5:gprb
With: ID: 4294967295 Cost: 1 Mapping: { Idx: 0 Map: #BreakDown: 1 [[0, 31], RegBank = GPRB]}, { Idx: 1 Map: #BreakDown: 1 [[0, 31], RegBank = GPRB]}, { Idx: 2 Map: #BreakDown: 1 [[0, 31], RegBank = GPRB]}
Opd0
Does assignment already match: none against GPRB
=> is free (simple assignment).
Opd1
Does assignment already match: GPRB against GPRB
=> is free (match).
Opd2
Does assignment already match: GPRB against GPRB
=> is free (match).
Total cost is: 1 * 1 + 0
Best Mapping: ID: 4294967295 Cost: 1 Mapping: { Idx: 0 Map: #BreakDown: 1 [[0, 31], RegBank = GPRB]}, { Idx: 1 Map: #BreakDown: 1 [[0, 31], RegBank = GPRB]}, { Idx: 2 Map: #BreakDown: 1 [[0, 31], RegBank = GPRB]}
Actual mapping of the operands: Mapping ID: 4294967295 Operand Mapping: 
Applying default-like mapping
OpIdx 0 has not been repaired, nothing to be done
OpIdx 1 has not been repaired, nothing to be done
OpIdx 2 has not been repaired, nothing to be done
Assign: %9:_(s32) = G_ASHR %1:gprb, %3:gprb(s32)
Evaluating mapping cost for: %9:_(s32) = G_ASHR %1:gprb, %3:gprb(s32)
With: ID: 4294967295 Cost: 1 Mapping: { Idx: 0 Map: #BreakDown: 1 [[0, 31], RegBank = GPRB]}, { Idx: 1 Map: #BreakDown: 1 [[0, 31], RegBank = GPRB]}, { Idx: 2 Map: #BreakDown: 1 [[0, 31], RegBank = GPRB]}
Opd0
Does assignment already match: none against GPRB
=> is free (simple assignment).
Opd1
Does assignment already match: GPRB against GPRB
=> is free (match).
Opd2
Does assignment already match: GPRB against GPRB
=> is free (match).
Total cost is: 1 * 1 + 0
Best Mapping: ID: 4294967295 Cost: 1 Mapping: { Idx: 0 Map: #BreakDown: 1 [[0, 31], RegBank = GPRB]}, { Idx: 1 Map: #BreakDown: 1 [[0, 31], RegBank = GPRB]}, { Idx: 2 Map: #BreakDown: 1 [[0, 31], RegBank = GPRB]}
Actual mapping of the operands: Mapping ID: 4294967295 Operand Mapping: 
Applying default-like mapping
OpIdx 0 has not been repaired, nothing to be done
OpIdx 1 has not been repaired, nothing to be done
OpIdx 2 has not been repaired, nothing to be done
Assign: %10:_(s32) = G_ASHR %2:gprb, %3:gprb(s32)
Evaluating mapping cost for: %10:_(s32) = G_ASHR %2:gprb, %3:gprb(s32)
With: ID: 4294967295 Cost: 1 Mapping: { Idx: 0 Map: #BreakDown: 1 [[0, 31], RegBank = GPRB]}, { Idx: 1 Map: #BreakDown: 1 [[0, 31], RegBank = GPRB]}, { Idx: 2 Map: #BreakDown: 1 [[0, 31], RegBank = GPRB]}
Opd0
Does assignment already match: none against GPRB
=> is free (simple assignment).
Opd1
Does assignment already match: GPRB against GPRB
=> is free (match).
Opd2
Does assignment already match: GPRB against GPRB
=> is free (match).
Total cost is: 1 * 1 + 0
Best Mapping: ID: 4294967295 Cost: 1 Mapping: { Idx: 0 Map: #BreakDown: 1 [[0, 31], RegBank = GPRB]}, { Idx: 1 Map: #BreakDown: 1 [[0, 31], RegBank = GPRB]}, { Idx: 2 Map: #BreakDown: 1 [[0, 31], RegBank = GPRB]}
Actual mapping of the operands: Mapping ID: 4294967295 Operand Mapping: 
Applying default-like mapping
OpIdx 0 has not been repaired, nothing to be done
OpIdx 1 has not been repaired, nothing to be done
OpIdx 2 has not been repaired, nothing to be done
Assign: %11:_(s32) = nsw G_MUL %10:gprb, %9:gprb
Evaluating mapping cost for: %11:_(s32) = nsw G_MUL %10:gprb, %9:gprb
With: ID: 4294967295 Cost: 1 Mapping: { Idx: 0 Map: #BreakDown: 1 [[0, 31], RegBank = GPRB]}, { Idx: 1 Map: #BreakDown: 1 [[0, 31], RegBank = GPRB]}, { Idx: 2 Map: #BreakDown: 1 [[0, 31], RegBank = GPRB]}
Opd0
Does assignment already match: none against GPRB
=> is free (simple assignment).
Opd1
Does assignment already match: GPRB against GPRB
=> is free (match).
Opd2
Does assignment already match: GPRB against GPRB
=> is free (match).
Total cost is: 1 * 1 + 0
Best Mapping: ID: 4294967295 Cost: 1 Mapping: { Idx: 0 Map: #BreakDown: 1 [[0, 31], RegBank = GPRB]}, { Idx: 1 Map: #BreakDown: 1 [[0, 31], RegBank = GPRB]}, { Idx: 2 Map: #BreakDown: 1 [[0, 31], RegBank = GPRB]}
Actual mapping of the operands: Mapping ID: 4294967295 Operand Mapping: 
Applying default-like mapping
OpIdx 0 has not been repaired, nothing to be done
OpIdx 1 has not been repaired, nothing to be done
OpIdx 2 has not been repaired, nothing to be done
Assign: %12:_(s32) = G_ADD %11:gprb, %0:gprb
Evaluating mapping cost for: %12:_(s32) = G_ADD %11:gprb, %0:gprb
With: ID: 4294967295 Cost: 1 Mapping: { Idx: 0 Map: #BreakDown: 1 [[0, 31], RegBank = GPRB]}, { Idx: 1 Map: #BreakDown: 1 [[0, 31], RegBank = GPRB]}, { Idx: 2 Map: #BreakDown: 1 [[0, 31], RegBank = GPRB]}
Opd0
Does assignment already match: none against GPRB
=> is free (simple assignment).
Opd1
Does assignment already match: GPRB against GPRB
=> is free (match).
Opd2
Does assignment already match: GPRB against GPRB
=> is free (match).
Total cost is: 1 * 1 + 0
Best Mapping: ID: 4294967295 Cost: 1 Mapping: { Idx: 0 Map: #BreakDown: 1 [[0, 31], RegBank = GPRB]}, { Idx: 1 Map: #BreakDown: 1 [[0, 31], RegBank = GPRB]}, { Idx: 2 Map: #BreakDown: 1 [[0, 31], RegBank = GPRB]}
Actual mapping of the operands: Mapping ID: 4294967295 Operand Mapping: 
Applying default-like mapping
OpIdx 0 has not been repaired, nothing to be done
OpIdx 1 has not been repaired, nothing to be done
OpIdx 2 has not been repaired, nothing to be done
Assign: %13:_(s32) = G_ADD %12:gprb, %8:gprb
Evaluating mapping cost for: %13:_(s32) = G_ADD %12:gprb, %8:gprb
With: ID: 4294967295 Cost: 1 Mapping: { Idx: 0 Map: #BreakDown: 1 [[0, 31], RegBank = GPRB]}, { Idx: 1 Map: #BreakDown: 1 [[0, 31], RegBank = GPRB]}, { Idx: 2 Map: #BreakDown: 1 [[0, 31], RegBank = GPRB]}
Opd0
Does assignment already match: none against GPRB
=> is free (simple assignment).
Opd1
Does assignment already match: GPRB against GPRB
=> is free (match).
Opd2
Does assignment already match: GPRB against GPRB
=> is free (match).
Total cost is: 1 * 1 + 0
Best Mapping: ID: 4294967295 Cost: 1 Mapping: { Idx: 0 Map: #BreakDown: 1 [[0, 31], RegBank = GPRB]}, { Idx: 1 Map: #BreakDown: 1 [[0, 31], RegBank = GPRB]}, { Idx: 2 Map: #BreakDown: 1 [[0, 31], RegBank = GPRB]}
Actual mapping of the operands: Mapping ID: 4294967295 Operand Mapping: 
Applying default-like mapping
OpIdx 0 has not been repaired, nothing to be done
OpIdx 1 has not been repaired, nothing to be done
OpIdx 2 has not been repaired, nothing to be done
Assign: $x10 = COPY %13:gprb(s32)
Evaluating mapping cost for: $x10 = COPY %13:gprb(s32)
With: ID: 4294967295 Cost: 1 Mapping: { Idx: 0 Map: #BreakDown: 1 [[0, 31], RegBank = GPRB]}
Total cost is: 1 * 1 + 0
Best Mapping: ID: 4294967295 Cost: 1 Mapping: { Idx: 0 Map: #BreakDown: 1 [[0, 31], RegBank = GPRB]}
Actual mapping of the operands: Mapping ID: 4294967295 Operand Mapping: 
Applying default-like mapping
OpIdx 0# *** IR Dump After RegBankSelect (regbankselect) ***:
# Machine code for function test_macs32_v2i16: IsSSA, TracksLiveness, Legalized, RegBankSelected
Function Live Ins: $x10, $x11, $x12

bb.1.entry:
  liveins: $x10, $x11, $x12
  %0:gprb(s32) = COPY $x10
  %1:gprb(s32) = COPY $x11
  %2:gprb(s32) = COPY $x12
  %3:gprb(s32) = G_CONSTANT i32 16
  %17:gprb(s32) = G_CONSTANT i32 16
  %16:gprb(s32) = G_SHL %1:gprb, %17:gprb(s32)
  %5:gprb(s32) = G_ASHR %16:gprb, %17:gprb(s32)
  %15:gprb(s32) = G_CONSTANT i32 16
  %14:gprb(s32) = G_SHL %2:gprb, %15:gprb(s32)
  %7:gprb(s32) = G_ASHR %14:gprb, %15:gprb(s32)
  %8:gprb(s32) = nsw G_MUL %7:gprb, %5:gprb
  %9:gprb(s32) = G_ASHR %1:gprb, %3:gprb(s32)
  %10:gprb(s32) = G_ASHR %2:gprb, %3:gprb(s32)
  %11:gprb(s32) = nsw G_MUL %10:gprb, %9:gprb
  %12:gprb(s32) = G_ADD %11:gprb, %0:gprb
  %13:gprb(s32) = G_ADD %12:gprb, %8:gprb
  $x10 = COPY %13:gprb(s32)
  PseudoRET implicit $x10

# End machine code for function test_macs32_v2i16.

# *** IR Dump Before InstructionSelect (instruction-select) ***:
# Machine code for function test_macs32_v2i16: IsSSA, TracksLiveness, Legalized, RegBankSelected
Function Live Ins: $x10, $x11, $x12

bb.1.entry:
  liveins: $x10, $x11, $x12
  %0:gprb(s32) = COPY $x10
  %1:gprb(s32) = COPY $x11
  %2:gprb(s32) = COPY $x12
  %3:gprb(s32) = G_CONSTANT i32 16
  %17:gprb(s32) = G_CONSTANT i32 16
  %16:gprb(s32) = G_SHL %1:gprb, %17:gprb(s32)
  %5:gprb(s32) = G_ASHR %16:gprb, %17:gprb(s32)
  %15:gprb(s32) = G_CONSTANT i32 16
  %14:gprb(s32) = G_SHL %2:gprb, %15:gprb(s32)
  %7:gprb(s32) = G_ASHR %14:gprb, %15:gprb(s32)
  %8:gprb(s32) = nsw G_MUL %7:gprb, %5:gprb
  %9:gprb(s32) = G_ASHR %1:gprb, %3:gprb(s32)
  %10:gprb(s32) = G_ASHR %2:gprb, %3:gprb(s32)
  %11:gprb(s32) = nsw G_MUL %10:gprb, %9:gprb
  %12:gprb(s32) = G_ADD %11:gprb, %0:gprb
  %13:gprb(s32) = G_ADD %12:gprb, %8:gprb
  $x10 = COPY %13:gprb(s32)
  PseudoRET implicit $x10

# End machine code for function test_macs32_v2i16.

Selecting function: test_macs32_v2i16
Applying legalizer ruleset to: Opcode=120, Tys={s32, }, MMOs={}
.. match
.. .. Legal, 0, LLT_invalid
Applying legalizer ruleset to: Opcode=120, Tys={s32, }, MMOs={}
.. match
.. .. Legal, 0, LLT_invalid
.. opcode 127 is aliased to 129
Applying legalizer ruleset to: Opcode=127, Tys={s32, s32, }, MMOs={}
.. match
.. .. Legal, 0, LLT_invalid
Applying legalizer ruleset to: Opcode=129, Tys={s32, s32, }, MMOs={}
.. match
.. .. Legal, 0, LLT_invalid
Applying legalizer ruleset to: Opcode=120, Tys={s32, }, MMOs={}
.. match
.. .. Legal, 0, LLT_invalid
.. opcode 127 is aliased to 129
Applying legalizer ruleset to: Opcode=127, Tys={s32, s32, }, MMOs={}
.. match
.. .. Legal, 0, LLT_invalid
Applying legalizer ruleset to: Opcode=129, Tys={s32, s32, }, MMOs={}
.. match
.. .. Legal, 0, LLT_invalid
Applying legalizer ruleset to: Opcode=49, Tys={s32, }, MMOs={}
.. match
.. .. Legal, 0, LLT_invalid
Applying legalizer ruleset to: Opcode=129, Tys={s32, s32, }, MMOs={}
.. match
.. .. Legal, 0, LLT_invalid
Applying legalizer ruleset to: Opcode=129, Tys={s32, s32, }, MMOs={}
.. match
.. .. Legal, 0, LLT_invalid
Applying legalizer ruleset to: Opcode=49, Tys={s32, }, MMOs={}
.. match
.. .. Legal, 0, LLT_invalid
Applying legalizer ruleset to: Opcode=47, Tys={s32, }, MMOs={}
.. match
.. .. Legal, 0, LLT_invalid
Applying legalizer ruleset to: Opcode=47, Tys={s32, }, MMOs={}
.. match
.. .. Legal, 0, LLT_invalid
Selecting: 
  PseudoRET implicit $x10
Into:
  PseudoRET implicit $x10

Selecting: 
  $x10 = COPY %13:gprb(s32)
Into:
  $x10 = COPY %13:gprb(s32)

Selecting: 
  %13:gprb(s32) = G_ADD %12:gprb, %8:gprb
10: GIM_SwitchOpcode(MIs[0], [47, 276), Default=475249, JumpTable...) // Got=47
937: GIM_SwitchType(MIs[0]->getOperand(0), [3, 34), Default=14879, JumpTable...) // Got=s32
1062: Begin try-block
1070: GIM_CheckType(MIs[0]->getOperand(1), TypeID=3)
1074: GIM_CheckType(MIs[0]->getOperand(2), TypeID=3)
1075: Begin try-block
1082: GIM_CheckFeatures(ExpectedBitsetID=159)
1082: Rejected
1280: Resume at 1280 (3 try-blocks remain)
1281: Begin try-block
1288: GIM_CheckFeatures(ExpectedBitsetID=160)
1293: GIM_CheckRegBankForClass(MIs[0]->getOperand(0), RCEnum=3)
1297: MIs[1] = GIM_RecordInsn(0, 1)
1301: GIM_CheckOpcode(MIs[1], ExpectedOpcode=49) // Got=47
1301: Rejected
1486: Resume at 1486 (3 try-blocks remain)
1487: Begin try-block
1494: GIM_CheckFeatures(ExpectedBitsetID=159)
1494: Rejected
1692: Resume at 1692 (3 try-blocks remain)
1693: Begin try-block
1700: GIM_CheckFeatures(ExpectedBitsetID=160)
1705: GIM_CheckRegBankForClass(MIs[0]->getOperand(0), RCEnum=3)
1709: MIs[1] = GIM_RecordInsn(0, 1)
1713: GIM_CheckOpcode(MIs[1], ExpectedOpcode=49) // Got=47
1713: Rejected
1898: Resume at 1898 (3 try-blocks remain)
1899: Begin try-block
1906: GIM_CheckFeatures(ExpectedBitsetID=159)
1906: Rejected
2104: Resume at 2104 (3 try-blocks remain)
2105: Begin try-block
2112: GIM_CheckFeatures(ExpectedBitsetID=160)
2117: GIM_CheckRegBankForClass(MIs[0]->getOperand(0), RCEnum=3)
2122: GIM_CheckRegBankForClass(MIs[0]->getOperand(1), RCEnum=3)
2126: MIs[1] = GIM_RecordInsn(0, 2)
2130: GIM_CheckOpcode(MIs[1], ExpectedOpcode=49) // Got=49
2134: GIM_CheckType(MIs[1]->getOperand(1), TypeID=3)
2138: GIM_CheckType(MIs[1]->getOperand(2), TypeID=3)
2142: MIs[2] = GIM_RecordInsn(1, 1)
2146: GIM_CheckOpcode(MIs[2], ExpectedOpcode=129) // Got=129
2150: GIM_CheckType(MIs[2]->getOperand(1), TypeID=3)
2154: GIM_CheckType(MIs[2]->getOperand(2), TypeID=3)
2158: MIs[3] = GIM_RecordInsn(2, 1)
2162: GIM_CheckOpcode(MIs[3], ExpectedOpcode=127) // Got=127
2166: GIM_CheckType(MIs[3]->getOperand(1), TypeID=3)
2170: GIM_CheckType(MIs[3]->getOperand(2), TypeID=3)
2174: MIs[4] = GIM_RecordInsn(3, 1)
2178: GIM_CheckOpcode(MIs[4], ExpectedOpcode=129) // Got=19
2178: Rejected
2310: Resume at 2310 (3 try-blocks remain)
2311: Begin try-block
2318: GIM_CheckFeatures(ExpectedBitsetID=159)
2318: Rejected
2516: Resume at 2516 (3 try-blocks remain)
2517: Begin try-block
2524: GIM_CheckFeatures(ExpectedBitsetID=160)
2529: GIM_CheckRegBankForClass(MIs[0]->getOperand(0), RCEnum=3)
2534: GIM_CheckRegBankForClass(MIs[0]->getOperand(1), RCEnum=3)
2538: MIs[1] = GIM_RecordInsn(0, 2)
2542: GIM_CheckOpcode(MIs[1], ExpectedOpcode=49) // Got=49
2546: GIM_CheckType(MIs[1]->getOperand(1), TypeID=3)
2550: GIM_CheckType(MIs[1]->getOperand(2), TypeID=3)
2554: MIs[2] = GIM_RecordInsn(1, 1)
2558: GIM_CheckOpcode(MIs[2], ExpectedOpcode=129) // Got=129
2562: GIM_CheckType(MIs[2]->getOperand(1), TypeID=3)
2566: GIM_CheckType(MIs[2]->getOperand(2), TypeID=3)
2570: MIs[3] = GIM_RecordInsn(2, 1)
2574: GIM_CheckOpcode(MIs[3], ExpectedOpcode=127) // Got=127
2578: GIM_CheckType(MIs[3]->getOperand(1), TypeID=3)
2582: GIM_CheckType(MIs[3]->getOperand(2), TypeID=3)
2586: MIs[4] = GIM_RecordInsn(3, 1)
2590: GIM_CheckOpcode(MIs[4], ExpectedOpcode=128) // Got=19
2590: Rejected
2722: Resume at 2722 (3 try-blocks remain)
2723: Begin try-block
2730: GIM_CheckFeatures(ExpectedBitsetID=164)
2730: Rejected
2881: Resume at 2881 (3 try-blocks remain)
2882: Begin try-block
2889: GIM_CheckFeatures(ExpectedBitsetID=165)
2894: GIM_CheckRegBankForClass(MIs[0]->getOperand(0), RCEnum=3)
2898: MIs[1] = GIM_RecordInsn(0, 1)
2902: GIM_CheckOpcode(MIs[1], ExpectedOpcode=49) // Got=47
2902: Rejected
3040: Resume at 3040 (3 try-blocks remain)
3041: Begin try-block
3048: GIM_CheckFeatures(ExpectedBitsetID=164)
3048: Rejected
3199: Resume at 3199 (3 try-blocks remain)
3200: Begin try-block
3207: GIM_CheckFeatures(ExpectedBitsetID=165)
3212: GIM_CheckRegBankForClass(MIs[0]->getOperand(0), RCEnum=3)
3217: GIM_CheckRegBankForClass(MIs[0]->getOperand(1), RCEnum=3)
3221: MIs[1] = GIM_RecordInsn(0, 2)
3225: GIM_CheckOpcode(MIs[1], ExpectedOpcode=49) // Got=49
3229: GIM_CheckType(MIs[1]->getOperand(1), TypeID=3)
3233: GIM_CheckType(MIs[1]->getOperand(2), TypeID=3)
3237: MIs[2] = GIM_RecordInsn(1, 1)
3241: GIM_CheckOpcode(MIs[2], ExpectedOpcode=129) // Got=129
3245: GIM_CheckType(MIs[2]->getOperand(1), TypeID=3)
3249: GIM_CheckType(MIs[2]->getOperand(2), TypeID=3)
3253: MIs[3] = GIM_RecordInsn(2, 1)
3257: GIM_CheckOpcode(MIs[3], ExpectedOpcode=127) // Got=127
3261: GIM_CheckType(MIs[3]->getOperand(1), TypeID=3)
3265: GIM_CheckType(MIs[3]->getOperand(2), TypeID=3)
3270: GIM_CheckRegBankForClass(MIs[3]->getOperand(1), RCEnum=3)
3274: GIM_CheckConstantInt(MIs[3]->getOperand(2), Value=16)
3278: GIM_CheckConstantInt(MIs[2]->getOperand(2), Value=16)
3282: MIs[4] = GIM_RecordInsn(1, 2)
3286: GIM_CheckOpcode(MIs[4], ExpectedOpcode=129) // Got=129
3290: GIM_CheckType(MIs[4]->getOperand(1), TypeID=3)
3294: GIM_CheckType(MIs[4]->getOperand(2), TypeID=3)
3298: MIs[5] = GIM_RecordInsn(4, 1)
3302: GIM_CheckOpcode(MIs[5], ExpectedOpcode=127) // Got=127
3306: GIM_CheckType(MIs[5]->getOperand(1), TypeID=3)
3310: GIM_CheckType(MIs[5]->getOperand(2), TypeID=3)
3315: GIM_CheckRegBankForClass(MIs[5]->getOperand(1), RCEnum=3)
3319: GIM_CheckConstantInt(MIs[5]->getOperand(2), Value=16)
3323: GIM_CheckConstantInt(MIs[4]->getOperand(2), Value=16)
3325: GIM_CheckIsSafeToFold(MIs[1])
3327: GIM_CheckIsSafeToFold(MIs[2])
3329: GIM_CheckIsSafeToFold(MIs[3])
3331: GIM_CheckIsSafeToFold(MIs[4])
3333: GIM_CheckIsSafeToFold(MIs[5])
3337: GIR_BuildMI(OutMIs[0], 13145)
3341: GIR_Copy(OutMIs[0], MIs[0], 0)
3345: GIR_Copy(OutMIs[0], MIs[0], 1)
3349: GIR_Copy(OutMIs[0], MIs[5], 1)
3353: GIR_Copy(OutMIs[0], MIs[3], 1)
Converting operand: %13:gprb
Converting operand: %12:gprb(tied-def 0)
Converting operand: %1:gprb
Converting operand: %2:gprb
3355: GIR_ConstrainSelectedInstOperands(OutMIs[0])
3357: GIR_EraseFromParent(MIs[0])
3358: GIR_Done
Into:
  %13:gpr(s32) = cv_macs_i16_ %12:gpr(tied-def 0)(s32), %1:gpr(s32), %2:gpr(s32)

Selecting: 
  %12:gpr(s32) = G_ADD %11:gprb, %0:gprb
10: GIM_SwitchOpcode(MIs[0], [47, 276), Default=475249, JumpTable...) // Got=47
937: GIM_SwitchType(MIs[0]->getOperand(0), [3, 34), Default=14879, JumpTable...) // Got=s32
1062: Begin try-block
1070: GIM_CheckType(MIs[0]->getOperand(1), TypeID=3)
1074: GIM_CheckType(MIs[0]->getOperand(2), TypeID=3)
1075: Begin try-block
1082: GIM_CheckFeatures(ExpectedBitsetID=159)
1082: Rejected
1280: Resume at 1280 (3 try-blocks remain)
1281: Begin try-block
1288: GIM_CheckFeatures(ExpectedBitsetID=160)
1293: GIM_CheckRegBankForClass(MIs[0]->getOperand(0), RCEnum=3)
1297: MIs[1] = GIM_RecordInsn(0, 1)
1301: GIM_CheckOpcode(MIs[1], ExpectedOpcode=49) // Got=49
1305: GIM_CheckType(MIs[1]->getOperand(1), TypeID=3)
1309: GIM_CheckType(MIs[1]->getOperand(2), TypeID=3)
1313: MIs[2] = GIM_RecordInsn(1, 1)
1317: GIM_CheckOpcode(MIs[2], ExpectedOpcode=129) // Got=129
1321: GIM_CheckType(MIs[2]->getOperand(1), TypeID=3)
1325: GIM_CheckType(MIs[2]->getOperand(2), TypeID=3)
1329: MIs[3] = GIM_RecordInsn(2, 1)
1333: GIM_CheckOpcode(MIs[3], ExpectedOpcode=127) // Got=19
1333: Rejected
1486: Resume at 1486 (3 try-blocks remain)
1487: Begin try-block
1494: GIM_CheckFeatures(ExpectedBitsetID=159)
1494: Rejected
1692: Resume at 1692 (3 try-blocks remain)
1693: Begin try-block
1700: GIM_CheckFeatures(ExpectedBitsetID=160)
1705: GIM_CheckRegBankForClass(MIs[0]->getOperand(0), RCEnum=3)
1709: MIs[1] = GIM_RecordInsn(0, 1)
1713: GIM_CheckOpcode(MIs[1], ExpectedOpcode=49) // Got=49
1717: GIM_CheckType(MIs[1]->getOperand(1), TypeID=3)
1721: GIM_CheckType(MIs[1]->getOperand(2), TypeID=3)
1725: MIs[2] = GIM_RecordInsn(1, 1)
1729: GIM_CheckOpcode(MIs[2], ExpectedOpcode=129) // Got=129
1733: GIM_CheckType(MIs[2]->getOperand(1), TypeID=3)
1737: GIM_CheckType(MIs[2]->getOperand(2), TypeID=3)
1741: MIs[3] = GIM_RecordInsn(2, 1)
1745: GIM_CheckOpcode(MIs[3], ExpectedOpcode=127) // Got=19
1745: Rejected
1898: Resume at 1898 (3 try-blocks remain)
1899: Begin try-block
1906: GIM_CheckFeatures(ExpectedBitsetID=159)
1906: Rejected
2104: Resume at 2104 (3 try-blocks remain)
2105: Begin try-block
2112: GIM_CheckFeatures(ExpectedBitsetID=160)
2117: GIM_CheckRegBankForClass(MIs[0]->getOperand(0), RCEnum=3)
2122: GIM_CheckRegBankForClass(MIs[0]->getOperand(1), RCEnum=3)
2126: MIs[1] = GIM_RecordInsn(0, 2)
2130: GIM_CheckOpcode(MIs[1], ExpectedOpcode=49) // Got=19
2130: Rejected
2310: Resume at 2310 (3 try-blocks remain)
2311: Begin try-block
2318: GIM_CheckFeatures(ExpectedBitsetID=159)
2318: Rejected
2516: Resume at 2516 (3 try-blocks remain)
2517: Begin try-block
2524: GIM_CheckFeatures(ExpectedBitsetID=160)
2529: GIM_CheckRegBankForClass(MIs[0]->getOperand(0), RCEnum=3)
2534: GIM_CheckRegBankForClass(MIs[0]->getOperand(1), RCEnum=3)
2538: MIs[1] = GIM_RecordInsn(0, 2)
2542: GIM_CheckOpcode(MIs[1], ExpectedOpcode=49) // Got=19
2542: Rejected
2722: Resume at 2722 (3 try-blocks remain)
2723: Begin try-block
2730: GIM_CheckFeatures(ExpectedBitsetID=164)
2730: Rejected
2881: Resume at 2881 (3 try-blocks remain)
2882: Begin try-block
2889: GIM_CheckFeatures(ExpectedBitsetID=165)
2894: GIM_CheckRegBankForClass(MIs[0]->getOperand(0), RCEnum=3)
2898: MIs[1] = GIM_RecordInsn(0, 1)
2902: GIM_CheckOpcode(MIs[1], ExpectedOpcode=49) // Got=49
2906: GIM_CheckType(MIs[1]->getOperand(1), TypeID=3)
2910: GIM_CheckType(MIs[1]->getOperand(2), TypeID=3)
2914: MIs[2] = GIM_RecordInsn(1, 1)
2918: GIM_CheckOpcode(MIs[2], ExpectedOpcode=129) // Got=129
2922: GIM_CheckType(MIs[2]->getOperand(1), TypeID=3)
2926: GIM_CheckType(MIs[2]->getOperand(2), TypeID=3)
2930: MIs[3] = GIM_RecordInsn(2, 1)
2934: GIM_CheckOpcode(MIs[3], ExpectedOpcode=127) // Got=19
2934: Rejected
3040: Resume at 3040 (3 try-blocks remain)
3041: Begin try-block
3048: GIM_CheckFeatures(ExpectedBitsetID=164)
3048: Rejected
3199: Resume at 3199 (3 try-blocks remain)
3200: Begin try-block
3207: GIM_CheckFeatures(ExpectedBitsetID=165)
3212: GIM_CheckRegBankForClass(MIs[0]->getOperand(0), RCEnum=3)
3217: GIM_CheckRegBankForClass(MIs[0]->getOperand(1), RCEnum=3)
3221: MIs[1] = GIM_RecordInsn(0, 2)
3225: GIM_CheckOpcode(MIs[1], ExpectedOpcode=49) // Got=19
3225: Rejected
3358: Resume at 3358 (3 try-blocks remain)
3359: Begin try-block
3366: GIM_CheckFeatures(ExpectedBitsetID=159)
3366: Rejected
3476: Resume at 3476 (3 try-blocks remain)
3477: Begin try-block
3484: GIM_CheckFeatures(ExpectedBitsetID=160)
3489: GIM_CheckRegBankForClass(MIs[0]->getOperand(0), RCEnum=3)
3493: MIs[1] = GIM_RecordInsn(0, 1)
3497: GIM_CheckOpcode(MIs[1], ExpectedOpcode=49) // Got=49
3501: GIM_CheckType(MIs[1]->getOperand(1), TypeID=3)
3505: GIM_CheckType(MIs[1]->getOperand(2), TypeID=3)
3509: MIs[2] = GIM_RecordInsn(1, 1)
3513: GIM_CheckOpcode(MIs[2], ExpectedOpcode=129) // Got=129
3517: GIM_CheckType(MIs[2]->getOperand(1), TypeID=3)
3521: GIM_CheckType(MIs[2]->getOperand(2), TypeID=3)
3526: GIM_CheckRegBankForClass(MIs[2]->getOperand(1), RCEnum=3)
3530: GIM_CheckConstantInt(MIs[2]->getOperand(2), Value=16)
3534: MIs[3] = GIM_RecordInsn(1, 2)
3538: GIM_CheckOpcode(MIs[3], ExpectedOpcode=129) // Got=129
3542: GIM_CheckType(MIs[3]->getOperand(1), TypeID=3)
3546: GIM_CheckType(MIs[3]->getOperand(2), TypeID=3)
3551: GIM_CheckRegBankForClass(MIs[3]->getOperand(1), RCEnum=3)
3555: GIM_CheckConstantInt(MIs[3]->getOperand(2), Value=16)
3560: GIM_CheckRegBankForClass(MIs[0]->getOperand(2), RCEnum=3)
3562: GIM_CheckIsSafeToFold(MIs[1])
3564: GIM_CheckIsSafeToFold(MIs[2])
3566: GIM_CheckIsSafeToFold(MIs[3])
3570: GIR_BuildMI(OutMIs[0], 13137)
3574: GIR_Copy(OutMIs[0], MIs[0], 0)
3578: GIR_Copy(OutMIs[0], MIs[0], 2)
3582: GIR_Copy(OutMIs[0], MIs[3], 1)
3586: GIR_Copy(OutMIs[0], MIs[2], 1)
3589: GIR_AddImm(OutMIs[0], 0)
Converting operand: %12:gpr
Converting operand: %0:gprb(tied-def 0)
Converting operand: %1:gpr
Converting operand: %2:gpr
3591: GIR_ConstrainSelectedInstOperands(OutMIs[0])
3593: GIR_EraseFromParent(MIs[0])
3594: GIR_Done
Into:
  %12:gpr(s32) = cv_machhNs_ %0:gpr(tied-def 0)(s32), %1:gpr(s32), %2:gpr(s32), 0

Selecting: 
  %11:gprb(s32) = nsw G_MUL %10:gprb, %9:gprb
Is dead; erasing.
Selecting: 
  %10:gprb(s32) = G_ASHR %2:gpr, %3:gprb(s32)
Is dead; erasing.
Selecting: 
  %9:gprb(s32) = G_ASHR %1:gpr, %3:gprb(s32)
Is dead; erasing.
Selecting: 
  %8:gprb(s32) = nsw G_MUL %7:gprb, %5:gprb
Is dead; erasing.
Selecting: 
  %7:gprb(s32) = G_ASHR %14:gprb, %15:gprb(s32)
Is dead; erasing.
Selecting: 
  %14:gprb(s32) = G_SHL %2:gpr, %15:gprb(s32)
Is dead; erasing.
Selecting: 
  %15:gprb(s32) = G_CONSTANT i32 16
Is dead; erasing.
Selecting: 
  %5:gprb(s32) = G_ASHR %16:gprb, %17:gprb(s32)
Is dead; erasing.
Selecting: 
  %16:gprb(s32) = G_SHL %1:gpr, %17:gprb(s32)
Is dead; erasing.
Selecting: 
  %17:gprb(s32) = G_CONSTANT i32 16
Is dead; erasing.
Selecting: 
  %3:gprb(s32) = G_CONSTANT i32 16
Is dead; erasing.
Selecting: 
  %2:gpr(s32) = COPY $x12
Into:
  %2:gpr(s32) = COPY $x12

Selecting: 
  %1:gpr(s32) = COPY $x11
Into:
  %1:gpr(s32) = COPY $x11

Selecting: 
  %0:gpr(s32) = COPY $x10
Into:
  %0:gpr(s32) = COPY $x10

Rules covered by selecting function: test_macs32_v2i16:

# *** IR Dump After InstructionSelect (instruction-select) ***:
# Machine code for function test_macs32_v2i16: IsSSA, TracksLiveness, Legalized, RegBankSelected, Selected
Function Live Ins: $x10, $x11, $x12

bb.1.entry:
  liveins: $x10, $x11, $x12
  %0:gpr = COPY $x10
  %1:gpr = COPY $x11
  %2:gpr = COPY $x12
  %12:gpr = cv_machhNs_ %0:gpr(tied-def 0), %1:gpr, %2:gpr, 0
  %13:gpr = cv_macs_i16_ %12:gpr(tied-def 0), %1:gpr, %2:gpr
  $x10 = COPY %13:gpr
  PseudoRET implicit $x10

# End machine code for function test_macs32_v2i16.

# *** IR Dump Before Finalize ISel and expand pseudo-instructions (finalize-isel) ***:
# Machine code for function test_macs32_v2i16: IsSSA, TracksLiveness, Legalized, RegBankSelected, Selected
Function Live Ins: $x10, $x11, $x12

bb.1.entry:
  liveins: $x10, $x11, $x12
  %0:gpr = COPY $x10
  %1:gpr = COPY $x11
  %2:gpr = COPY $x12
  %12:gpr = cv_machhNs_ %0:gpr(tied-def 0), %1:gpr, %2:gpr, 0
  %13:gpr = cv_macs_i16_ %12:gpr(tied-def 0), %1:gpr, %2:gpr
  $x10 = COPY %13:gpr
  PseudoRET implicit $x10

# End machine code for function test_macs32_v2i16.

# *** IR Dump After Finalize ISel and expand pseudo-instructions (finalize-isel) ***:
# Machine code for function test_macs32_v2i16: IsSSA, TracksLiveness, Legalized, RegBankSelected, Selected
Function Live Ins: $x10, $x11, $x12

bb.1.entry:
  liveins: $x10, $x11, $x12
  %0:gpr = COPY $x10
  %1:gpr = COPY $x11
  %2:gpr = COPY $x12
  %12:gpr = cv_machhNs_ %0:gpr(tied-def 0), %1:gpr, %2:gpr, 0
  %13:gpr = cv_macs_i16_ %12:gpr(tied-def 0), %1:gpr, %2:gpr
  $x10 = COPY %13:gpr
  PseudoRET implicit $x10

# End machine code for function test_macs32_v2i16.

# *** IR Dump Before RISC-V Fold Masks (riscv-fold-masks) ***:
# Machine code for function test_macs32_v2i16: IsSSA, TracksLiveness, Legalized, RegBankSelected, Selected
Function Live Ins: $x10, $x11, $x12

bb.1.entry:
  liveins: $x10, $x11, $x12
  %0:gpr = COPY $x10
  %1:gpr = COPY $x11
  %2:gpr = COPY $x12
  %12:gpr = cv_machhNs_ %0:gpr(tied-def 0), %1:gpr, %2:gpr, 0
  %13:gpr = cv_macs_i16_ %12:gpr(tied-def 0), %1:gpr, %2:gpr
  $x10 = COPY %13:gpr
  PseudoRET implicit $x10

# End machine code for function test_macs32_v2i16.

# *** IR Dump After RISC-V Fold Masks (riscv-fold-masks) ***:
# Machine code for function test_macs32_v2i16: IsSSA, TracksLiveness, Legalized, RegBankSelected, Selected
Function Live Ins: $x10, $x11, $x12

bb.1.entry:
  liveins: $x10, $x11, $x12
  %0:gpr = COPY $x10
  %1:gpr = COPY $x11
  %2:gpr = COPY $x12
  %12:gpr = cv_machhNs_ %0:gpr(tied-def 0), %1:gpr, %2:gpr, 0
  %13:gpr = cv_macs_i16_ %12:gpr(tied-def 0), %1:gpr, %2:gpr
  $x10 = COPY %13:gpr
  PseudoRET implicit $x10

# End machine code for function test_macs32_v2i16.

# *** IR Dump Before Early Tail Duplication (early-tailduplication) ***:
# Machine code for function test_macs32_v2i16: IsSSA, TracksLiveness, Legalized, RegBankSelected, Selected
Function Live Ins: $x10, $x11, $x12

bb.1.entry:
  liveins: $x10, $x11, $x12
  %0:gpr = COPY $x10
  %1:gpr = COPY $x11
  %2:gpr = COPY $x12
  %12:gpr = cv_machhNs_ %0:gpr(tied-def 0), %1:gpr, %2:gpr, 0
  %13:gpr = cv_macs_i16_ %12:gpr(tied-def 0), %1:gpr, %2:gpr
  $x10 = COPY %13:gpr
  PseudoRET implicit $x10

# End machine code for function test_macs32_v2i16.

# *** IR Dump After Early Tail Duplication (early-tailduplication) ***:
# Machine code for function test_macs32_v2i16: IsSSA, TracksLiveness, Legalized, RegBankSelected, Selected
Function Live Ins: $x10, $x11, $x12

bb.1.entry:
  liveins: $x10, $x11, $x12
  %0:gpr = COPY $x10
  %1:gpr = COPY $x11
  %2:gpr = COPY $x12
  %12:gpr = cv_machhNs_ %0:gpr(tied-def 0), %1:gpr, %2:gpr, 0
  %13:gpr = cv_macs_i16_ %12:gpr(tied-def 0), %1:gpr, %2:gpr
  $x10 = COPY %13:gpr
  PseudoRET implicit $x10

# End machine code for function test_macs32_v2i16.

# *** IR Dump Before Optimize machine instruction PHIs (opt-phis) ***:
# Machine code for function test_macs32_v2i16: IsSSA, TracksLiveness, Legalized, RegBankSelected, Selected
Function Live Ins: $x10, $x11, $x12

bb.1.entry:
  liveins: $x10, $x11, $x12
  %0:gpr = COPY $x10
  %1:gpr = COPY $x11
  %2:gpr = COPY $x12
  %12:gpr = cv_machhNs_ %0:gpr(tied-def 0), %1:gpr, %2:gpr, 0
  %13:gpr = cv_macs_i16_ %12:gpr(tied-def 0), %1:gpr, %2:gpr
  $x10 = COPY %13:gpr
  PseudoRET implicit $x10

# End machine code for function test_macs32_v2i16.

# *** IR Dump After Optimize machine instruction PHIs (opt-phis) ***:
# Machine code for function test_macs32_v2i16: IsSSA, TracksLiveness, Legalized, RegBankSelected, Selected
Function Live Ins: $x10, $x11, $x12

bb.1.entry:
  liveins: $x10, $x11, $x12
  %0:gpr = COPY $x10
  %1:gpr = COPY $x11
  %2:gpr = COPY $x12
  %12:gpr = cv_machhNs_ %0:gpr(tied-def 0), %1:gpr, %2:gpr, 0
  %13:gpr = cv_macs_i16_ %12:gpr(tied-def 0), %1:gpr, %2:gpr
  $x10 = COPY %13:gpr
  PseudoRET implicit $x10

# End machine code for function test_macs32_v2i16.

# *** IR Dump Before Slot index numbering (slotindexes) ***:
# Machine code for function test_macs32_v2i16: IsSSA, TracksLiveness, Legalized, RegBankSelected, Selected
Function Live Ins: $x10, $x11, $x12

bb.1.entry:
  liveins: $x10, $x11, $x12
  %0:gpr = COPY $x10
  %1:gpr = COPY $x11
  %2:gpr = COPY $x12
  %12:gpr = cv_machhNs_ %0:gpr(tied-def 0), %1:gpr, %2:gpr, 0
  %13:gpr = cv_macs_i16_ %12:gpr(tied-def 0), %1:gpr, %2:gpr
  $x10 = COPY %13:gpr
  PseudoRET implicit $x10

# End machine code for function test_macs32_v2i16.

# Machine code for function test_macs32_v2i16: IsSSA, TracksLiveness, Legalized, RegBankSelected, Selected
Function Live Ins: $x10, $x11, $x12

0B	bb.1.entry:
	  liveins: $x10, $x11, $x12
16B	  %0:gpr = COPY $x10
32B	  %1:gpr = COPY $x11
48B	  %2:gpr = COPY $x12
64B	  %12:gpr = cv_machhNs_ %0:gpr(tied-def 0), %1:gpr, %2:gpr, 0
80B	  %13:gpr = cv_macs_i16_ %12:gpr(tied-def 0), %1:gpr, %2:gpr
96B	  $x10 = COPY %13:gpr
112B	  PseudoRET implicit $x10

# End machine code for function test_macs32_v2i16.

# *** IR Dump After Slot index numbering (slotindexes) ***:
# Machine code for function test_macs32_v2i16: IsSSA, TracksLiveness, Legalized, RegBankSelected, Selected
Function Live Ins: $x10, $x11, $x12

0B	bb.1.entry:
	  liveins: $x10, $x11, $x12
16B	  %0:gpr = COPY $x10
32B	  %1:gpr = COPY $x11
48B	  %2:gpr = COPY $x12
64B	  %12:gpr = cv_machhNs_ %0:gpr(tied-def 0), %1:gpr, %2:gpr, 0
80B	  %13:gpr = cv_macs_i16_ %12:gpr(tied-def 0), %1:gpr, %2:gpr
96B	  $x10 = COPY %13:gpr
112B	  PseudoRET implicit $x10

# End machine code for function test_macs32_v2i16.

# *** IR Dump Before Merge disjoint stack slots (stack-coloring) ***:
# Machine code for function test_macs32_v2i16: IsSSA, TracksLiveness, Legalized, RegBankSelected, Selected
Function Live Ins: $x10, $x11, $x12

0B	bb.1.entry:
	  liveins: $x10, $x11, $x12
16B	  %0:gpr = COPY $x10
32B	  %1:gpr = COPY $x11
48B	  %2:gpr = COPY $x12
64B	  %12:gpr = cv_machhNs_ %0:gpr(tied-def 0), %1:gpr, %2:gpr, 0
80B	  %13:gpr = cv_macs_i16_ %12:gpr(tied-def 0), %1:gpr, %2:gpr
96B	  $x10 = COPY %13:gpr
112B	  PseudoRET implicit $x10

# End machine code for function test_macs32_v2i16.

********** Stack Coloring **********
********** Function: test_macs32_v2i16
# *** IR Dump After Merge disjoint stack slots (stack-coloring) ***:
# Machine code for function test_macs32_v2i16: IsSSA, TracksLiveness, Legalized, RegBankSelected, Selected
Function Live Ins: $x10, $x11, $x12

bb.1.entry:
  liveins: $x10, $x11, $x12
  %0:gpr = COPY $x10
  %1:gpr = COPY $x11
  %2:gpr = COPY $x12
  %12:gpr = cv_machhNs_ %0:gpr(tied-def 0), %1:gpr, %2:gpr, 0
  %13:gpr = cv_macs_i16_ %12:gpr(tied-def 0), %1:gpr, %2:gpr
  $x10 = COPY %13:gpr
  PseudoRET implicit $x10

# End machine code for function test_macs32_v2i16.

# *** IR Dump Before Local Stack Slot Allocation (localstackalloc) ***:
# Machine code for function test_macs32_v2i16: IsSSA, TracksLiveness, Legalized, RegBankSelected, Selected
Function Live Ins: $x10, $x11, $x12

bb.1.entry:
  liveins: $x10, $x11, $x12
  %0:gpr = COPY $x10
  %1:gpr = COPY $x11
  %2:gpr = COPY $x12
  %12:gpr = cv_machhNs_ %0:gpr(tied-def 0), %1:gpr, %2:gpr, 0
  %13:gpr = cv_macs_i16_ %12:gpr(tied-def 0), %1:gpr, %2:gpr
  $x10 = COPY %13:gpr
  PseudoRET implicit $x10

# End machine code for function test_macs32_v2i16.

# *** IR Dump After Local Stack Slot Allocation (localstackalloc) ***:
# Machine code for function test_macs32_v2i16: IsSSA, TracksLiveness, Legalized, RegBankSelected, Selected
Function Live Ins: $x10, $x11, $x12

bb.1.entry:
  liveins: $x10, $x11, $x12
  %0:gpr = COPY $x10
  %1:gpr = COPY $x11
  %2:gpr = COPY $x12
  %12:gpr = cv_machhNs_ %0:gpr(tied-def 0), %1:gpr, %2:gpr, 0
  %13:gpr = cv_macs_i16_ %12:gpr(tied-def 0), %1:gpr, %2:gpr
  $x10 = COPY %13:gpr
  PseudoRET implicit $x10

# End machine code for function test_macs32_v2i16.

# *** IR Dump Before Remove dead machine instructions (dead-mi-elimination) ***:
# Machine code for function test_macs32_v2i16: IsSSA, TracksLiveness, Legalized, RegBankSelected, Selected
Function Live Ins: $x10, $x11, $x12

bb.1.entry:
  liveins: $x10, $x11, $x12
  %0:gpr = COPY $x10
  %1:gpr = COPY $x11
  %2:gpr = COPY $x12
  %12:gpr = cv_machhNs_ %0:gpr(tied-def 0), %1:gpr, %2:gpr, 0
  %13:gpr = cv_macs_i16_ %12:gpr(tied-def 0), %1:gpr, %2:gpr
  $x10 = COPY %13:gpr
  PseudoRET implicit $x10

# End machine code for function test_macs32_v2i16.

# *** IR Dump After Remove dead machine instructions (dead-mi-elimination) ***:
# Machine code for function test_macs32_v2i16: IsSSA, TracksLiveness, Legalized, RegBankSelected, Selected
Function Live Ins: $x10, $x11, $x12

bb.1.entry:
  liveins: $x10, $x11, $x12
  %0:gpr = COPY $x10
  %1:gpr = COPY $x11
  %2:gpr = COPY $x12
  %12:gpr = cv_machhNs_ %0:gpr(tied-def 0), %1:gpr, %2:gpr, 0
  %13:gpr = cv_macs_i16_ %12:gpr(tied-def 0), %1:gpr, %2:gpr
  $x10 = COPY %13:gpr
  PseudoRET implicit $x10

# End machine code for function test_macs32_v2i16.


block-frequency: test_macs32_v2i16
==================================
reverse-post-order-traversal
 - 0: BB1[entry]
loop-detection
compute-mass-in-function
 - node: BB1[entry]
  => mass:  ffffffffffffffff
float-to-int: min = 1.0, max = 1.0, factor = 18014398509481984.0
 - BB1[entry]: float = 1.0, scaled = 18014398509481984.0, int = 18014398509481984
block-frequency-info: test_macs32_v2i16
 - BB1[entry]: float = 1.0, int = 18014398509481984

# *** IR Dump Before Early Machine Loop Invariant Code Motion (early-machinelicm) ***:
# Machine code for function test_macs32_v2i16: IsSSA, TracksLiveness, Legalized, RegBankSelected, Selected
Function Live Ins: $x10, $x11, $x12

bb.1.entry:
  liveins: $x10, $x11, $x12
  %0:gpr = COPY $x10
  %1:gpr = COPY $x11
  %2:gpr = COPY $x12
  %12:gpr = cv_machhNs_ %0:gpr(tied-def 0), %1:gpr, %2:gpr, 0
  %13:gpr = cv_macs_i16_ %12:gpr(tied-def 0), %1:gpr, %2:gpr
  $x10 = COPY %13:gpr
  PseudoRET implicit $x10

# End machine code for function test_macs32_v2i16.

******** Pre-regalloc Machine LICM: test_macs32_v2i16 ********
# *** IR Dump After Early Machine Loop Invariant Code Motion (early-machinelicm) ***:
# Machine code for function test_macs32_v2i16: IsSSA, TracksLiveness, Legalized, RegBankSelected, Selected
Function Live Ins: $x10, $x11, $x12

bb.1.entry:
  liveins: $x10, $x11, $x12
  %0:gpr = COPY $x10
  %1:gpr = COPY $x11
  %2:gpr = COPY $x12
  %12:gpr = cv_machhNs_ %0:gpr(tied-def 0), %1:gpr, %2:gpr, 0
  %13:gpr = cv_macs_i16_ %12:gpr(tied-def 0), %1:gpr, %2:gpr
  $x10 = COPY %13:gpr
  PseudoRET implicit $x10

# End machine code for function test_macs32_v2i16.


block-frequency: test_macs32_v2i16
==================================
reverse-post-order-traversal
 - 0: BB1[entry]
loop-detection
compute-mass-in-function
 - node: BB1[entry]
  => mass:  ffffffffffffffff
float-to-int: min = 1.0, max = 1.0, factor = 18014398509481984.0
 - BB1[entry]: float = 1.0, scaled = 18014398509481984.0, int = 18014398509481984
block-frequency-info: test_macs32_v2i16
 - BB1[entry]: float = 1.0, int = 18014398509481984

# *** IR Dump Before Machine Common Subexpression Elimination (machine-cse) ***:
# Machine code for function test_macs32_v2i16: IsSSA, TracksLiveness, Legalized, RegBankSelected, Selected
Function Live Ins: $x10, $x11, $x12

bb.1.entry:
  liveins: $x10, $x11, $x12
  %0:gpr = COPY $x10
  %1:gpr = COPY $x11
  %2:gpr = COPY $x12
  %12:gpr = cv_machhNs_ %0:gpr(tied-def 0), %1:gpr, %2:gpr, 0
  %13:gpr = cv_macs_i16_ %12:gpr(tied-def 0), %1:gpr, %2:gpr
  $x10 = COPY %13:gpr
  PseudoRET implicit $x10

# End machine code for function test_macs32_v2i16.

Entering: entry
Exiting: entry
# *** IR Dump After Machine Common Subexpression Elimination (machine-cse) ***:
# Machine code for function test_macs32_v2i16: IsSSA, TracksLiveness, Legalized, RegBankSelected, Selected
Function Live Ins: $x10, $x11, $x12

bb.1.entry:
  liveins: $x10, $x11, $x12
  %0:gpr = COPY $x10
  %1:gpr = COPY $x11
  %2:gpr = COPY $x12
  %12:gpr = cv_machhNs_ %0:gpr(tied-def 0), %1:gpr, %2:gpr, 0
  %13:gpr = cv_macs_i16_ %12:gpr(tied-def 0), %1:gpr, %2:gpr
  $x10 = COPY %13:gpr
  PseudoRET implicit $x10

# End machine code for function test_macs32_v2i16.

		Looking for trivial roots
Found a new trivial root: %bb.1
Last visited node: %bb.1
		Looking for non-trivial roots
Total: 1, Num: 2
Discovered CFG nodes:
0: nullptr
1: nullptr
2: %bb.1
Found roots: %bb.1 
Computing cycles for function: test_macs32_v2i16
Entry block: bb.1.entry
DFS visiting block: bb.1.entry
  first encountered at depth 1
  preorder number: 1
DFS visiting block: bb.1.entry
  ended at 1
Preorder:
  bb.1.entry: 0
# *** IR Dump Before Machine code sinking (machine-sink) ***:
# Machine code for function test_macs32_v2i16: IsSSA, TracksLiveness, Legalized, RegBankSelected, Selected
Function Live Ins: $x10, $x11, $x12

bb.1.entry:
  liveins: $x10, $x11, $x12
  %0:gpr = COPY $x10
  %1:gpr = COPY $x11
  %2:gpr = COPY $x12
  %12:gpr = cv_machhNs_ %0:gpr(tied-def 0), %1:gpr, %2:gpr, 0
  %13:gpr = cv_macs_i16_ %12:gpr(tied-def 0), %1:gpr, %2:gpr
  $x10 = COPY %13:gpr
  PseudoRET implicit $x10

# End machine code for function test_macs32_v2i16.

******** Machine Sinking ********
# *** IR Dump After Machine code sinking (machine-sink) ***:
# Machine code for function test_macs32_v2i16: IsSSA, TracksLiveness, Legalized, RegBankSelected, Selected
Function Live Ins: $x10, $x11, $x12

bb.1.entry:
  liveins: $x10, $x11, $x12
  %0:gpr = COPY $x10
  %1:gpr = COPY $x11
  %2:gpr = COPY $x12
  %12:gpr = cv_machhNs_ %0:gpr(tied-def 0), %1:gpr, %2:gpr, 0
  %13:gpr = cv_macs_i16_ %12:gpr(tied-def 0), %1:gpr, %2:gpr
  $x10 = COPY %13:gpr
  PseudoRET implicit $x10

# End machine code for function test_macs32_v2i16.

# *** IR Dump Before Peephole Optimizations (peephole-opt) ***:
# Machine code for function test_macs32_v2i16: IsSSA, TracksLiveness, Legalized, RegBankSelected, Selected
Function Live Ins: $x10, $x11, $x12

bb.1.entry:
  liveins: $x10, $x11, $x12
  %0:gpr = COPY $x10
  %1:gpr = COPY $x11
  %2:gpr = COPY $x12
  %12:gpr = cv_machhNs_ %0:gpr(tied-def 0), %1:gpr, %2:gpr, 0
  %13:gpr = cv_macs_i16_ %12:gpr(tied-def 0), %1:gpr, %2:gpr
  $x10 = COPY %13:gpr
  PseudoRET implicit $x10

# End machine code for function test_macs32_v2i16.

********** PEEPHOLE OPTIMIZER **********
********** Function: test_macs32_v2i16
# *** IR Dump After Peephole Optimizations (peephole-opt) ***:
# Machine code for function test_macs32_v2i16: IsSSA, TracksLiveness, Legalized, RegBankSelected, Selected
Function Live Ins: $x10, $x11, $x12

bb.1.entry:
  liveins: $x10, $x11, $x12
  %0:gpr = COPY $x10
  %1:gpr = COPY $x11
  %2:gpr = COPY $x12
  %12:gpr = cv_machhNs_ %0:gpr(tied-def 0), %1:gpr, %2:gpr, 0
  %13:gpr = cv_macs_i16_ %12:gpr(tied-def 0), %1:gpr, %2:gpr
  $x10 = COPY %13:gpr
  PseudoRET implicit $x10

# End machine code for function test_macs32_v2i16.

# *** IR Dump Before Remove dead machine instructions (dead-mi-elimination) ***:
# Machine code for function test_macs32_v2i16: IsSSA, TracksLiveness, Legalized, RegBankSelected, Selected
Function Live Ins: $x10, $x11, $x12

bb.1.entry:
  liveins: $x10, $x11, $x12
  %0:gpr = COPY $x10
  %1:gpr = COPY $x11
  %2:gpr = COPY $x12
  %12:gpr = cv_machhNs_ %0:gpr(tied-def 0), %1:gpr, %2:gpr, 0
  %13:gpr = cv_macs_i16_ %12:gpr(tied-def 0), %1:gpr, %2:gpr
  $x10 = COPY %13:gpr
  PseudoRET implicit $x10

# End machine code for function test_macs32_v2i16.

# *** IR Dump After Remove dead machine instructions (dead-mi-elimination) ***:
# Machine code for function test_macs32_v2i16: IsSSA, TracksLiveness, Legalized, RegBankSelected, Selected
Function Live Ins: $x10, $x11, $x12

bb.1.entry:
  liveins: $x10, $x11, $x12
  %0:gpr = COPY $x10
  %1:gpr = COPY $x11
  %2:gpr = COPY $x12
  %12:gpr = cv_machhNs_ %0:gpr(tied-def 0), %1:gpr, %2:gpr, 0
  %13:gpr = cv_macs_i16_ %12:gpr(tied-def 0), %1:gpr, %2:gpr
  $x10 = COPY %13:gpr
  PseudoRET implicit $x10

# End machine code for function test_macs32_v2i16.

# *** IR Dump Before Machine InstCombiner (machine-combiner) ***:
# Machine code for function test_macs32_v2i16: IsSSA, TracksLiveness, Legalized, RegBankSelected, Selected
Function Live Ins: $x10, $x11, $x12

bb.1.entry:
  liveins: $x10, $x11, $x12
  %0:gpr = COPY $x10
  %1:gpr = COPY $x11
  %2:gpr = COPY $x12
  %12:gpr = cv_machhNs_ %0:gpr(tied-def 0), %1:gpr, %2:gpr, 0
  %13:gpr = cv_macs_i16_ %12:gpr(tied-def 0), %1:gpr, %2:gpr
  $x10 = COPY %13:gpr
  PseudoRET implicit $x10

# End machine code for function test_macs32_v2i16.

Machine InstCombiner: test_macs32_v2i16
Combining MBB entry
# *** IR Dump After Machine InstCombiner (machine-combiner) ***:
# Machine code for function test_macs32_v2i16: IsSSA, TracksLiveness, Legalized, RegBankSelected, Selected
Function Live Ins: $x10, $x11, $x12

bb.1.entry:
  liveins: $x10, $x11, $x12
  %0:gpr = COPY $x10
  %1:gpr = COPY $x11
  %2:gpr = COPY $x12
  %12:gpr = cv_machhNs_ %0:gpr(tied-def 0), %1:gpr, %2:gpr, 0
  %13:gpr = cv_macs_i16_ %12:gpr(tied-def 0), %1:gpr, %2:gpr
  $x10 = COPY %13:gpr
  PseudoRET implicit $x10

# End machine code for function test_macs32_v2i16.

# *** IR Dump Before RISC-V Pre-RA pseudo instruction expansion pass (riscv-prera-expand-pseudo) ***:
# Machine code for function test_macs32_v2i16: IsSSA, TracksLiveness, Legalized, RegBankSelected, Selected
Function Live Ins: $x10, $x11, $x12

bb.1.entry:
  liveins: $x10, $x11, $x12
  %0:gpr = COPY $x10
  %1:gpr = COPY $x11
  %2:gpr = COPY $x12
  %12:gpr = cv_machhNs_ %0:gpr(tied-def 0), %1:gpr, %2:gpr, 0
  %13:gpr = cv_macs_i16_ %12:gpr(tied-def 0), %1:gpr, %2:gpr
  $x10 = COPY %13:gpr
  PseudoRET implicit $x10

# End machine code for function test_macs32_v2i16.

# *** IR Dump After RISC-V Pre-RA pseudo instruction expansion pass (riscv-prera-expand-pseudo) ***:
# Machine code for function test_macs32_v2i16: IsSSA, TracksLiveness, Legalized, RegBankSelected, Selected
Function Live Ins: $x10, $x11, $x12

bb.1.entry:
  liveins: $x10, $x11, $x12
  %0:gpr = COPY $x10
  %1:gpr = COPY $x11
  %2:gpr = COPY $x12
  %12:gpr = cv_machhNs_ %0:gpr(tied-def 0), %1:gpr, %2:gpr, 0
  %13:gpr = cv_macs_i16_ %12:gpr(tied-def 0), %1:gpr, %2:gpr
  $x10 = COPY %13:gpr
  PseudoRET implicit $x10

# End machine code for function test_macs32_v2i16.

# *** IR Dump Before RISC-V Merge Base Offset (riscv-merge-base-offset) ***:
# Machine code for function test_macs32_v2i16: IsSSA, TracksLiveness, Legalized, RegBankSelected, Selected
Function Live Ins: $x10, $x11, $x12

bb.1.entry:
  liveins: $x10, $x11, $x12
  %0:gpr = COPY $x10
  %1:gpr = COPY $x11
  %2:gpr = COPY $x12
  %12:gpr = cv_machhNs_ %0:gpr(tied-def 0), %1:gpr, %2:gpr, 0
  %13:gpr = cv_macs_i16_ %12:gpr(tied-def 0), %1:gpr, %2:gpr
  $x10 = COPY %13:gpr
  PseudoRET implicit $x10

# End machine code for function test_macs32_v2i16.

MBB: entry
# *** IR Dump After RISC-V Merge Base Offset (riscv-merge-base-offset) ***:
# Machine code for function test_macs32_v2i16: IsSSA, TracksLiveness, Legalized, RegBankSelected, Selected
Function Live Ins: $x10, $x11, $x12

bb.1.entry:
  liveins: $x10, $x11, $x12
  %0:gpr = COPY $x10
  %1:gpr = COPY $x11
  %2:gpr = COPY $x12
  %12:gpr = cv_machhNs_ %0:gpr(tied-def 0), %1:gpr, %2:gpr, 0
  %13:gpr = cv_macs_i16_ %12:gpr(tied-def 0), %1:gpr, %2:gpr
  $x10 = COPY %13:gpr
  PseudoRET implicit $x10

# End machine code for function test_macs32_v2i16.

# *** IR Dump Before RISC-V Insert VSETVLI pass (riscv-insert-vsetvli) ***:
# Machine code for function test_macs32_v2i16: IsSSA, TracksLiveness, Legalized, RegBankSelected, Selected
Function Live Ins: $x10, $x11, $x12

bb.1.entry:
  liveins: $x10, $x11, $x12
  %0:gpr = COPY $x10
  %1:gpr = COPY $x11
  %2:gpr = COPY $x12
  %12:gpr = cv_machhNs_ %0:gpr(tied-def 0), %1:gpr, %2:gpr, 0
  %13:gpr = cv_macs_i16_ %12:gpr(tied-def 0), %1:gpr, %2:gpr
  $x10 = COPY %13:gpr
  PseudoRET implicit $x10

# End machine code for function test_macs32_v2i16.

# *** IR Dump After RISC-V Insert VSETVLI pass (riscv-insert-vsetvli) ***:
# Machine code for function test_macs32_v2i16: IsSSA, TracksLiveness, Legalized, RegBankSelected, Selected
Function Live Ins: $x10, $x11, $x12

bb.1.entry:
  liveins: $x10, $x11, $x12
  %0:gpr = COPY $x10
  %1:gpr = COPY $x11
  %2:gpr = COPY $x12
  %12:gpr = cv_machhNs_ %0:gpr(tied-def 0), %1:gpr, %2:gpr, 0
  %13:gpr = cv_macs_i16_ %12:gpr(tied-def 0), %1:gpr, %2:gpr
  $x10 = COPY %13:gpr
  PseudoRET implicit $x10

# End machine code for function test_macs32_v2i16.

# *** IR Dump Before RISC-V Dead register definitions (riscv-dead-defs) ***:
# Machine code for function test_macs32_v2i16: IsSSA, TracksLiveness, Legalized, RegBankSelected, Selected
Function Live Ins: $x10, $x11, $x12

bb.1.entry:
  liveins: $x10, $x11, $x12
  %0:gpr = COPY $x10
  %1:gpr = COPY $x11
  %2:gpr = COPY $x12
  %12:gpr = cv_machhNs_ %0:gpr(tied-def 0), %1:gpr, %2:gpr, 0
  %13:gpr = cv_macs_i16_ %12:gpr(tied-def 0), %1:gpr, %2:gpr
  $x10 = COPY %13:gpr
  PseudoRET implicit $x10

# End machine code for function test_macs32_v2i16.

***** RISCVDeadRegisterDefinitions *****
# *** IR Dump After RISC-V Dead register definitions (riscv-dead-defs) ***:
# Machine code for function test_macs32_v2i16: IsSSA, TracksLiveness, Legalized, RegBankSelected, Selected
Function Live Ins: $x10, $x11, $x12

bb.1.entry:
  liveins: $x10, $x11, $x12
  %0:gpr = COPY $x10
  %1:gpr = COPY $x11
  %2:gpr = COPY $x12
  %12:gpr = cv_machhNs_ %0:gpr(tied-def 0), %1:gpr, %2:gpr, 0
  %13:gpr = cv_macs_i16_ %12:gpr(tied-def 0), %1:gpr, %2:gpr
  $x10 = COPY %13:gpr
  PseudoRET implicit $x10

# End machine code for function test_macs32_v2i16.

# *** IR Dump Before RISC-V Insert Read/Write CSR Pass (riscv-insert-read-write-csr) ***:
# Machine code for function test_macs32_v2i16: IsSSA, TracksLiveness, Legalized, RegBankSelected, Selected
Function Live Ins: $x10, $x11, $x12

bb.1.entry:
  liveins: $x10, $x11, $x12
  %0:gpr = COPY $x10
  %1:gpr = COPY $x11
  %2:gpr = COPY $x12
  %12:gpr = cv_machhNs_ %0:gpr(tied-def 0), %1:gpr, %2:gpr, 0
  %13:gpr = cv_macs_i16_ %12:gpr(tied-def 0), %1:gpr, %2:gpr
  $x10 = COPY %13:gpr
  PseudoRET implicit $x10

# End machine code for function test_macs32_v2i16.

# *** IR Dump After RISC-V Insert Read/Write CSR Pass (riscv-insert-read-write-csr) ***:
# Machine code for function test_macs32_v2i16: IsSSA, TracksLiveness, Legalized, RegBankSelected, Selected
Function Live Ins: $x10, $x11, $x12

bb.1.entry:
  liveins: $x10, $x11, $x12
  %0:gpr = COPY $x10
  %1:gpr = COPY $x11
  %2:gpr = COPY $x12
  %12:gpr = cv_machhNs_ %0:gpr(tied-def 0), %1:gpr, %2:gpr, 0
  %13:gpr = cv_macs_i16_ %12:gpr(tied-def 0), %1:gpr, %2:gpr
  $x10 = COPY %13:gpr
  PseudoRET implicit $x10

# End machine code for function test_macs32_v2i16.

# *** IR Dump Before RISC-V Insert Write VXRM Pass (riscv-insert-write-vxrm) ***:
# Machine code for function test_macs32_v2i16: IsSSA, TracksLiveness, Legalized, RegBankSelected, Selected
Function Live Ins: $x10, $x11, $x12

bb.1.entry:
  liveins: $x10, $x11, $x12
  %0:gpr = COPY $x10
  %1:gpr = COPY $x11
  %2:gpr = COPY $x12
  %12:gpr = cv_machhNs_ %0:gpr(tied-def 0), %1:gpr, %2:gpr, 0
  %13:gpr = cv_macs_i16_ %12:gpr(tied-def 0), %1:gpr, %2:gpr
  $x10 = COPY %13:gpr
  PseudoRET implicit $x10

# End machine code for function test_macs32_v2i16.

# *** IR Dump After RISC-V Insert Write VXRM Pass (riscv-insert-write-vxrm) ***:
# Machine code for function test_macs32_v2i16: IsSSA, TracksLiveness, Legalized, RegBankSelected, Selected
Function Live Ins: $x10, $x11, $x12

bb.1.entry:
  liveins: $x10, $x11, $x12
  %0:gpr = COPY $x10
  %1:gpr = COPY $x11
  %2:gpr = COPY $x12
  %12:gpr = cv_machhNs_ %0:gpr(tied-def 0), %1:gpr, %2:gpr, 0
  %13:gpr = cv_macs_i16_ %12:gpr(tied-def 0), %1:gpr, %2:gpr
  $x10 = COPY %13:gpr
  PseudoRET implicit $x10

# End machine code for function test_macs32_v2i16.

# *** IR Dump Before Detect Dead Lanes (detect-dead-lanes) ***:
# Machine code for function test_macs32_v2i16: IsSSA, TracksLiveness, Legalized, RegBankSelected, Selected
Function Live Ins: $x10, $x11, $x12

bb.1.entry:
  liveins: $x10, $x11, $x12
  %0:gpr = COPY $x10
  %1:gpr = COPY $x11
  %2:gpr = COPY $x12
  %12:gpr = cv_machhNs_ %0:gpr(tied-def 0), %1:gpr, %2:gpr, 0
  %13:gpr = cv_macs_i16_ %12:gpr(tied-def 0), %1:gpr, %2:gpr
  $x10 = COPY %13:gpr
  PseudoRET implicit $x10

# End machine code for function test_macs32_v2i16.

Defined/Used lanes:
%0 Used: 0000000000000001 Def: 0000000000000001
%1 Used: 0000000000000001 Def: 0000000000000001
%2 Used: 0000000000000001 Def: 0000000000000001
%3 Used: 0000000000000000 Def: FFFFFFFFFFFFFFFF
%4 Used: 0000000000000000 Def: FFFFFFFFFFFFFFFF
%5 Used: 0000000000000000 Def: FFFFFFFFFFFFFFFF
%6 Used: 0000000000000000 Def: FFFFFFFFFFFFFFFF
%7 Used: 0000000000000000 Def: FFFFFFFFFFFFFFFF
%8 Used: 0000000000000000 Def: FFFFFFFFFFFFFFFF
%9 Used: 0000000000000000 Def: FFFFFFFFFFFFFFFF
%10 Used: 0000000000000000 Def: FFFFFFFFFFFFFFFF
%11 Used: 0000000000000000 Def: FFFFFFFFFFFFFFFF
%12 Used: 0000000000000001 Def: 0000000000000001
%13 Used: 0000000000000001 Def: 0000000000000001
%14 Used: 0000000000000000 Def: FFFFFFFFFFFFFFFF
%15 Used: 0000000000000000 Def: FFFFFFFFFFFFFFFF
%16 Used: 0000000000000000 Def: FFFFFFFFFFFFFFFF
%17 Used: 0000000000000000 Def: FFFFFFFFFFFFFFFF

# *** IR Dump After Detect Dead Lanes (detect-dead-lanes) ***:
# Machine code for function test_macs32_v2i16: IsSSA, TracksLiveness, Legalized, RegBankSelected, Selected
Function Live Ins: $x10, $x11, $x12

bb.1.entry:
  liveins: $x10, $x11, $x12
  %0:gpr = COPY $x10
  %1:gpr = COPY $x11
  %2:gpr = COPY $x12
  %12:gpr = cv_machhNs_ %0:gpr(tied-def 0), %1:gpr, %2:gpr, 0
  %13:gpr = cv_macs_i16_ %12:gpr(tied-def 0), %1:gpr, %2:gpr
  $x10 = COPY %13:gpr
  PseudoRET implicit $x10

# End machine code for function test_macs32_v2i16.

# *** IR Dump Before RISC-V init undef pass (riscv-init-undef) ***:
# Machine code for function test_macs32_v2i16: IsSSA, TracksLiveness, Legalized, RegBankSelected, Selected
Function Live Ins: $x10, $x11, $x12

bb.1.entry:
  liveins: $x10, $x11, $x12
  %0:gpr = COPY $x10
  %1:gpr = COPY $x11
  %2:gpr = COPY $x12
  %12:gpr = cv_machhNs_ %0:gpr(tied-def 0), %1:gpr, %2:gpr, 0
  %13:gpr = cv_macs_i16_ %12:gpr(tied-def 0), %1:gpr, %2:gpr
  $x10 = COPY %13:gpr
  PseudoRET implicit $x10

# End machine code for function test_macs32_v2i16.

# *** IR Dump After RISC-V init undef pass (riscv-init-undef) ***:
# Machine code for function test_macs32_v2i16: IsSSA, TracksLiveness, Legalized, RegBankSelected, Selected
Function Live Ins: $x10, $x11, $x12

bb.1.entry:
  liveins: $x10, $x11, $x12
  %0:gpr = COPY $x10
  %1:gpr = COPY $x11
  %2:gpr = COPY $x12
  %12:gpr = cv_machhNs_ %0:gpr(tied-def 0), %1:gpr, %2:gpr, 0
  %13:gpr = cv_macs_i16_ %12:gpr(tied-def 0), %1:gpr, %2:gpr
  $x10 = COPY %13:gpr
  PseudoRET implicit $x10

# End machine code for function test_macs32_v2i16.

# *** IR Dump Before Process Implicit Definitions (processimpdefs) ***:
# Machine code for function test_macs32_v2i16: IsSSA, TracksLiveness, Legalized, RegBankSelected, Selected
Function Live Ins: $x10, $x11, $x12

bb.1.entry:
  liveins: $x10, $x11, $x12
  %0:gpr = COPY $x10
  %1:gpr = COPY $x11
  %2:gpr = COPY $x12
  %12:gpr = cv_machhNs_ %0:gpr(tied-def 0), %1:gpr, %2:gpr, 0
  %13:gpr = cv_macs_i16_ %12:gpr(tied-def 0), %1:gpr, %2:gpr
  $x10 = COPY %13:gpr
  PseudoRET implicit $x10

# End machine code for function test_macs32_v2i16.

********** PROCESS IMPLICIT DEFS **********
********** Function: test_macs32_v2i16
# *** IR Dump After Process Implicit Definitions (processimpdefs) ***:
# Machine code for function test_macs32_v2i16: IsSSA, TracksLiveness, Legalized, RegBankSelected, Selected
Function Live Ins: $x10, $x11, $x12

bb.1.entry:
  liveins: $x10, $x11, $x12
  %0:gpr = COPY $x10
  %1:gpr = COPY $x11
  %2:gpr = COPY $x12
  %12:gpr = cv_machhNs_ %0:gpr(tied-def 0), %1:gpr, %2:gpr, 0
  %13:gpr = cv_macs_i16_ %12:gpr(tied-def 0), %1:gpr, %2:gpr
  $x10 = COPY %13:gpr
  PseudoRET implicit $x10

# End machine code for function test_macs32_v2i16.

# *** IR Dump Before Remove unreachable machine basic blocks (unreachable-mbb-elimination) ***:
# Machine code for function test_macs32_v2i16: IsSSA, TracksLiveness, Legalized, RegBankSelected, Selected
Function Live Ins: $x10, $x11, $x12

bb.1.entry:
  liveins: $x10, $x11, $x12
  %0:gpr = COPY $x10
  %1:gpr = COPY $x11
  %2:gpr = COPY $x12
  %12:gpr = cv_machhNs_ %0:gpr(tied-def 0), %1:gpr, %2:gpr, 0
  %13:gpr = cv_macs_i16_ %12:gpr(tied-def 0), %1:gpr, %2:gpr
  $x10 = COPY %13:gpr
  PseudoRET implicit $x10

# End machine code for function test_macs32_v2i16.

# *** IR Dump After Remove unreachable machine basic blocks (unreachable-mbb-elimination) ***:
# Machine code for function test_macs32_v2i16: IsSSA, TracksLiveness, Legalized, RegBankSelected, Selected
Function Live Ins: $x10, $x11, $x12

bb.0.entry:
  liveins: $x10, $x11, $x12
  %0:gpr = COPY $x10
  %1:gpr = COPY $x11
  %2:gpr = COPY $x12
  %12:gpr = cv_machhNs_ %0:gpr(tied-def 0), %1:gpr, %2:gpr, 0
  %13:gpr = cv_macs_i16_ %12:gpr(tied-def 0), %1:gpr, %2:gpr
  $x10 = COPY %13:gpr
  PseudoRET implicit $x10

# End machine code for function test_macs32_v2i16.

# *** IR Dump Before Live Variable Analysis (livevars) ***:
# Machine code for function test_macs32_v2i16: IsSSA, TracksLiveness, Legalized, RegBankSelected, Selected
Function Live Ins: $x10, $x11, $x12

bb.0.entry:
  liveins: $x10, $x11, $x12
  %0:gpr = COPY $x10
  %1:gpr = COPY $x11
  %2:gpr = COPY $x12
  %12:gpr = cv_machhNs_ %0:gpr(tied-def 0), %1:gpr, %2:gpr, 0
  %13:gpr = cv_macs_i16_ %12:gpr(tied-def 0), %1:gpr, %2:gpr
  $x10 = COPY %13:gpr
  PseudoRET implicit $x10

# End machine code for function test_macs32_v2i16.

# *** IR Dump After Live Variable Analysis (livevars) ***:
# Machine code for function test_macs32_v2i16: IsSSA, TracksLiveness, Legalized, RegBankSelected, Selected
Function Live Ins: $x10, $x11, $x12

bb.0.entry:
  liveins: $x10, $x11, $x12
  %0:gpr = COPY killed $x10
  %1:gpr = COPY killed $x11
  %2:gpr = COPY killed $x12
  %12:gpr = cv_machhNs_ killed %0:gpr(tied-def 0), %1:gpr, %2:gpr, 0
  %13:gpr = cv_macs_i16_ killed %12:gpr(tied-def 0), killed %1:gpr, killed %2:gpr
  $x10 = COPY killed %13:gpr
  PseudoRET implicit killed $x10

# End machine code for function test_macs32_v2i16.

# *** IR Dump Before Eliminate PHI nodes for register allocation (phi-node-elimination) ***:
# Machine code for function test_macs32_v2i16: IsSSA, TracksLiveness, Legalized, RegBankSelected, Selected
Function Live Ins: $x10, $x11, $x12

bb.0.entry:
  liveins: $x10, $x11, $x12
  %0:gpr = COPY killed $x10
  %1:gpr = COPY killed $x11
  %2:gpr = COPY killed $x12
  %12:gpr = cv_machhNs_ killed %0:gpr(tied-def 0), %1:gpr, %2:gpr, 0
  %13:gpr = cv_macs_i16_ killed %12:gpr(tied-def 0), killed %1:gpr, killed %2:gpr
  $x10 = COPY killed %13:gpr
  PseudoRET implicit killed $x10

# End machine code for function test_macs32_v2i16.

# *** IR Dump After Eliminate PHI nodes for register allocation (phi-node-elimination) ***:
# Machine code for function test_macs32_v2i16: NoPHIs, TracksLiveness, Legalized, RegBankSelected, Selected
Function Live Ins: $x10, $x11, $x12

bb.0.entry:
  liveins: $x10, $x11, $x12
  %0:gpr = COPY killed $x10
  %1:gpr = COPY killed $x11
  %2:gpr = COPY killed $x12
  %12:gpr = cv_machhNs_ killed %0:gpr(tied-def 0), %1:gpr, %2:gpr, 0
  %13:gpr = cv_macs_i16_ killed %12:gpr(tied-def 0), killed %1:gpr, killed %2:gpr
  $x10 = COPY killed %13:gpr
  PseudoRET implicit killed $x10

# End machine code for function test_macs32_v2i16.

# *** IR Dump Before Two-Address instruction pass (twoaddressinstruction) ***:
# Machine code for function test_macs32_v2i16: NoPHIs, TracksLiveness, Legalized, RegBankSelected, Selected
Function Live Ins: $x10, $x11, $x12

bb.0.entry:
  liveins: $x10, $x11, $x12
  %0:gpr = COPY killed $x10
  %1:gpr = COPY killed $x11
  %2:gpr = COPY killed $x12
  %12:gpr = cv_machhNs_ killed %0:gpr(tied-def 0), %1:gpr, %2:gpr, 0
  %13:gpr = cv_macs_i16_ killed %12:gpr(tied-def 0), killed %1:gpr, killed %2:gpr
  $x10 = COPY killed %13:gpr
  PseudoRET implicit killed $x10

# End machine code for function test_macs32_v2i16.

********** REWRITING TWO-ADDR INSTRS **********
********** Function: test_macs32_v2i16
	%12:gpr = cv_machhNs_ killed %0:gpr(tied-def 0), %1:gpr, %2:gpr, 0
		prepend:	%12:gpr = COPY %0:gpr
		rewrite to:	%12:gpr = cv_machhNs_ %12:gpr(tied-def 0), %1:gpr, %2:gpr, 0
	%13:gpr = cv_macs_i16_ killed %12:gpr(tied-def 0), killed %1:gpr, killed %2:gpr
		prepend:	%13:gpr = COPY %12:gpr
		rewrite to:	%13:gpr = cv_macs_i16_ %13:gpr(tied-def 0), killed %1:gpr, killed %2:gpr
# *** IR Dump After Two-Address instruction pass (twoaddressinstruction) ***:
# Machine code for function test_macs32_v2i16: NoPHIs, TracksLiveness, Legalized, RegBankSelected, Selected, TiedOpsRewritten
Function Live Ins: $x10, $x11, $x12

bb.0.entry:
  liveins: $x10, $x11, $x12
  %0:gpr = COPY killed $x10
  %1:gpr = COPY killed $x11
  %2:gpr = COPY killed $x12
  %12:gpr = COPY killed %0:gpr
  %12:gpr = cv_machhNs_ %12:gpr(tied-def 0), %1:gpr, %2:gpr, 0
  %13:gpr = COPY killed %12:gpr
  %13:gpr = cv_macs_i16_ %13:gpr(tied-def 0), killed %1:gpr, killed %2:gpr
  $x10 = COPY killed %13:gpr
  PseudoRET implicit killed $x10

# End machine code for function test_macs32_v2i16.

# *** IR Dump Before Slot index numbering (slotindexes) ***:
# Machine code for function test_macs32_v2i16: NoPHIs, TracksLiveness, Legalized, RegBankSelected, Selected, TiedOpsRewritten
Function Live Ins: $x10, $x11, $x12

bb.0.entry:
  liveins: $x10, $x11, $x12
  %0:gpr = COPY killed $x10
  %1:gpr = COPY killed $x11
  %2:gpr = COPY killed $x12
  %12:gpr = COPY killed %0:gpr
  %12:gpr = cv_machhNs_ %12:gpr(tied-def 0), %1:gpr, %2:gpr, 0
  %13:gpr = COPY killed %12:gpr
  %13:gpr = cv_macs_i16_ %13:gpr(tied-def 0), killed %1:gpr, killed %2:gpr
  $x10 = COPY killed %13:gpr
  PseudoRET implicit killed $x10

# End machine code for function test_macs32_v2i16.

# Machine code for function test_macs32_v2i16: NoPHIs, TracksLiveness, Legalized, RegBankSelected, Selected, TiedOpsRewritten
Function Live Ins: $x10, $x11, $x12

0B	bb.0.entry:
	  liveins: $x10, $x11, $x12
16B	  %0:gpr = COPY killed $x10
32B	  %1:gpr = COPY killed $x11
48B	  %2:gpr = COPY killed $x12
64B	  %12:gpr = COPY killed %0:gpr
80B	  %12:gpr = cv_machhNs_ %12:gpr(tied-def 0), %1:gpr, %2:gpr, 0
96B	  %13:gpr = COPY killed %12:gpr
112B	  %13:gpr = cv_macs_i16_ %13:gpr(tied-def 0), killed %1:gpr, killed %2:gpr
128B	  $x10 = COPY killed %13:gpr
144B	  PseudoRET implicit killed $x10

# End machine code for function test_macs32_v2i16.

# *** IR Dump After Slot index numbering (slotindexes) ***:
# Machine code for function test_macs32_v2i16: NoPHIs, TracksLiveness, Legalized, RegBankSelected, Selected, TiedOpsRewritten
Function Live Ins: $x10, $x11, $x12

0B	bb.0.entry:
	  liveins: $x10, $x11, $x12
16B	  %0:gpr = COPY killed $x10
32B	  %1:gpr = COPY killed $x11
48B	  %2:gpr = COPY killed $x12
64B	  %12:gpr = COPY killed %0:gpr
80B	  %12:gpr = cv_machhNs_ %12:gpr(tied-def 0), %1:gpr, %2:gpr, 0
96B	  %13:gpr = COPY killed %12:gpr
112B	  %13:gpr = cv_macs_i16_ %13:gpr(tied-def 0), killed %1:gpr, killed %2:gpr
128B	  $x10 = COPY killed %13:gpr
144B	  PseudoRET implicit killed $x10

# End machine code for function test_macs32_v2i16.

# *** IR Dump Before Live Interval Analysis (liveintervals) ***:
# Machine code for function test_macs32_v2i16: NoPHIs, TracksLiveness, Legalized, RegBankSelected, Selected, TiedOpsRewritten
Function Live Ins: $x10, $x11, $x12

0B	bb.0.entry:
	  liveins: $x10, $x11, $x12
16B	  %0:gpr = COPY killed $x10
32B	  %1:gpr = COPY killed $x11
48B	  %2:gpr = COPY killed $x12
64B	  %12:gpr = COPY killed %0:gpr
80B	  %12:gpr = cv_machhNs_ %12:gpr(tied-def 0), %1:gpr, %2:gpr, 0
96B	  %13:gpr = COPY killed %12:gpr
112B	  %13:gpr = cv_macs_i16_ %13:gpr(tied-def 0), killed %1:gpr, killed %2:gpr
128B	  $x10 = COPY killed %13:gpr
144B	  PseudoRET implicit killed $x10

# End machine code for function test_macs32_v2i16.

Computing live-in reg-units in ABI blocks.
0B	%bb.0 X10#0 X11#0 X12#0
Created 3 new intervals.
********** INTERVALS **********
X10 [0B,16r:0)[128r,144r:1) 0@0B-phi 1@128r
X11 [0B,32r:0) 0@0B-phi
X12 [0B,48r:0) 0@0B-phi
%0 [16r,64r:0) 0@16r  weight:0.000000e+00
%1 [32r,112r:0) 0@32r  weight:0.000000e+00
%2 [48r,112r:0) 0@48r  weight:0.000000e+00
%12 [64r,80r:0)[80r,96r:1) 0@64r 1@80r  weight:0.000000e+00
%13 [96r,112r:0)[112r,128r:1) 0@96r 1@112r  weight:0.000000e+00
RegMasks:
********** MACHINEINSTRS **********
# Machine code for function test_macs32_v2i16: NoPHIs, TracksLiveness, Legalized, RegBankSelected, Selected, TiedOpsRewritten
Function Live Ins: $x10, $x11, $x12

0B	bb.0.entry:
	  liveins: $x10, $x11, $x12
16B	  %0:gpr = COPY $x10
32B	  %1:gpr = COPY $x11
48B	  %2:gpr = COPY $x12
64B	  %12:gpr = COPY %0:gpr
80B	  %12:gpr = cv_machhNs_ %12:gpr(tied-def 0), %1:gpr, %2:gpr, 0
96B	  %13:gpr = COPY %12:gpr
112B	  %13:gpr = cv_macs_i16_ %13:gpr(tied-def 0), %1:gpr, %2:gpr
128B	  $x10 = COPY %13:gpr
144B	  PseudoRET implicit $x10

# End machine code for function test_macs32_v2i16.

# *** IR Dump After Live Interval Analysis (liveintervals) ***:
# Machine code for function test_macs32_v2i16: NoPHIs, TracksLiveness, Legalized, RegBankSelected, Selected, TiedOpsRewritten
Function Live Ins: $x10, $x11, $x12

0B	bb.0.entry:
	  liveins: $x10, $x11, $x12
16B	  %0:gpr = COPY $x10
32B	  %1:gpr = COPY $x11
48B	  %2:gpr = COPY $x12
64B	  %12:gpr = COPY %0:gpr
80B	  %12:gpr = cv_machhNs_ %12:gpr(tied-def 0), %1:gpr, %2:gpr, 0
96B	  %13:gpr = COPY %12:gpr
112B	  %13:gpr = cv_macs_i16_ %13:gpr(tied-def 0), %1:gpr, %2:gpr
128B	  $x10 = COPY %13:gpr
144B	  PseudoRET implicit $x10

# End machine code for function test_macs32_v2i16.

# *** IR Dump Before Register Coalescer (register-coalescer) ***:
# Machine code for function test_macs32_v2i16: NoPHIs, TracksLiveness, Legalized, RegBankSelected, Selected, TiedOpsRewritten
Function Live Ins: $x10, $x11, $x12

0B	bb.0.entry:
	  liveins: $x10, $x11, $x12
16B	  %0:gpr = COPY $x10
32B	  %1:gpr = COPY $x11
48B	  %2:gpr = COPY $x12
64B	  %12:gpr = COPY %0:gpr
80B	  %12:gpr = cv_machhNs_ %12:gpr(tied-def 0), %1:gpr, %2:gpr, 0
96B	  %13:gpr = COPY %12:gpr
112B	  %13:gpr = cv_macs_i16_ %13:gpr(tied-def 0), %1:gpr, %2:gpr
128B	  $x10 = COPY %13:gpr
144B	  PseudoRET implicit $x10

# End machine code for function test_macs32_v2i16.

********** REGISTER COALESCER **********
********** Function: test_macs32_v2i16
********** JOINING INTERVALS ***********
entry:
16B	%0:gpr = COPY $x10
	Considering merging %0 with $x10
	Can only merge into reserved registers.
32B	%1:gpr = COPY $x11
	Considering merging %1 with $x11
	Can only merge into reserved registers.
48B	%2:gpr = COPY $x12
	Considering merging %2 with $x12
	Can only merge into reserved registers.
128B	$x10 = COPY %13:gpr
	Considering merging %13 with $x10
	Can only merge into reserved registers.
64B	%12:gpr = COPY %0:gpr
	Considering merging to GPR with %0 in %12
		RHS = %0 [16r,64r:0) 0@16r  weight:0.000000e+00
		LHS = %12 [64r,80r:0)[80r,96r:1) 0@64r 1@80r  weight:0.000000e+00
		merge %12:0@64r into %0:0@16r --> @16r
		erased:	64r	%12:gpr = COPY %0:gpr
AllocationOrder(GPR) = [ $x10 $x11 $x12 $x13 $x14 $x15 $x16 $x17 $x5 $x6 $x7 $x28 $x29 $x30 $x31 $x8 $x9 $x18 $x19 $x20 $x21 $x22 $x23 $x24 $x25 $x26 $x27 $x1 ]
		updated: 16B	%12:gpr = COPY $x10
	Success: %0 -> %12
	Result = %12 [16r,80r:0)[80r,96r:1) 0@16r 1@80r  weight:0.000000e+00
96B	%13:gpr = COPY %12:gpr
	Considering merging to GPR with %12 in %13
		RHS = %12 [16r,80r:0)[80r,96r:1) 0@16r 1@80r  weight:0.000000e+00
		LHS = %13 [96r,112r:0)[112r,128r:1) 0@96r 1@112r  weight:0.000000e+00
		merge %13:0@96r into %12:1@80r --> @80r
		erased:	96r	%13:gpr = COPY %12:gpr
		updated: 16B	%13:gpr = COPY $x10
		updated: 80B	%13:gpr = cv_machhNs_ %13:gpr(tied-def 0), %1:gpr, %2:gpr, 0
	Success: %12 -> %13
	Result = %13 [16r,80r:2)[80r,112r:0)[112r,128r:1) 0@80r 1@112r 2@16r  weight:0.000000e+00
Trying to inflate 0 regs.
********** INTERVALS **********
X10 [0B,16r:0)[128r,144r:1) 0@0B-phi 1@128r
X11 [0B,32r:0) 0@0B-phi
X12 [0B,48r:0) 0@0B-phi
%1 [32r,112r:0) 0@32r  weight:0.000000e+00
%2 [48r,112r:0) 0@48r  weight:0.000000e+00
%13 [16r,80r:2)[80r,112r:0)[112r,128r:1) 0@80r 1@112r 2@16r  weight:0.000000e+00
RegMasks:
********** MACHINEINSTRS **********
# Machine code for function test_macs32_v2i16: NoPHIs, TracksLiveness, Legalized, RegBankSelected, Selected, TiedOpsRewritten
Function Live Ins: $x10, $x11, $x12

0B	bb.0.entry:
	  liveins: $x10, $x11, $x12
16B	  %13:gpr = COPY $x10
32B	  %1:gpr = COPY $x11
48B	  %2:gpr = COPY $x12
80B	  %13:gpr = cv_machhNs_ %13:gpr(tied-def 0), %1:gpr, %2:gpr, 0
112B	  %13:gpr = cv_macs_i16_ %13:gpr(tied-def 0), %1:gpr, %2:gpr
128B	  $x10 = COPY %13:gpr
144B	  PseudoRET implicit $x10

# End machine code for function test_macs32_v2i16.

# *** IR Dump After Register Coalescer (register-coalescer) ***:
# Machine code for function test_macs32_v2i16: NoPHIs, TracksLiveness, Legalized, RegBankSelected, Selected, TiedOpsRewritten
Function Live Ins: $x10, $x11, $x12

0B	bb.0.entry:
	  liveins: $x10, $x11, $x12
16B	  %13:gpr = COPY $x10
32B	  %1:gpr = COPY $x11
48B	  %2:gpr = COPY $x12
80B	  %13:gpr = cv_machhNs_ %13:gpr(tied-def 0), %1:gpr, %2:gpr, 0
112B	  %13:gpr = cv_macs_i16_ %13:gpr(tied-def 0), %1:gpr, %2:gpr
128B	  $x10 = COPY %13:gpr
144B	  PseudoRET implicit $x10

# End machine code for function test_macs32_v2i16.

# *** IR Dump Before Rename Disconnected Subregister Components (rename-independent-subregs) ***:
# Machine code for function test_macs32_v2i16: NoPHIs, TracksLiveness, Legalized, RegBankSelected, Selected, TiedOpsRewritten
Function Live Ins: $x10, $x11, $x12

0B	bb.0.entry:
	  liveins: $x10, $x11, $x12
16B	  %13:gpr = COPY $x10
32B	  %1:gpr = COPY $x11
48B	  %2:gpr = COPY $x12
80B	  %13:gpr = cv_machhNs_ %13:gpr(tied-def 0), %1:gpr, %2:gpr, 0
112B	  %13:gpr = cv_macs_i16_ %13:gpr(tied-def 0), %1:gpr, %2:gpr
128B	  $x10 = COPY %13:gpr
144B	  PseudoRET implicit $x10

# End machine code for function test_macs32_v2i16.

Renaming independent subregister live ranges in test_macs32_v2i16
# *** IR Dump After Rename Disconnected Subregister Components (rename-independent-subregs) ***:
# Machine code for function test_macs32_v2i16: NoPHIs, TracksLiveness, Legalized, RegBankSelected, Selected, TiedOpsRewritten
Function Live Ins: $x10, $x11, $x12

0B	bb.0.entry:
	  liveins: $x10, $x11, $x12
16B	  %13:gpr = COPY $x10
32B	  %1:gpr = COPY $x11
48B	  %2:gpr = COPY $x12
80B	  %13:gpr = cv_machhNs_ %13:gpr(tied-def 0), %1:gpr, %2:gpr, 0
112B	  %13:gpr = cv_macs_i16_ %13:gpr(tied-def 0), %1:gpr, %2:gpr
128B	  $x10 = COPY %13:gpr
144B	  PseudoRET implicit $x10

# End machine code for function test_macs32_v2i16.

# *** IR Dump Before Machine Instruction Scheduler (machine-scheduler) ***:
# Machine code for function test_macs32_v2i16: NoPHIs, TracksLiveness, Legalized, RegBankSelected, Selected, TiedOpsRewritten
Function Live Ins: $x10, $x11, $x12

0B	bb.0.entry:
	  liveins: $x10, $x11, $x12
16B	  %13:gpr = COPY $x10
32B	  %1:gpr = COPY $x11
48B	  %2:gpr = COPY $x12
80B	  %13:gpr = cv_machhNs_ %13:gpr(tied-def 0), %1:gpr, %2:gpr, 0
112B	  %13:gpr = cv_macs_i16_ %13:gpr(tied-def 0), %1:gpr, %2:gpr
128B	  $x10 = COPY %13:gpr
144B	  PseudoRET implicit $x10

# End machine code for function test_macs32_v2i16.

Before MISched:
# Machine code for function test_macs32_v2i16: NoPHIs, TracksLiveness, Legalized, RegBankSelected, Selected, TiedOpsRewritten
Function Live Ins: $x10, $x11, $x12

bb.0.entry:
  liveins: $x10, $x11, $x12
  %13:gpr = COPY $x10
  %1:gpr = COPY $x11
  %2:gpr = COPY $x12
  %13:gpr = cv_machhNs_ %13:gpr(tied-def 0), %1:gpr, %2:gpr, 0
  %13:gpr = cv_macs_i16_ %13:gpr(tied-def 0), %1:gpr, %2:gpr
  $x10 = COPY %13:gpr
  PseudoRET implicit $x10

# End machine code for function test_macs32_v2i16.

AllocationOrder(GPR) = [ $x10 $x11 $x12 $x13 $x14 $x15 $x16 $x17 $x5 $x6 $x7 $x28 $x29 $x30 $x31 $x8 $x9 $x18 $x19 $x20 $x21 $x22 $x23 $x24 $x25 $x26 $x27 $x1 ]
********** MI Scheduling **********
test_macs32_v2i16:%bb.0 entry
  From: %13:gpr = COPY $x10
    To: PseudoRET implicit $x10
 RegionInstrs: 6
ScheduleDAGMILive::schedule starting
GenericScheduler RegionPolicy:  ShouldTrackPressure=0 OnlyTopDown=0 OnlyBottomUp=1
Disabled scoreboard hazard recognizer
Disabled scoreboard hazard recognizer
SU(0):   %13:gpr = COPY $x10
  # preds left       : 0
  # succs left       : 3
  # rdefs left       : 0
  Latency            : 0
  Depth              : 0
  Height             : 3
  Successors:
    SU(3): Data Latency=0 Reg=%13
    SU(3): Out  Latency=1
    SU(5): Anti Latency=0
  Single Issue       : false;
SU(1):   %1:gpr = COPY $x11
  # preds left       : 0
  # succs left       : 2
  # rdefs left       : 0
  Latency            : 0
  Depth              : 0
  Height             : 2
  Successors:
    SU(4): Data Latency=0 Reg=%1
    SU(3): Data Latency=0 Reg=%1
  Single Issue       : false;
SU(2):   %2:gpr = COPY $x12
  # preds left       : 0
  # succs left       : 2
  # rdefs left       : 0
  Latency            : 0
  Depth              : 0
  Height             : 2
  Successors:
    SU(4): Data Latency=0 Reg=%2
    SU(3): Data Latency=0 Reg=%2
  Single Issue       : false;
SU(3):   %13:gpr = cv_machhNs_ %13:gpr(tied-def 0), %1:gpr, %2:gpr, 0
  # preds left       : 4
  # succs left       : 2
  # rdefs left       : 0
  Latency            : 1
  Depth              : 1
  Height             : 2
  Predecessors:
    SU(2): Data Latency=0 Reg=%2
    SU(1): Data Latency=0 Reg=%1
    SU(0): Data Latency=0 Reg=%13
    SU(0): Out  Latency=1
  Successors:
    SU(4): Data Latency=1 Reg=%13
    SU(4): Out  Latency=1
  Single Issue       : false;
SU(4):   %13:gpr = cv_macs_i16_ %13:gpr(tied-def 0), %1:gpr, %2:gpr
  # preds left       : 4
  # succs left       : 1
  # rdefs left       : 0
  Latency            : 1
  Depth              : 2
  Height             : 1
  Predecessors:
    SU(3): Data Latency=1 Reg=%13
    SU(3): Out  Latency=1
    SU(2): Data Latency=0 Reg=%2
    SU(1): Data Latency=0 Reg=%1
  Successors:
    SU(5): Data Latency=1 Reg=%13
  Single Issue       : false;
SU(5):   $x10 = COPY %13:gpr
  # preds left       : 2
  # succs left       : 1
  # rdefs left       : 0
  Latency            : 0
  Depth              : 3
  Height             : 0
  Predecessors:
    SU(4): Data Latency=1 Reg=%13
    SU(0): Anti Latency=0
  Successors:
    ExitSU: Ord  Latency=0 Artificial
  Single Issue       : false;
ExitSU:   PseudoRET implicit $x10
  # preds left       : 1
  # succs left       : 0
  # rdefs left       : 0
  Latency            : 0
  Depth              : 3
  Height             : 0
  Predecessors:
    SU(5): Ord  Latency=0 Artificial
Critical Path(GS-RR ): 3
** ScheduleDAGMILive::schedule picking next node
Queue BotQ.P: 
Queue BotQ.A: 5 
Scheduling SU(5) $x10 = COPY %13:gpr
  Ready @0c
  BotQ.A TopLatency SU(5) 3c
BotQ.A @0c
  Retired: 0
  Executed: 0c
  Critical: 0c, 0 MOps
  ExpectedLatency: 0c
  - Latency limited.
** ScheduleDAGMILive::schedule picking next node
Cycle: 1 BotQ.A
Queue BotQ.P: 
Queue BotQ.A: 4 
Scheduling SU(4) %13:gpr = cv_macs_i16_ %13:gpr(tied-def 0), %1:gpr, %2:gpr
  Ready @1c
  BotQ.A BotLatency SU(4) 1c
  *** Max MOps 1 at cycle 1
Cycle: 2 BotQ.A
BotQ.A @2c
  Retired: 1
  Executed: 2c
  Critical: 1c, 1 MOps
  ExpectedLatency: 1c
  - Latency limited.
** ScheduleDAGMILive::schedule picking next node
Queue BotQ.P: 
Queue BotQ.A: 3 
Scheduling SU(3) %13:gpr = cv_machhNs_ %13:gpr(tied-def 0), %1:gpr, %2:gpr, 0
  Ready @2c
  BotQ.A BotLatency SU(3) 2c
  *** Max MOps 1 at cycle 2
Cycle: 3 BotQ.A
BotQ.A @3c
  Retired: 2
  Executed: 3c
  Critical: 2c, 2 MOps
  ExpectedLatency: 2c
  - Latency limited.
** ScheduleDAGMILive::schedule picking next node
Queue BotQ.P: 
Queue BotQ.A: 2 1 0 
  Cand SU(2) ORDER                              
Pick Bot ORDER     
Scheduling SU(2) %2:gpr = COPY $x12
  Ready @3c
BotQ.A @3c
  Retired: 2
  Executed: 3c
  Critical: 2c, 2 MOps
  ExpectedLatency: 2c
  - Latency limited.
** ScheduleDAGMILive::schedule picking next node
Queue BotQ.P: 
Queue BotQ.A: 0 1 
  Cand SU(0) ORDER                              
  Cand SU(1) ORDER                              
Pick Bot ORDER     
Scheduling SU(1) %1:gpr = COPY $x11
  Ready @3c
BotQ.A @3c
  Retired: 2
  Executed: 3c
  Critical: 2c, 2 MOps
  ExpectedLatency: 2c
  - Latency limited.
** ScheduleDAGMILive::schedule picking next node
Queue BotQ.P: 
Queue BotQ.A: 0 
Scheduling SU(0) %13:gpr = COPY $x10
  Ready @3c
  BotQ.A BotLatency SU(0) 3c
BotQ.A @3c
  Retired: 2
  Executed: 3c
  Critical: 2c, 2 MOps
  ExpectedLatency: 3c
  - Latency limited.
** ScheduleDAGMILive::schedule picking next node
*** Final schedule for %bb.0 ***
SU(0):   %13:gpr = COPY $x10
SU(1):   %1:gpr = COPY $x11
SU(2):   %2:gpr = COPY $x12
SU(3):   %13:gpr = cv_machhNs_ %13:gpr(tied-def 0), %1:gpr, %2:gpr, 0
SU(4):   %13:gpr = cv_macs_i16_ %13:gpr(tied-def 0), %1:gpr, %2:gpr
SU(5):   $x10 = COPY %13:gpr

********** INTERVALS **********
X10 [0B,16r:0)[128r,144r:1) 0@0B-phi 1@128r
X11 [0B,32r:0) 0@0B-phi
X12 [0B,48r:0) 0@0B-phi
%1 [32r,112r:0) 0@32r  weight:0.000000e+00
%2 [48r,112r:0) 0@48r  weight:0.000000e+00
%13 [16r,80r:2)[80r,112r:0)[112r,128r:1) 0@80r 1@112r 2@16r  weight:0.000000e+00
RegMasks:
********** MACHINEINSTRS **********
# Machine code for function test_macs32_v2i16: NoPHIs, TracksLiveness, Legalized, RegBankSelected, Selected, TiedOpsRewritten
Function Live Ins: $x10, $x11, $x12

0B	bb.0.entry:
	  liveins: $x10, $x11, $x12
16B	  %13:gpr = COPY $x10
32B	  %1:gpr = COPY $x11
48B	  %2:gpr = COPY $x12
80B	  %13:gpr = cv_machhNs_ %13:gpr(tied-def 0), %1:gpr, %2:gpr, 0
112B	  %13:gpr = cv_macs_i16_ %13:gpr(tied-def 0), %1:gpr, %2:gpr
128B	  $x10 = COPY %13:gpr
144B	  PseudoRET implicit $x10

# End machine code for function test_macs32_v2i16.

# *** IR Dump After Machine Instruction Scheduler (machine-scheduler) ***:
# Machine code for function test_macs32_v2i16: NoPHIs, TracksLiveness, Legalized, RegBankSelected, Selected, TiedOpsRewritten
Function Live Ins: $x10, $x11, $x12

0B	bb.0.entry:
	  liveins: $x10, $x11, $x12
16B	  %13:gpr = COPY $x10
32B	  %1:gpr = COPY $x11
48B	  %2:gpr = COPY $x12
80B	  %13:gpr = cv_machhNs_ %13:gpr(tied-def 0), %1:gpr, %2:gpr, 0
112B	  %13:gpr = cv_macs_i16_ %13:gpr(tied-def 0), %1:gpr, %2:gpr
128B	  $x10 = COPY %13:gpr
144B	  PseudoRET implicit $x10

# End machine code for function test_macs32_v2i16.


block-frequency: test_macs32_v2i16
==================================
reverse-post-order-traversal
 - 0: BB0[entry]
loop-detection
compute-mass-in-function
 - node: BB0[entry]
  => mass:  ffffffffffffffff
float-to-int: min = 1.0, max = 1.0, factor = 18014398509481984.0
 - BB0[entry]: float = 1.0, scaled = 18014398509481984.0, int = 18014398509481984
block-frequency-info: test_macs32_v2i16
 - BB0[entry]: float = 1.0, int = 18014398509481984

# *** IR Dump Before Debug Variable Analysis (livedebugvars) ***:
# Machine code for function test_macs32_v2i16: NoPHIs, TracksLiveness, Legalized, RegBankSelected, Selected, TiedOpsRewritten
Function Live Ins: $x10, $x11, $x12

0B	bb.0.entry:
	  liveins: $x10, $x11, $x12
16B	  %13:gpr = COPY $x10
32B	  %1:gpr = COPY $x11
48B	  %2:gpr = COPY $x12
80B	  %13:gpr = cv_machhNs_ %13:gpr(tied-def 0), %1:gpr, %2:gpr, 0
112B	  %13:gpr = cv_macs_i16_ %13:gpr(tied-def 0), %1:gpr, %2:gpr
128B	  $x10 = COPY %13:gpr
144B	  PseudoRET implicit $x10

# End machine code for function test_macs32_v2i16.

# *** IR Dump After Debug Variable Analysis (livedebugvars) ***:
# Machine code for function test_macs32_v2i16: NoPHIs, TracksLiveness, Legalized, RegBankSelected, Selected, TiedOpsRewritten, TracksDebugUserValues
Function Live Ins: $x10, $x11, $x12

0B	bb.0.entry:
	  liveins: $x10, $x11, $x12
16B	  %13:gpr = COPY $x10
32B	  %1:gpr = COPY $x11
48B	  %2:gpr = COPY $x12
80B	  %13:gpr = cv_machhNs_ %13:gpr(tied-def 0), %1:gpr, %2:gpr, 0
112B	  %13:gpr = cv_macs_i16_ %13:gpr(tied-def 0), %1:gpr, %2:gpr
128B	  $x10 = COPY %13:gpr
144B	  PseudoRET implicit $x10

# End machine code for function test_macs32_v2i16.

# *** IR Dump Before Live Stack Slot Analysis (livestacks) ***:
# Machine code for function test_macs32_v2i16: NoPHIs, TracksLiveness, Legalized, RegBankSelected, Selected, TiedOpsRewritten, TracksDebugUserValues
Function Live Ins: $x10, $x11, $x12

0B	bb.0.entry:
	  liveins: $x10, $x11, $x12
16B	  %13:gpr = COPY $x10
32B	  %1:gpr = COPY $x11
48B	  %2:gpr = COPY $x12
80B	  %13:gpr = cv_machhNs_ %13:gpr(tied-def 0), %1:gpr, %2:gpr, 0
112B	  %13:gpr = cv_macs_i16_ %13:gpr(tied-def 0), %1:gpr, %2:gpr
128B	  $x10 = COPY %13:gpr
144B	  PseudoRET implicit $x10

# End machine code for function test_macs32_v2i16.

# *** IR Dump After Live Stack Slot Analysis (livestacks) ***:
# Machine code for function test_macs32_v2i16: NoPHIs, TracksLiveness, Legalized, RegBankSelected, Selected, TiedOpsRewritten, TracksDebugUserValues
Function Live Ins: $x10, $x11, $x12

0B	bb.0.entry:
	  liveins: $x10, $x11, $x12
16B	  %13:gpr = COPY $x10
32B	  %1:gpr = COPY $x11
48B	  %2:gpr = COPY $x12
80B	  %13:gpr = cv_machhNs_ %13:gpr(tied-def 0), %1:gpr, %2:gpr, 0
112B	  %13:gpr = cv_macs_i16_ %13:gpr(tied-def 0), %1:gpr, %2:gpr
128B	  $x10 = COPY %13:gpr
144B	  PseudoRET implicit $x10

# End machine code for function test_macs32_v2i16.

# *** IR Dump Before Virtual Register Map (virtregmap) ***:
# Machine code for function test_macs32_v2i16: NoPHIs, TracksLiveness, Legalized, RegBankSelected, Selected, TiedOpsRewritten, TracksDebugUserValues
Function Live Ins: $x10, $x11, $x12

0B	bb.0.entry:
	  liveins: $x10, $x11, $x12
16B	  %13:gpr = COPY $x10
32B	  %1:gpr = COPY $x11
48B	  %2:gpr = COPY $x12
80B	  %13:gpr = cv_machhNs_ %13:gpr(tied-def 0), %1:gpr, %2:gpr, 0
112B	  %13:gpr = cv_macs_i16_ %13:gpr(tied-def 0), %1:gpr, %2:gpr
128B	  $x10 = COPY %13:gpr
144B	  PseudoRET implicit $x10

# End machine code for function test_macs32_v2i16.

# *** IR Dump After Virtual Register Map (virtregmap) ***:
# Machine code for function test_macs32_v2i16: NoPHIs, TracksLiveness, Legalized, RegBankSelected, Selected, TiedOpsRewritten, TracksDebugUserValues
Function Live Ins: $x10, $x11, $x12

0B	bb.0.entry:
	  liveins: $x10, $x11, $x12
16B	  %13:gpr = COPY $x10
32B	  %1:gpr = COPY $x11
48B	  %2:gpr = COPY $x12
80B	  %13:gpr = cv_machhNs_ %13:gpr(tied-def 0), %1:gpr, %2:gpr, 0
112B	  %13:gpr = cv_macs_i16_ %13:gpr(tied-def 0), %1:gpr, %2:gpr
128B	  $x10 = COPY %13:gpr
144B	  PseudoRET implicit $x10

# End machine code for function test_macs32_v2i16.

# *** IR Dump Before Live Register Matrix (liveregmatrix) ***:
# Machine code for function test_macs32_v2i16: NoPHIs, TracksLiveness, Legalized, RegBankSelected, Selected, TiedOpsRewritten, TracksDebugUserValues
Function Live Ins: $x10, $x11, $x12

0B	bb.0.entry:
	  liveins: $x10, $x11, $x12
16B	  %13:gpr = COPY $x10
32B	  %1:gpr = COPY $x11
48B	  %2:gpr = COPY $x12
80B	  %13:gpr = cv_machhNs_ %13:gpr(tied-def 0), %1:gpr, %2:gpr, 0
112B	  %13:gpr = cv_macs_i16_ %13:gpr(tied-def 0), %1:gpr, %2:gpr
128B	  $x10 = COPY %13:gpr
144B	  PseudoRET implicit $x10

# End machine code for function test_macs32_v2i16.

# *** IR Dump After Live Register Matrix (liveregmatrix) ***:
# Machine code for function test_macs32_v2i16: NoPHIs, TracksLiveness, Legalized, RegBankSelected, Selected, TiedOpsRewritten, TracksDebugUserValues
Function Live Ins: $x10, $x11, $x12

0B	bb.0.entry:
	  liveins: $x10, $x11, $x12
16B	  %13:gpr = COPY $x10
32B	  %1:gpr = COPY $x11
48B	  %2:gpr = COPY $x12
80B	  %13:gpr = cv_machhNs_ %13:gpr(tied-def 0), %1:gpr, %2:gpr, 0
112B	  %13:gpr = cv_macs_i16_ %13:gpr(tied-def 0), %1:gpr, %2:gpr
128B	  $x10 = COPY %13:gpr
144B	  PseudoRET implicit $x10

# End machine code for function test_macs32_v2i16.

# *** IR Dump Before Greedy Register Allocator (greedy) ***:
# Machine code for function test_macs32_v2i16: NoPHIs, TracksLiveness, Legalized, RegBankSelected, Selected, TiedOpsRewritten, TracksDebugUserValues
Function Live Ins: $x10, $x11, $x12

0B	bb.0.entry:
	  liveins: $x10, $x11, $x12
16B	  %13:gpr = COPY $x10
32B	  %1:gpr = COPY $x11
48B	  %2:gpr = COPY $x12
80B	  %13:gpr = cv_machhNs_ %13:gpr(tied-def 0), %1:gpr, %2:gpr, 0
112B	  %13:gpr = cv_macs_i16_ %13:gpr(tied-def 0), %1:gpr, %2:gpr
128B	  $x10 = COPY %13:gpr
144B	  PseudoRET implicit $x10

# End machine code for function test_macs32_v2i16.

********** GREEDY REGISTER ALLOCATION **********
********** Function: test_macs32_v2i16
# *** IR Dump After Greedy Register Allocator (greedy) ***:
# Machine code for function test_macs32_v2i16: NoPHIs, TracksLiveness, Legalized, RegBankSelected, Selected, TiedOpsRewritten, TracksDebugUserValues
Function Live Ins: $x10, $x11, $x12

0B	bb.0.entry:
	  liveins: $x10, $x11, $x12
16B	  %13:gpr = COPY $x10
32B	  %1:gpr = COPY $x11
48B	  %2:gpr = COPY $x12
80B	  %13:gpr = cv_machhNs_ %13:gpr(tied-def 0), %1:gpr, %2:gpr, 0
112B	  %13:gpr = cv_macs_i16_ %13:gpr(tied-def 0), %1:gpr, %2:gpr
128B	  $x10 = COPY %13:gpr
144B	  PseudoRET implicit $x10

# End machine code for function test_macs32_v2i16.

# *** IR Dump Before Virtual Register Rewriter (virtregrewriter) ***:
# Machine code for function test_macs32_v2i16: NoPHIs, TracksLiveness, Legalized, RegBankSelected, Selected, TiedOpsRewritten, TracksDebugUserValues
Function Live Ins: $x10, $x11, $x12

0B	bb.0.entry:
	  liveins: $x10, $x11, $x12
16B	  %13:gpr = COPY $x10
32B	  %1:gpr = COPY $x11
48B	  %2:gpr = COPY $x12
80B	  %13:gpr = cv_machhNs_ %13:gpr(tied-def 0), %1:gpr, %2:gpr, 0
112B	  %13:gpr = cv_macs_i16_ %13:gpr(tied-def 0), %1:gpr, %2:gpr
128B	  $x10 = COPY %13:gpr
144B	  PseudoRET implicit $x10

# End machine code for function test_macs32_v2i16.

********** REWRITE VIRTUAL REGISTERS **********
********** Function: test_macs32_v2i16
********** REGISTER MAP **********

0B	bb.0.entry:
	  liveins: $x10, $x11, $x12
16B	  %13:gpr = COPY $x10
32B	  %1:gpr = COPY $x11
48B	  %2:gpr = COPY $x12
80B	  %13:gpr = cv_machhNs_ %13:gpr(tied-def 0), %1:gpr, %2:gpr, 0
112B	  %13:gpr = cv_macs_i16_ %13:gpr(tied-def 0), %1:gpr, %2:gpr
128B	  $x10 = COPY %13:gpr
144B	  PseudoRET implicit $x10
> %13:gpr = COPY $x10
> %1:gpr = COPY $x11
> %2:gpr = COPY $x12
> %13:gpr = cv_machhNs_ %13:gpr(tied-def 0), %1:gpr, %2:gpr, 0
> %13:gpr = cv_macs_i16_ %13:gpr(tied-def 0), %1:gpr, %2:gpr
> $x10 = COPY %13:gpr
> PseudoRET implicit $x10
# *** IR Dump After Virtual Register Rewriter (virtregrewriter) ***:
# Machine code for function test_macs32_v2i16: NoPHIs, TracksLiveness, Legalized, RegBankSelected, Selected, TiedOpsRewritten, TracksDebugUserValues
Function Live Ins: $x10, $x11, $x12

0B	bb.0.entry:
	  liveins: $x10, $x11, $x12
16B	  %13:gpr = COPY $x10
32B	  %1:gpr = COPY $x11
48B	  %2:gpr = COPY $x12
80B	  %13:gpr = cv_machhNs_ %13:gpr(tied-def 0), %1:gpr, %2:gpr, 0
112B	  %13:gpr = cv_macs_i16_ %13:gpr(tied-def 0), %1:gpr, %2:gpr
128B	  $x10 = COPY %13:gpr
144B	  PseudoRET implicit $x10

# End machine code for function test_macs32_v2i16.

# *** IR Dump Before Virtual Register Map (virtregmap) ***:
# Machine code for function test_macs32_v2i16: NoPHIs, TracksLiveness, Legalized, RegBankSelected, Selected, TiedOpsRewritten, TracksDebugUserValues
Function Live Ins: $x10, $x11, $x12

0B	bb.0.entry:
	  liveins: $x10, $x11, $x12
16B	  %13:gpr = COPY $x10
32B	  %1:gpr = COPY $x11
48B	  %2:gpr = COPY $x12
80B	  %13:gpr = cv_machhNs_ %13:gpr(tied-def 0), %1:gpr, %2:gpr, 0
112B	  %13:gpr = cv_macs_i16_ %13:gpr(tied-def 0), %1:gpr, %2:gpr
128B	  $x10 = COPY %13:gpr
144B	  PseudoRET implicit $x10

# End machine code for function test_macs32_v2i16.

# *** IR Dump After Virtual Register Map (virtregmap) ***:
# Machine code for function test_macs32_v2i16: NoPHIs, TracksLiveness, Legalized, RegBankSelected, Selected, TiedOpsRewritten, TracksDebugUserValues
Function Live Ins: $x10, $x11, $x12

0B	bb.0.entry:
	  liveins: $x10, $x11, $x12
16B	  %13:gpr = COPY $x10
32B	  %1:gpr = COPY $x11
48B	  %2:gpr = COPY $x12
80B	  %13:gpr = cv_machhNs_ %13:gpr(tied-def 0), %1:gpr, %2:gpr, 0
112B	  %13:gpr = cv_macs_i16_ %13:gpr(tied-def 0), %1:gpr, %2:gpr
128B	  $x10 = COPY %13:gpr
144B	  PseudoRET implicit $x10

# End machine code for function test_macs32_v2i16.

# *** IR Dump Before Live Register Matrix (liveregmatrix) ***:
# Machine code for function test_macs32_v2i16: NoPHIs, TracksLiveness, Legalized, RegBankSelected, Selected, TiedOpsRewritten, TracksDebugUserValues
Function Live Ins: $x10, $x11, $x12

0B	bb.0.entry:
	  liveins: $x10, $x11, $x12
16B	  %13:gpr = COPY $x10
32B	  %1:gpr = COPY $x11
48B	  %2:gpr = COPY $x12
80B	  %13:gpr = cv_machhNs_ %13:gpr(tied-def 0), %1:gpr, %2:gpr, 0
112B	  %13:gpr = cv_macs_i16_ %13:gpr(tied-def 0), %1:gpr, %2:gpr
128B	  $x10 = COPY %13:gpr
144B	  PseudoRET implicit $x10

# End machine code for function test_macs32_v2i16.

# *** IR Dump After Live Register Matrix (liveregmatrix) ***:
# Machine code for function test_macs32_v2i16: NoPHIs, TracksLiveness, Legalized, RegBankSelected, Selected, TiedOpsRewritten, TracksDebugUserValues
Function Live Ins: $x10, $x11, $x12

0B	bb.0.entry:
	  liveins: $x10, $x11, $x12
16B	  %13:gpr = COPY $x10
32B	  %1:gpr = COPY $x11
48B	  %2:gpr = COPY $x12
80B	  %13:gpr = cv_machhNs_ %13:gpr(tied-def 0), %1:gpr, %2:gpr, 0
112B	  %13:gpr = cv_macs_i16_ %13:gpr(tied-def 0), %1:gpr, %2:gpr
128B	  $x10 = COPY %13:gpr
144B	  PseudoRET implicit $x10

# End machine code for function test_macs32_v2i16.

# *** IR Dump Before Greedy Register Allocator (greedy) ***:
# Machine code for function test_macs32_v2i16: NoPHIs, TracksLiveness, Legalized, RegBankSelected, Selected, TiedOpsRewritten, TracksDebugUserValues
Function Live Ins: $x10, $x11, $x12

0B	bb.0.entry:
	  liveins: $x10, $x11, $x12
16B	  %13:gpr = COPY $x10
32B	  %1:gpr = COPY $x11
48B	  %2:gpr = COPY $x12
80B	  %13:gpr = cv_machhNs_ %13:gpr(tied-def 0), %1:gpr, %2:gpr, 0
112B	  %13:gpr = cv_macs_i16_ %13:gpr(tied-def 0), %1:gpr, %2:gpr
128B	  $x10 = COPY %13:gpr
144B	  PseudoRET implicit $x10

# End machine code for function test_macs32_v2i16.

********** GREEDY REGISTER ALLOCATION **********
********** Function: test_macs32_v2i16
********** Compute Spill Weights **********
********** Function: test_macs32_v2i16
********** INTERVALS **********
X10 [0B,16r:0)[128r,144r:1) 0@0B-phi 1@128r
X11 [0B,32r:0) 0@0B-phi
X12 [0B,48r:0) 0@0B-phi
%1 [32r,112r:0) 0@32r  weight:6.312500e-03
%2 [48r,112r:0) 0@48r  weight:6.530172e-03
%13 [16r,80r:2)[80r,112r:0)[112r,128r:1) 0@80r 1@112r 2@16r  weight:1.183594e-02
RegMasks:
********** MACHINEINSTRS **********
# Machine code for function test_macs32_v2i16: NoPHIs, TracksLiveness, Legalized, RegBankSelected, Selected, TiedOpsRewritten, TracksDebugUserValues
Function Live Ins: $x10, $x11, $x12

0B	bb.0.entry:
	  liveins: $x10, $x11, $x12
16B	  %13:gpr = COPY $x10
32B	  %1:gpr = COPY $x11
48B	  %2:gpr = COPY $x12
80B	  %13:gpr = cv_machhNs_ %13:gpr(tied-def 0), %1:gpr, %2:gpr, 0
112B	  %13:gpr = cv_macs_i16_ %13:gpr(tied-def 0), %1:gpr, %2:gpr
128B	  $x10 = COPY %13:gpr
144B	  PseudoRET implicit $x10

# End machine code for function test_macs32_v2i16.

Enqueuing %1
AllocationOrder(GPR) = [ $x10 $x11 $x12 $x13 $x14 $x15 $x16 $x17 $x5 $x6 $x7 $x28 $x29 $x30 $x31 $x8 $x9 $x18 $x19 $x20 $x21 $x22 $x23 $x24 $x25 $x26 $x27 $x1 ]
Enqueuing %2
Enqueuing %13

selectOrSplit GPR:%13 [16r,80r:2)[80r,112r:0)[112r,128r:1) 0@80r 1@112r 2@16r  weight:1.183594e-02 w=1.183594e-02
hints: $x10
assigning %13 to $x10: X10 [16r,80r:2)[80r,112r:0)[112r,128r:1) 0@80r 1@112r 2@16r

selectOrSplit GPR:%1 [32r,112r:0) 0@32r  weight:6.312500e-03 w=6.312500e-03
hints: $x11
assigning %1 to $x11: X11 [32r,112r:0) 0@32r

selectOrSplit GPR:%2 [48r,112r:0) 0@48r  weight:6.530172e-03 w=6.530172e-03
hints: $x12
assigning %2 to $x12: X12 [48r,112r:0) 0@48r
# *** IR Dump After Greedy Register Allocator (greedy) ***:
# Machine code for function test_macs32_v2i16: NoPHIs, TracksLiveness, Legalized, RegBankSelected, Selected, TiedOpsRewritten, TracksDebugUserValues
Function Live Ins: $x10, $x11, $x12

0B	bb.0.entry:
	  liveins: $x10, $x11, $x12
16B	  %13:gpr = COPY $x10
32B	  %1:gpr = COPY $x11
48B	  %2:gpr = COPY $x12
80B	  %13:gpr = cv_machhNs_ %13:gpr(tied-def 0), %1:gpr, %2:gpr, 0
112B	  %13:gpr = cv_macs_i16_ %13:gpr(tied-def 0), %1:gpr, %2:gpr
128B	  $x10 = COPY %13:gpr
144B	  PseudoRET implicit $x10

# End machine code for function test_macs32_v2i16.

# *** IR Dump Before Virtual Register Rewriter (virtregrewriter) ***:
# Machine code for function test_macs32_v2i16: NoPHIs, TracksLiveness, Legalized, RegBankSelected, Selected, TiedOpsRewritten, TracksDebugUserValues
Function Live Ins: $x10, $x11, $x12

0B	bb.0.entry:
	  liveins: $x10, $x11, $x12
16B	  %13:gpr = COPY $x10
32B	  %1:gpr = COPY $x11
48B	  %2:gpr = COPY $x12
80B	  %13:gpr = cv_machhNs_ %13:gpr(tied-def 0), %1:gpr, %2:gpr, 0
112B	  %13:gpr = cv_macs_i16_ %13:gpr(tied-def 0), %1:gpr, %2:gpr
128B	  $x10 = COPY %13:gpr
144B	  PseudoRET implicit $x10

# End machine code for function test_macs32_v2i16.

********** REWRITE VIRTUAL REGISTERS **********
********** Function: test_macs32_v2i16
********** REGISTER MAP **********
[%1 -> $x11] GPR
[%2 -> $x12] GPR
[%13 -> $x10] GPR

0B	bb.0.entry:
	  liveins: $x10, $x11, $x12
16B	  %13:gpr = COPY $x10
32B	  %1:gpr = COPY $x11
48B	  %2:gpr = COPY $x12
80B	  %13:gpr = cv_machhNs_ killed %13:gpr(tied-def 0), %1:gpr, %2:gpr, 0
112B	  %13:gpr = cv_macs_i16_ killed %13:gpr(tied-def 0), killed %1:gpr, killed %2:gpr
128B	  $x10 = COPY killed %13:gpr
144B	  PseudoRET implicit $x10
> renamable $x10 = COPY $x10
Identity copy: renamable $x10 = COPY $x10
  deleted.
> renamable $x11 = COPY $x11
Identity copy: renamable $x11 = COPY $x11
  deleted.
> renamable $x12 = COPY $x12
Identity copy: renamable $x12 = COPY $x12
  deleted.
> renamable $x10 = cv_machhNs_ killed renamable $x10(tied-def 0), renamable $x11, renamable $x12, 0
> renamable $x10 = cv_macs_i16_ killed renamable $x10(tied-def 0), killed renamable $x11, killed renamable $x12
> $x10 = COPY killed renamable $x10
Identity copy: $x10 = COPY killed renamable $x10
  deleted.
> PseudoRET implicit $x10
# *** IR Dump After Virtual Register Rewriter (virtregrewriter) ***:
# Machine code for function test_macs32_v2i16: NoPHIs, TracksLiveness, NoVRegs, Legalized, RegBankSelected, Selected, TiedOpsRewritten, TracksDebugUserValues
Function Live Ins: $x10, $x11, $x12

0B	bb.0.entry:
	  liveins: $x10, $x11, $x12
80B	  renamable $x10 = cv_machhNs_ killed renamable $x10(tied-def 0), renamable $x11, renamable $x12, 0
112B	  renamable $x10 = cv_macs_i16_ killed renamable $x10(tied-def 0), killed renamable $x11, killed renamable $x12
144B	  PseudoRET implicit $x10

# End machine code for function test_macs32_v2i16.

# *** IR Dump Before Register Allocation Pass Scoring (regallocscoringpass) ***:
# Machine code for function test_macs32_v2i16: NoPHIs, TracksLiveness, NoVRegs, Legalized, RegBankSelected, Selected, TiedOpsRewritten, TracksDebugUserValues
Function Live Ins: $x10, $x11, $x12

0B	bb.0.entry:
	  liveins: $x10, $x11, $x12
80B	  renamable $x10 = cv_machhNs_ killed renamable $x10(tied-def 0), renamable $x11, renamable $x12, 0
112B	  renamable $x10 = cv_macs_i16_ killed renamable $x10(tied-def 0), killed renamable $x11, killed renamable $x12
144B	  PseudoRET implicit $x10

# End machine code for function test_macs32_v2i16.

# *** IR Dump After Register Allocation Pass Scoring (regallocscoringpass) ***:
# Machine code for function test_macs32_v2i16: NoPHIs, TracksLiveness, NoVRegs, Legalized, RegBankSelected, Selected, TiedOpsRewritten, TracksDebugUserValues
Function Live Ins: $x10, $x11, $x12

0B	bb.0.entry:
	  liveins: $x10, $x11, $x12
80B	  renamable $x10 = cv_machhNs_ killed renamable $x10(tied-def 0), renamable $x11, renamable $x12, 0
112B	  renamable $x10 = cv_macs_i16_ killed renamable $x10(tied-def 0), killed renamable $x11, killed renamable $x12
144B	  PseudoRET implicit $x10

# End machine code for function test_macs32_v2i16.

# *** IR Dump Before Stack Slot Coloring (stack-slot-coloring) ***:
# Machine code for function test_macs32_v2i16: NoPHIs, TracksLiveness, NoVRegs, Legalized, RegBankSelected, Selected, TiedOpsRewritten, TracksDebugUserValues
Function Live Ins: $x10, $x11, $x12

0B	bb.0.entry:
	  liveins: $x10, $x11, $x12
80B	  renamable $x10 = cv_machhNs_ killed renamable $x10(tied-def 0), renamable $x11, renamable $x12, 0
112B	  renamable $x10 = cv_macs_i16_ killed renamable $x10(tied-def 0), killed renamable $x11, killed renamable $x12
144B	  PseudoRET implicit $x10

# End machine code for function test_macs32_v2i16.

********** Stack Slot Coloring **********
********** Function: test_macs32_v2i16
# *** IR Dump After Stack Slot Coloring (stack-slot-coloring) ***:
# Machine code for function test_macs32_v2i16: NoPHIs, TracksLiveness, NoVRegs, Legalized, RegBankSelected, Selected, TiedOpsRewritten, TracksDebugUserValues
Function Live Ins: $x10, $x11, $x12

0B	bb.0.entry:
	  liveins: $x10, $x11, $x12
80B	  renamable $x10 = cv_machhNs_ killed renamable $x10(tied-def 0), renamable $x11, renamable $x12, 0
112B	  renamable $x10 = cv_macs_i16_ killed renamable $x10(tied-def 0), killed renamable $x11, killed renamable $x12
144B	  PseudoRET implicit $x10

# End machine code for function test_macs32_v2i16.

# *** IR Dump Before Machine Copy Propagation Pass (machine-cp) ***:
# Machine code for function test_macs32_v2i16: NoPHIs, TracksLiveness, NoVRegs, Legalized, RegBankSelected, Selected, TiedOpsRewritten, TracksDebugUserValues
Function Live Ins: $x10, $x11, $x12

0B	bb.0.entry:
	  liveins: $x10, $x11, $x12
80B	  renamable $x10 = cv_machhNs_ killed renamable $x10(tied-def 0), renamable $x11, renamable $x12, 0
112B	  renamable $x10 = cv_macs_i16_ killed renamable $x10(tied-def 0), killed renamable $x11, killed renamable $x12
144B	  PseudoRET implicit $x10

# End machine code for function test_macs32_v2i16.

MCP: BackwardCopyPropagateBlock entry
MCP: ForwardCopyPropagateBlock entry
# *** IR Dump After Machine Copy Propagation Pass (machine-cp) ***:
# Machine code for function test_macs32_v2i16: NoPHIs, TracksLiveness, NoVRegs, Legalized, RegBankSelected, Selected, TiedOpsRewritten, TracksDebugUserValues
Function Live Ins: $x10, $x11, $x12

bb.0.entry:
  liveins: $x10, $x11, $x12
  renamable $x10 = cv_machhNs_ killed renamable $x10(tied-def 0), renamable $x11, renamable $x12, 0
  renamable $x10 = cv_macs_i16_ killed renamable $x10(tied-def 0), killed renamable $x11, killed renamable $x12
  PseudoRET implicit $x10

# End machine code for function test_macs32_v2i16.

# *** IR Dump Before Machine Loop Invariant Code Motion (machinelicm) ***:
# Machine code for function test_macs32_v2i16: NoPHIs, TracksLiveness, NoVRegs, Legalized, RegBankSelected, Selected, TiedOpsRewritten, TracksDebugUserValues
Function Live Ins: $x10, $x11, $x12

bb.0.entry:
  liveins: $x10, $x11, $x12
  renamable $x10 = cv_machhNs_ killed renamable $x10(tied-def 0), renamable $x11, renamable $x12, 0
  renamable $x10 = cv_macs_i16_ killed renamable $x10(tied-def 0), killed renamable $x11, killed renamable $x12
  PseudoRET implicit $x10

# End machine code for function test_macs32_v2i16.

******** Post-regalloc Machine LICM: test_macs32_v2i16 ********
# *** IR Dump After Machine Loop Invariant Code Motion (machinelicm) ***:
# Machine code for function test_macs32_v2i16: NoPHIs, TracksLiveness, NoVRegs, Legalized, RegBankSelected, Selected, TiedOpsRewritten, TracksDebugUserValues
Function Live Ins: $x10, $x11, $x12

bb.0.entry:
  liveins: $x10, $x11, $x12
  renamable $x10 = cv_machhNs_ killed renamable $x10(tied-def 0), renamable $x11, renamable $x12, 0
  renamable $x10 = cv_macs_i16_ killed renamable $x10(tied-def 0), killed renamable $x11, killed renamable $x12
  PseudoRET implicit $x10

# End machine code for function test_macs32_v2i16.

# *** IR Dump Before RISC-V Redundant Copy Elimination (riscv-copyelim) ***:
# Machine code for function test_macs32_v2i16: NoPHIs, TracksLiveness, NoVRegs, Legalized, RegBankSelected, Selected, TiedOpsRewritten, TracksDebugUserValues
Function Live Ins: $x10, $x11, $x12

bb.0.entry:
  liveins: $x10, $x11, $x12
  renamable $x10 = cv_machhNs_ killed renamable $x10(tied-def 0), renamable $x11, renamable $x12, 0
  renamable $x10 = cv_macs_i16_ killed renamable $x10(tied-def 0), killed renamable $x11, killed renamable $x12
  PseudoRET implicit $x10

# End machine code for function test_macs32_v2i16.

# *** IR Dump After RISC-V Redundant Copy Elimination (riscv-copyelim) ***:
# Machine code for function test_macs32_v2i16: NoPHIs, TracksLiveness, NoVRegs, Legalized, RegBankSelected, Selected, TiedOpsRewritten, TracksDebugUserValues
Function Live Ins: $x10, $x11, $x12

bb.0.entry:
  liveins: $x10, $x11, $x12
  renamable $x10 = cv_machhNs_ killed renamable $x10(tied-def 0), renamable $x11, renamable $x12, 0
  renamable $x10 = cv_macs_i16_ killed renamable $x10(tied-def 0), killed renamable $x11, killed renamable $x12
  PseudoRET implicit $x10

# End machine code for function test_macs32_v2i16.

# *** IR Dump Before Remove Redundant DEBUG_VALUE analysis (removeredundantdebugvalues) ***:
# Machine code for function test_macs32_v2i16: NoPHIs, TracksLiveness, NoVRegs, Legalized, RegBankSelected, Selected, TiedOpsRewritten, TracksDebugUserValues
Function Live Ins: $x10, $x11, $x12

bb.0.entry:
  liveins: $x10, $x11, $x12
  renamable $x10 = cv_machhNs_ killed renamable $x10(tied-def 0), renamable $x11, renamable $x12, 0
  renamable $x10 = cv_macs_i16_ killed renamable $x10(tied-def 0), killed renamable $x11, killed renamable $x12
  PseudoRET implicit $x10

# End machine code for function test_macs32_v2i16.

# *** IR Dump After Remove Redundant DEBUG_VALUE analysis (removeredundantdebugvalues) ***:
# Machine code for function test_macs32_v2i16: NoPHIs, TracksLiveness, NoVRegs, Legalized, RegBankSelected, Selected, TiedOpsRewritten, TracksDebugUserValues
Function Live Ins: $x10, $x11, $x12

bb.0.entry:
  liveins: $x10, $x11, $x12
  renamable $x10 = cv_machhNs_ killed renamable $x10(tied-def 0), renamable $x11, renamable $x12, 0
  renamable $x10 = cv_macs_i16_ killed renamable $x10(tied-def 0), killed renamable $x11, killed renamable $x12
  PseudoRET implicit $x10

# End machine code for function test_macs32_v2i16.

# *** IR Dump Before Fixup Statepoint Caller Saved (fixup-statepoint-caller-saved) ***:
# Machine code for function test_macs32_v2i16: NoPHIs, TracksLiveness, NoVRegs, Legalized, RegBankSelected, Selected, TiedOpsRewritten, TracksDebugUserValues
Function Live Ins: $x10, $x11, $x12

bb.0.entry:
  liveins: $x10, $x11, $x12
  renamable $x10 = cv_machhNs_ killed renamable $x10(tied-def 0), renamable $x11, renamable $x12, 0
  renamable $x10 = cv_macs_i16_ killed renamable $x10(tied-def 0), killed renamable $x11, killed renamable $x12
  PseudoRET implicit $x10

# End machine code for function test_macs32_v2i16.

# *** IR Dump After Fixup Statepoint Caller Saved (fixup-statepoint-caller-saved) ***:
# Machine code for function test_macs32_v2i16: NoPHIs, TracksLiveness, NoVRegs, Legalized, RegBankSelected, Selected, TiedOpsRewritten, TracksDebugUserValues
Function Live Ins: $x10, $x11, $x12

bb.0.entry:
  liveins: $x10, $x11, $x12
  renamable $x10 = cv_machhNs_ killed renamable $x10(tied-def 0), renamable $x11, renamable $x12, 0
  renamable $x10 = cv_macs_i16_ killed renamable $x10(tied-def 0), killed renamable $x11, killed renamable $x12
  PseudoRET implicit $x10

# End machine code for function test_macs32_v2i16.

# *** IR Dump Before PostRA Machine Sink (postra-machine-sink) ***:
# Machine code for function test_macs32_v2i16: NoPHIs, TracksLiveness, NoVRegs, Legalized, RegBankSelected, Selected, TiedOpsRewritten, TracksDebugUserValues
Function Live Ins: $x10, $x11, $x12

bb.0.entry:
  liveins: $x10, $x11, $x12
  renamable $x10 = cv_machhNs_ killed renamable $x10(tied-def 0), renamable $x11, renamable $x12, 0
  renamable $x10 = cv_macs_i16_ killed renamable $x10(tied-def 0), killed renamable $x11, killed renamable $x12
  PseudoRET implicit $x10

# End machine code for function test_macs32_v2i16.

# *** IR Dump After PostRA Machine Sink (postra-machine-sink) ***:
# Machine code for function test_macs32_v2i16: NoPHIs, TracksLiveness, NoVRegs, Legalized, RegBankSelected, Selected, TiedOpsRewritten, TracksDebugUserValues
Function Live Ins: $x10, $x11, $x12

bb.0.entry:
  liveins: $x10, $x11, $x12
  renamable $x10 = cv_machhNs_ killed renamable $x10(tied-def 0), renamable $x11, renamable $x12, 0
  renamable $x10 = cv_macs_i16_ killed renamable $x10(tied-def 0), killed renamable $x11, killed renamable $x12
  PseudoRET implicit $x10

# End machine code for function test_macs32_v2i16.


block-frequency: test_macs32_v2i16
==================================
reverse-post-order-traversal
 - 0: BB0[entry]
loop-detection
compute-mass-in-function
 - node: BB0[entry]
  => mass:  ffffffffffffffff
float-to-int: min = 1.0, max = 1.0, factor = 18014398509481984.0
 - BB0[entry]: float = 1.0, scaled = 18014398509481984.0, int = 18014398509481984
block-frequency-info: test_macs32_v2i16
 - BB0[entry]: float = 1.0, int = 18014398509481984

		Looking for trivial roots
Found a new trivial root: %bb.0
Last visited node: %bb.0
		Looking for non-trivial roots
Total: 1, Num: 2
Discovered CFG nodes:
0: nullptr
1: nullptr
2: %bb.0
Found roots: %bb.0 
# *** IR Dump Before Shrink Wrapping analysis (shrink-wrap) ***:
# Machine code for function test_macs32_v2i16: NoPHIs, TracksLiveness, NoVRegs, Legalized, RegBankSelected, Selected, TiedOpsRewritten, TracksDebugUserValues
Function Live Ins: $x10, $x11, $x12

bb.0.entry:
  liveins: $x10, $x11, $x12
  renamable $x10 = cv_machhNs_ killed renamable $x10(tied-def 0), renamable $x11, renamable $x12, 0
  renamable $x10 = cv_macs_i16_ killed renamable $x10(tied-def 0), killed renamable $x11, killed renamable $x12
  PseudoRET implicit $x10

# End machine code for function test_macs32_v2i16.

**** Analysing test_macs32_v2i16
Look into: %bb.0
Nothing to shrink-wrap
# *** IR Dump After Shrink Wrapping analysis (shrink-wrap) ***:
# Machine code for function test_macs32_v2i16: NoPHIs, TracksLiveness, NoVRegs, Legalized, RegBankSelected, Selected, TiedOpsRewritten, TracksDebugUserValues
Function Live Ins: $x10, $x11, $x12

bb.0.entry:
  liveins: $x10, $x11, $x12
  renamable $x10 = cv_machhNs_ killed renamable $x10(tied-def 0), renamable $x11, renamable $x12, 0
  renamable $x10 = cv_macs_i16_ killed renamable $x10(tied-def 0), killed renamable $x11, killed renamable $x12
  PseudoRET implicit $x10

# End machine code for function test_macs32_v2i16.

# *** IR Dump Before Prologue/Epilogue Insertion & Frame Finalization (prologepilog) ***:
# Machine code for function test_macs32_v2i16: NoPHIs, TracksLiveness, NoVRegs, Legalized, RegBankSelected, Selected, TiedOpsRewritten, TracksDebugUserValues
Function Live Ins: $x10, $x11, $x12

bb.0.entry:
  liveins: $x10, $x11, $x12
  renamable $x10 = cv_machhNs_ killed renamable $x10(tied-def 0), renamable $x11, renamable $x12, 0
  renamable $x10 = cv_macs_i16_ killed renamable $x10(tied-def 0), killed renamable $x11, killed renamable $x12
  PseudoRET implicit $x10

# End machine code for function test_macs32_v2i16.

# *** IR Dump After Prologue/Epilogue Insertion & Frame Finalization (prologepilog) ***:
# Machine code for function test_macs32_v2i16: NoPHIs, TracksLiveness, NoVRegs, Legalized, RegBankSelected, Selected, TiedOpsRewritten, TracksDebugUserValues
Function Live Ins: $x10, $x11, $x12

bb.0.entry:
  liveins: $x10, $x11, $x12
  renamable $x10 = cv_machhNs_ killed renamable $x10(tied-def 0), renamable $x11, renamable $x12, 0
  renamable $x10 = cv_macs_i16_ killed renamable $x10(tied-def 0), killed renamable $x11, killed renamable $x12
  PseudoRET implicit $x10

# End machine code for function test_macs32_v2i16.

# *** IR Dump Before Machine Late Instructions Cleanup Pass (machine-latecleanup) ***:
# Machine code for function test_macs32_v2i16: NoPHIs, TracksLiveness, NoVRegs, Legalized, RegBankSelected, Selected, TiedOpsRewritten, TracksDebugUserValues
Function Live Ins: $x10, $x11, $x12

bb.0.entry:
  liveins: $x10, $x11, $x12
  renamable $x10 = cv_machhNs_ killed renamable $x10(tied-def 0), renamable $x11, renamable $x12, 0
  renamable $x10 = cv_macs_i16_ killed renamable $x10(tied-def 0), killed renamable $x11, killed renamable $x12
  PseudoRET implicit $x10

# End machine code for function test_macs32_v2i16.

# *** IR Dump After Machine Late Instructions Cleanup Pass (machine-latecleanup) ***:
# Machine code for function test_macs32_v2i16: NoPHIs, TracksLiveness, NoVRegs, Legalized, RegBankSelected, Selected, TiedOpsRewritten, TracksDebugUserValues
Function Live Ins: $x10, $x11, $x12

bb.0.entry:
  liveins: $x10, $x11, $x12
  renamable $x10 = cv_machhNs_ killed renamable $x10(tied-def 0), renamable $x11, renamable $x12, 0
  renamable $x10 = cv_macs_i16_ killed renamable $x10(tied-def 0), killed renamable $x11, killed renamable $x12
  PseudoRET implicit $x10

# End machine code for function test_macs32_v2i16.

# *** IR Dump Before Control Flow Optimizer (branch-folder) ***:
# Machine code for function test_macs32_v2i16: NoPHIs, TracksLiveness, NoVRegs, Legalized, RegBankSelected, Selected, TiedOpsRewritten, TracksDebugUserValues
Function Live Ins: $x10, $x11, $x12

bb.0.entry:
  liveins: $x10, $x11, $x12
  renamable $x10 = cv_machhNs_ killed renamable $x10(tied-def 0), renamable $x11, renamable $x12, 0
  renamable $x10 = cv_macs_i16_ killed renamable $x10(tied-def 0), killed renamable $x11, killed renamable $x12
  PseudoRET implicit $x10

# End machine code for function test_macs32_v2i16.

# *** IR Dump After Control Flow Optimizer (branch-folder) ***:
# Machine code for function test_macs32_v2i16: NoPHIs, TracksLiveness, NoVRegs, Legalized, RegBankSelected, Selected, TiedOpsRewritten, TracksDebugUserValues
Function Live Ins: $x10, $x11, $x12

bb.0.entry:
  liveins: $x10, $x11, $x12
  renamable $x10 = cv_machhNs_ killed renamable $x10(tied-def 0), renamable $x11, renamable $x12, 0
  renamable $x10 = cv_macs_i16_ killed renamable $x10(tied-def 0), killed renamable $x11, killed renamable $x12
  PseudoRET implicit $x10

# End machine code for function test_macs32_v2i16.

# *** IR Dump Before Tail Duplication (tailduplication) ***:
# Machine code for function test_macs32_v2i16: NoPHIs, TracksLiveness, NoVRegs, Legalized, RegBankSelected, Selected, TiedOpsRewritten, TracksDebugUserValues
Function Live Ins: $x10, $x11, $x12

bb.0.entry:
  liveins: $x10, $x11, $x12
  renamable $x10 = cv_machhNs_ killed renamable $x10(tied-def 0), renamable $x11, renamable $x12, 0
  renamable $x10 = cv_macs_i16_ killed renamable $x10(tied-def 0), killed renamable $x11, killed renamable $x12
  PseudoRET implicit $x10

# End machine code for function test_macs32_v2i16.

# *** IR Dump After Tail Duplication (tailduplication) ***:
# Machine code for function test_macs32_v2i16: NoPHIs, TracksLiveness, NoVRegs, Legalized, RegBankSelected, Selected, TiedOpsRewritten, TracksDebugUserValues
Function Live Ins: $x10, $x11, $x12

bb.0.entry:
  liveins: $x10, $x11, $x12
  renamable $x10 = cv_machhNs_ killed renamable $x10(tied-def 0), renamable $x11, renamable $x12, 0
  renamable $x10 = cv_macs_i16_ killed renamable $x10(tied-def 0), killed renamable $x11, killed renamable $x12
  PseudoRET implicit $x10

# End machine code for function test_macs32_v2i16.

# *** IR Dump Before Machine Copy Propagation Pass (machine-cp) ***:
# Machine code for function test_macs32_v2i16: NoPHIs, TracksLiveness, NoVRegs, Legalized, RegBankSelected, Selected, TiedOpsRewritten, TracksDebugUserValues
Function Live Ins: $x10, $x11, $x12

bb.0.entry:
  liveins: $x10, $x11, $x12
  renamable $x10 = cv_machhNs_ killed renamable $x10(tied-def 0), renamable $x11, renamable $x12, 0
  renamable $x10 = cv_macs_i16_ killed renamable $x10(tied-def 0), killed renamable $x11, killed renamable $x12
  PseudoRET implicit $x10

# End machine code for function test_macs32_v2i16.

MCP: BackwardCopyPropagateBlock entry
MCP: ForwardCopyPropagateBlock entry
# *** IR Dump After Machine Copy Propagation Pass (machine-cp) ***:
# Machine code for function test_macs32_v2i16: NoPHIs, TracksLiveness, NoVRegs, Legalized, RegBankSelected, Selected, TiedOpsRewritten, TracksDebugUserValues
Function Live Ins: $x10, $x11, $x12

bb.0.entry:
  liveins: $x10, $x11, $x12
  renamable $x10 = cv_machhNs_ killed renamable $x10(tied-def 0), renamable $x11, renamable $x12, 0
  renamable $x10 = cv_macs_i16_ killed renamable $x10(tied-def 0), killed renamable $x11, killed renamable $x12
  PseudoRET implicit $x10

# End machine code for function test_macs32_v2i16.

# *** IR Dump Before Post-RA pseudo instruction expansion pass (postrapseudos) ***:
# Machine code for function test_macs32_v2i16: NoPHIs, TracksLiveness, NoVRegs, Legalized, RegBankSelected, Selected, TiedOpsRewritten, TracksDebugUserValues
Function Live Ins: $x10, $x11, $x12

bb.0.entry:
  liveins: $x10, $x11, $x12
  renamable $x10 = cv_machhNs_ killed renamable $x10(tied-def 0), renamable $x11, renamable $x12, 0
  renamable $x10 = cv_macs_i16_ killed renamable $x10(tied-def 0), killed renamable $x11, killed renamable $x12
  PseudoRET implicit $x10

# End machine code for function test_macs32_v2i16.

Machine Function
********** EXPANDING POST-RA PSEUDO INSTRS **********
********** Function: test_macs32_v2i16
# *** IR Dump After Post-RA pseudo instruction expansion pass (postrapseudos) ***:
# Machine code for function test_macs32_v2i16: NoPHIs, TracksLiveness, NoVRegs, Legalized, RegBankSelected, Selected, TiedOpsRewritten, TracksDebugUserValues
Function Live Ins: $x10, $x11, $x12

bb.0.entry:
  liveins: $x10, $x11, $x12
  renamable $x10 = cv_machhNs_ killed renamable $x10(tied-def 0), renamable $x11, renamable $x12, 0
  renamable $x10 = cv_macs_i16_ killed renamable $x10(tied-def 0), killed renamable $x11, killed renamable $x12
  PseudoRET implicit $x10

# End machine code for function test_macs32_v2i16.

# *** IR Dump Before RISC-V post-regalloc pseudo instruction expansion pass (riscv-expand-pseudolisimm32) ***:
# Machine code for function test_macs32_v2i16: NoPHIs, TracksLiveness, NoVRegs, Legalized, RegBankSelected, Selected, TiedOpsRewritten, TracksDebugUserValues
Function Live Ins: $x10, $x11, $x12

bb.0.entry:
  liveins: $x10, $x11, $x12
  renamable $x10 = cv_machhNs_ killed renamable $x10(tied-def 0), renamable $x11, renamable $x12, 0
  renamable $x10 = cv_macs_i16_ killed renamable $x10(tied-def 0), killed renamable $x11, killed renamable $x12
  PseudoRET implicit $x10

# End machine code for function test_macs32_v2i16.

# *** IR Dump After RISC-V post-regalloc pseudo instruction expansion pass (riscv-expand-pseudolisimm32) ***:
# Machine code for function test_macs32_v2i16: NoPHIs, TracksLiveness, NoVRegs, Legalized, RegBankSelected, Selected, TiedOpsRewritten, TracksDebugUserValues
Function Live Ins: $x10, $x11, $x12

bb.0.entry:
  liveins: $x10, $x11, $x12
  renamable $x10 = cv_machhNs_ killed renamable $x10(tied-def 0), renamable $x11, renamable $x12, 0
  renamable $x10 = cv_macs_i16_ killed renamable $x10(tied-def 0), killed renamable $x11, killed renamable $x12
  PseudoRET implicit $x10

# End machine code for function test_macs32_v2i16.

# *** IR Dump Before Insert KCFI indirect call checks (kcfi) ***:
# Machine code for function test_macs32_v2i16: NoPHIs, TracksLiveness, NoVRegs, Legalized, RegBankSelected, Selected, TiedOpsRewritten, TracksDebugUserValues
Function Live Ins: $x10, $x11, $x12

bb.0.entry:
  liveins: $x10, $x11, $x12
  renamable $x10 = cv_machhNs_ killed renamable $x10(tied-def 0), renamable $x11, renamable $x12, 0
  renamable $x10 = cv_macs_i16_ killed renamable $x10(tied-def 0), killed renamable $x11, killed renamable $x12
  PseudoRET implicit $x10

# End machine code for function test_macs32_v2i16.

# *** IR Dump After Insert KCFI indirect call checks (kcfi) ***:
# Machine code for function test_macs32_v2i16: NoPHIs, TracksLiveness, NoVRegs, Legalized, RegBankSelected, Selected, TiedOpsRewritten, TracksDebugUserValues
Function Live Ins: $x10, $x11, $x12

bb.0.entry:
  liveins: $x10, $x11, $x12
  renamable $x10 = cv_machhNs_ killed renamable $x10(tied-def 0), renamable $x11, renamable $x12, 0
  renamable $x10 = cv_macs_i16_ killed renamable $x10(tied-def 0), killed renamable $x11, killed renamable $x12
  PseudoRET implicit $x10

# End machine code for function test_macs32_v2i16.

# *** IR Dump Before PostRA Machine Instruction Scheduler (postmisched) ***:
# Machine code for function test_macs32_v2i16: NoPHIs, TracksLiveness, NoVRegs, Legalized, RegBankSelected, Selected, TiedOpsRewritten, TracksDebugUserValues
Function Live Ins: $x10, $x11, $x12

bb.0.entry:
  liveins: $x10, $x11, $x12
  renamable $x10 = cv_machhNs_ killed renamable $x10(tied-def 0), renamable $x11, renamable $x12, 0
  renamable $x10 = cv_macs_i16_ killed renamable $x10(tied-def 0), killed renamable $x11, killed renamable $x12
  PseudoRET implicit $x10

# End machine code for function test_macs32_v2i16.

Subtarget disables post-MI-sched.
# *** IR Dump After PostRA Machine Instruction Scheduler (postmisched) ***:
# Machine code for function test_macs32_v2i16: NoPHIs, TracksLiveness, NoVRegs, Legalized, RegBankSelected, Selected, TiedOpsRewritten, TracksDebugUserValues
Function Live Ins: $x10, $x11, $x12

bb.0.entry:
  liveins: $x10, $x11, $x12
  renamable $x10 = cv_machhNs_ killed renamable $x10(tied-def 0), renamable $x11, renamable $x12, 0
  renamable $x10 = cv_macs_i16_ killed renamable $x10(tied-def 0), killed renamable $x11, killed renamable $x12
  PseudoRET implicit $x10

# End machine code for function test_macs32_v2i16.

# *** IR Dump Before Analyze Machine Code For Garbage Collection (gc-analysis) ***:
# Machine code for function test_macs32_v2i16: NoPHIs, TracksLiveness, NoVRegs, Legalized, RegBankSelected, Selected, TiedOpsRewritten, TracksDebugUserValues
Function Live Ins: $x10, $x11, $x12

bb.0.entry:
  liveins: $x10, $x11, $x12
  renamable $x10 = cv_machhNs_ killed renamable $x10(tied-def 0), renamable $x11, renamable $x12, 0
  renamable $x10 = cv_macs_i16_ killed renamable $x10(tied-def 0), killed renamable $x11, killed renamable $x12
  PseudoRET implicit $x10

# End machine code for function test_macs32_v2i16.

# *** IR Dump After Analyze Machine Code For Garbage Collection (gc-analysis) ***:
# Machine code for function test_macs32_v2i16: NoPHIs, TracksLiveness, NoVRegs, Legalized, RegBankSelected, Selected, TiedOpsRewritten, TracksDebugUserValues
Function Live Ins: $x10, $x11, $x12

bb.0.entry:
  liveins: $x10, $x11, $x12
  renamable $x10 = cv_machhNs_ killed renamable $x10(tied-def 0), renamable $x11, renamable $x12, 0
  renamable $x10 = cv_macs_i16_ killed renamable $x10(tied-def 0), killed renamable $x11, killed renamable $x12
  PseudoRET implicit $x10

# End machine code for function test_macs32_v2i16.


block-frequency: test_macs32_v2i16
==================================
reverse-post-order-traversal
 - 0: BB0[entry]
loop-detection
compute-mass-in-function
 - node: BB0[entry]
  => mass:  ffffffffffffffff
float-to-int: min = 1.0, max = 1.0, factor = 18014398509481984.0
 - BB0[entry]: float = 1.0, scaled = 18014398509481984.0, int = 18014398509481984
block-frequency-info: test_macs32_v2i16
 - BB0[entry]: float = 1.0, int = 18014398509481984

		Looking for trivial roots
Found a new trivial root: %bb.0
Last visited node: %bb.0
		Looking for non-trivial roots
Total: 1, Num: 2
Discovered CFG nodes:
0: nullptr
1: nullptr
2: %bb.0
Found roots: %bb.0 
# *** IR Dump Before Branch Probability Basic Block Placement (block-placement) ***:
# Machine code for function test_macs32_v2i16: NoPHIs, TracksLiveness, NoVRegs, Legalized, RegBankSelected, Selected, TiedOpsRewritten, TracksDebugUserValues
Function Live Ins: $x10, $x11, $x12

bb.0.entry:
  liveins: $x10, $x11, $x12
  renamable $x10 = cv_machhNs_ killed renamable $x10(tied-def 0), renamable $x11, renamable $x12, 0
  renamable $x10 = cv_macs_i16_ killed renamable $x10(tied-def 0), killed renamable $x11, killed renamable $x12
  PseudoRET implicit $x10

# End machine code for function test_macs32_v2i16.

# *** IR Dump After Branch Probability Basic Block Placement (block-placement) ***:
# Machine code for function test_macs32_v2i16: NoPHIs, TracksLiveness, NoVRegs, Legalized, RegBankSelected, Selected, TiedOpsRewritten, TracksDebugUserValues
Function Live Ins: $x10, $x11, $x12

bb.0.entry:
  liveins: $x10, $x11, $x12
  renamable $x10 = cv_machhNs_ killed renamable $x10(tied-def 0), renamable $x11, renamable $x12, 0
  renamable $x10 = cv_macs_i16_ killed renamable $x10(tied-def 0), killed renamable $x11, killed renamable $x12
  PseudoRET implicit $x10

# End machine code for function test_macs32_v2i16.

# *** IR Dump Before Insert fentry calls (fentry-insert) ***:
# Machine code for function test_macs32_v2i16: NoPHIs, TracksLiveness, NoVRegs, Legalized, RegBankSelected, Selected, TiedOpsRewritten, TracksDebugUserValues
Function Live Ins: $x10, $x11, $x12

bb.0.entry:
  liveins: $x10, $x11, $x12
  renamable $x10 = cv_machhNs_ killed renamable $x10(tied-def 0), renamable $x11, renamable $x12, 0
  renamable $x10 = cv_macs_i16_ killed renamable $x10(tied-def 0), killed renamable $x11, killed renamable $x12
  PseudoRET implicit $x10

# End machine code for function test_macs32_v2i16.

# *** IR Dump After Insert fentry calls (fentry-insert) ***:
# Machine code for function test_macs32_v2i16: NoPHIs, TracksLiveness, NoVRegs, Legalized, RegBankSelected, Selected, TiedOpsRewritten, TracksDebugUserValues
Function Live Ins: $x10, $x11, $x12

bb.0.entry:
  liveins: $x10, $x11, $x12
  renamable $x10 = cv_machhNs_ killed renamable $x10(tied-def 0), renamable $x11, renamable $x12, 0
  renamable $x10 = cv_macs_i16_ killed renamable $x10(tied-def 0), killed renamable $x11, killed renamable $x12
  PseudoRET implicit $x10

# End machine code for function test_macs32_v2i16.

# *** IR Dump Before Insert XRay ops (xray-instrumentation) ***:
# Machine code for function test_macs32_v2i16: NoPHIs, TracksLiveness, NoVRegs, Legalized, RegBankSelected, Selected, TiedOpsRewritten, TracksDebugUserValues
Function Live Ins: $x10, $x11, $x12

bb.0.entry:
  liveins: $x10, $x11, $x12
  renamable $x10 = cv_machhNs_ killed renamable $x10(tied-def 0), renamable $x11, renamable $x12, 0
  renamable $x10 = cv_macs_i16_ killed renamable $x10(tied-def 0), killed renamable $x11, killed renamable $x12
  PseudoRET implicit $x10

# End machine code for function test_macs32_v2i16.

# *** IR Dump After Insert XRay ops (xray-instrumentation) ***:
# Machine code for function test_macs32_v2i16: NoPHIs, TracksLiveness, NoVRegs, Legalized, RegBankSelected, Selected, TiedOpsRewritten, TracksDebugUserValues
Function Live Ins: $x10, $x11, $x12

bb.0.entry:
  liveins: $x10, $x11, $x12
  renamable $x10 = cv_machhNs_ killed renamable $x10(tied-def 0), renamable $x11, renamable $x12, 0
  renamable $x10 = cv_macs_i16_ killed renamable $x10(tied-def 0), killed renamable $x11, killed renamable $x12
  PseudoRET implicit $x10

# End machine code for function test_macs32_v2i16.

# *** IR Dump Before Implement the 'patchable-function' attribute (patchable-function) ***:
# Machine code for function test_macs32_v2i16: NoPHIs, TracksLiveness, NoVRegs, Legalized, RegBankSelected, Selected, TiedOpsRewritten, TracksDebugUserValues
Function Live Ins: $x10, $x11, $x12

bb.0.entry:
  liveins: $x10, $x11, $x12
  renamable $x10 = cv_machhNs_ killed renamable $x10(tied-def 0), renamable $x11, renamable $x12, 0
  renamable $x10 = cv_macs_i16_ killed renamable $x10(tied-def 0), killed renamable $x11, killed renamable $x12
  PseudoRET implicit $x10

# End machine code for function test_macs32_v2i16.

# *** IR Dump After Implement the 'patchable-function' attribute (patchable-function) ***:
# Machine code for function test_macs32_v2i16: NoPHIs, TracksLiveness, NoVRegs, Legalized, RegBankSelected, Selected, TiedOpsRewritten, TracksDebugUserValues
Function Live Ins: $x10, $x11, $x12

bb.0.entry:
  liveins: $x10, $x11, $x12
  renamable $x10 = cv_machhNs_ killed renamable $x10(tied-def 0), renamable $x11, renamable $x12, 0
  renamable $x10 = cv_macs_i16_ killed renamable $x10(tied-def 0), killed renamable $x11, killed renamable $x12
  PseudoRET implicit $x10

# End machine code for function test_macs32_v2i16.

# *** IR Dump Before Branch relaxation pass (branch-relaxation) ***:
# Machine code for function test_macs32_v2i16: NoPHIs, TracksLiveness, NoVRegs, Legalized, RegBankSelected, Selected, TiedOpsRewritten, TracksDebugUserValues
Function Live Ins: $x10, $x11, $x12

bb.0.entry:
  liveins: $x10, $x11, $x12
  renamable $x10 = cv_machhNs_ killed renamable $x10(tied-def 0), renamable $x11, renamable $x12, 0
  renamable $x10 = cv_macs_i16_ killed renamable $x10(tied-def 0), killed renamable $x11, killed renamable $x12
  PseudoRET implicit $x10

# End machine code for function test_macs32_v2i16.

***** BranchRelaxation *****
  Basic blocks before relaxation
%bb.0	offset=00000000	size=0xc
  Basic blocks after relaxation

%bb.0	offset=00000000	size=0xc
# *** IR Dump After Branch relaxation pass (branch-relaxation) ***:
# Machine code for function test_macs32_v2i16: NoPHIs, TracksLiveness, NoVRegs, Legalized, RegBankSelected, Selected, TiedOpsRewritten, TracksDebugUserValues
Function Live Ins: $x10, $x11, $x12

bb.0.entry:
  liveins: $x10, $x11, $x12
  renamable $x10 = cv_machhNs_ killed renamable $x10(tied-def 0), renamable $x11, renamable $x12, 0
  renamable $x10 = cv_macs_i16_ killed renamable $x10(tied-def 0), killed renamable $x11, killed renamable $x12
  PseudoRET implicit $x10

# End machine code for function test_macs32_v2i16.

# *** IR Dump Before RISC-V Make Compressible (riscv-make-compressible) ***:
# Machine code for function test_macs32_v2i16: NoPHIs, TracksLiveness, NoVRegs, Legalized, RegBankSelected, Selected, TiedOpsRewritten, TracksDebugUserValues
Function Live Ins: $x10, $x11, $x12

bb.0.entry:
  liveins: $x10, $x11, $x12
  renamable $x10 = cv_machhNs_ killed renamable $x10(tied-def 0), renamable $x11, renamable $x12, 0
  renamable $x10 = cv_macs_i16_ killed renamable $x10(tied-def 0), killed renamable $x11, killed renamable $x12
  PseudoRET implicit $x10

# End machine code for function test_macs32_v2i16.

# *** IR Dump After RISC-V Make Compressible (riscv-make-compressible) ***:
# Machine code for function test_macs32_v2i16: NoPHIs, TracksLiveness, NoVRegs, Legalized, RegBankSelected, Selected, TiedOpsRewritten, TracksDebugUserValues
Function Live Ins: $x10, $x11, $x12

bb.0.entry:
  liveins: $x10, $x11, $x12
  renamable $x10 = cv_machhNs_ killed renamable $x10(tied-def 0), renamable $x11, renamable $x12, 0
  renamable $x10 = cv_macs_i16_ killed renamable $x10(tied-def 0), killed renamable $x11, killed renamable $x12
  PseudoRET implicit $x10

# End machine code for function test_macs32_v2i16.

# *** IR Dump Before Machine Copy Propagation Pass (machine-cp) ***:
# Machine code for function test_macs32_v2i16: NoPHIs, TracksLiveness, NoVRegs, Legalized, RegBankSelected, Selected, TiedOpsRewritten, TracksDebugUserValues
Function Live Ins: $x10, $x11, $x12

bb.0.entry:
  liveins: $x10, $x11, $x12
  renamable $x10 = cv_machhNs_ killed renamable $x10(tied-def 0), renamable $x11, renamable $x12, 0
  renamable $x10 = cv_macs_i16_ killed renamable $x10(tied-def 0), killed renamable $x11, killed renamable $x12
  PseudoRET implicit $x10

# End machine code for function test_macs32_v2i16.

MCP: BackwardCopyPropagateBlock entry
MCP: ForwardCopyPropagateBlock entry
# *** IR Dump After Machine Copy Propagation Pass (machine-cp) ***:
# Machine code for function test_macs32_v2i16: NoPHIs, TracksLiveness, NoVRegs, Legalized, RegBankSelected, Selected, TiedOpsRewritten, TracksDebugUserValues
Function Live Ins: $x10, $x11, $x12

bb.0.entry:
  liveins: $x10, $x11, $x12
  renamable $x10 = cv_machhNs_ killed renamable $x10(tied-def 0), renamable $x11, renamable $x12, 0
  renamable $x10 = cv_macs_i16_ killed renamable $x10(tied-def 0), killed renamable $x11, killed renamable $x12
  PseudoRET implicit $x10

# End machine code for function test_macs32_v2i16.

# *** IR Dump Before Contiguously Lay Out Funclets (funclet-layout) ***:
# Machine code for function test_macs32_v2i16: NoPHIs, TracksLiveness, NoVRegs, Legalized, RegBankSelected, Selected, TiedOpsRewritten, TracksDebugUserValues
Function Live Ins: $x10, $x11, $x12

bb.0.entry:
  liveins: $x10, $x11, $x12
  renamable $x10 = cv_machhNs_ killed renamable $x10(tied-def 0), renamable $x11, renamable $x12, 0
  renamable $x10 = cv_macs_i16_ killed renamable $x10(tied-def 0), killed renamable $x11, killed renamable $x12
  PseudoRET implicit $x10

# End machine code for function test_macs32_v2i16.

# *** IR Dump After Contiguously Lay Out Funclets (funclet-layout) ***:
# Machine code for function test_macs32_v2i16: NoPHIs, TracksLiveness, NoVRegs, Legalized, RegBankSelected, Selected, TiedOpsRewritten, TracksDebugUserValues
Function Live Ins: $x10, $x11, $x12

bb.0.entry:
  liveins: $x10, $x11, $x12
  renamable $x10 = cv_machhNs_ killed renamable $x10(tied-def 0), renamable $x11, renamable $x12, 0
  renamable $x10 = cv_macs_i16_ killed renamable $x10(tied-def 0), killed renamable $x11, killed renamable $x12
  PseudoRET implicit $x10

# End machine code for function test_macs32_v2i16.

# *** IR Dump Before StackMap Liveness Analysis (stackmap-liveness) ***:
# Machine code for function test_macs32_v2i16: NoPHIs, TracksLiveness, NoVRegs, Legalized, RegBankSelected, Selected, TiedOpsRewritten, TracksDebugUserValues
Function Live Ins: $x10, $x11, $x12

bb.0.entry:
  liveins: $x10, $x11, $x12
  renamable $x10 = cv_machhNs_ killed renamable $x10(tied-def 0), renamable $x11, renamable $x12, 0
  renamable $x10 = cv_macs_i16_ killed renamable $x10(tied-def 0), killed renamable $x11, killed renamable $x12
  PseudoRET implicit $x10

# End machine code for function test_macs32_v2i16.

********** COMPUTING STACKMAP LIVENESS: test_macs32_v2i16 **********
# *** IR Dump After StackMap Liveness Analysis (stackmap-liveness) ***:
# Machine code for function test_macs32_v2i16: NoPHIs, TracksLiveness, NoVRegs, Legalized, RegBankSelected, Selected, TiedOpsRewritten, TracksDebugUserValues
Function Live Ins: $x10, $x11, $x12

bb.0.entry:
  liveins: $x10, $x11, $x12
  renamable $x10 = cv_machhNs_ killed renamable $x10(tied-def 0), renamable $x11, renamable $x12, 0
  renamable $x10 = cv_macs_i16_ killed renamable $x10(tied-def 0), killed renamable $x11, killed renamable $x12
  PseudoRET implicit $x10

# End machine code for function test_macs32_v2i16.

# *** IR Dump Before Live DEBUG_VALUE analysis (livedebugvalues) ***:
# Machine code for function test_macs32_v2i16: NoPHIs, TracksLiveness, NoVRegs, Legalized, RegBankSelected, Selected, TiedOpsRewritten, TracksDebugUserValues
Function Live Ins: $x10, $x11, $x12

bb.0.entry:
  liveins: $x10, $x11, $x12
  renamable $x10 = cv_machhNs_ killed renamable $x10(tied-def 0), renamable $x11, renamable $x12, 0
  renamable $x10 = cv_macs_i16_ killed renamable $x10(tied-def 0), killed renamable $x11, killed renamable $x12
  PseudoRET implicit $x10

# End machine code for function test_macs32_v2i16.


Debug Range Extension: test_macs32_v2i16
# *** IR Dump After Live DEBUG_VALUE analysis (livedebugvalues) ***:
# Machine code for function test_macs32_v2i16: NoPHIs, TracksLiveness, NoVRegs, Legalized, RegBankSelected, Selected, TiedOpsRewritten, TracksDebugUserValues
Function Live Ins: $x10, $x11, $x12

bb.0.entry:
  liveins: $x10, $x11, $x12
  renamable $x10 = cv_machhNs_ killed renamable $x10(tied-def 0), renamable $x11, renamable $x12, 0
  renamable $x10 = cv_macs_i16_ killed renamable $x10(tied-def 0), killed renamable $x11, killed renamable $x12
  PseudoRET implicit $x10

# End machine code for function test_macs32_v2i16.

# *** IR Dump Before Machine Sanitizer Binary Metadata (machine-sanmd) ***:
# Machine code for function test_macs32_v2i16: NoPHIs, TracksLiveness, NoVRegs, Legalized, RegBankSelected, Selected, TiedOpsRewritten, TracksDebugUserValues
Function Live Ins: $x10, $x11, $x12

bb.0.entry:
  liveins: $x10, $x11, $x12
  renamable $x10 = cv_machhNs_ killed renamable $x10(tied-def 0), renamable $x11, renamable $x12, 0
  renamable $x10 = cv_macs_i16_ killed renamable $x10(tied-def 0), killed renamable $x11, killed renamable $x12
  PseudoRET implicit $x10

# End machine code for function test_macs32_v2i16.

# *** IR Dump After Machine Sanitizer Binary Metadata (machine-sanmd) ***:
# Machine code for function test_macs32_v2i16: NoPHIs, TracksLiveness, NoVRegs, Legalized, RegBankSelected, Selected, TiedOpsRewritten, TracksDebugUserValues
Function Live Ins: $x10, $x11, $x12

bb.0.entry:
  liveins: $x10, $x11, $x12
  renamable $x10 = cv_machhNs_ killed renamable $x10(tied-def 0), renamable $x11, renamable $x12, 0
  renamable $x10 = cv_macs_i16_ killed renamable $x10(tied-def 0), killed renamable $x11, killed renamable $x12
  PseudoRET implicit $x10

# End machine code for function test_macs32_v2i16.

*** IR Dump Before Machine Outliner (machine-outliner) ***
; ModuleID = 'cecil_test.c'
source_filename = "cecil_test.c"
target datalayout = "e-m:e-p:32:32-i64:64-n32-S128"
target triple = "riscv32-unknown-unknown"

; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none)
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv4, %conv1
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv11, %conv7
  %add = add i32 %mul12, %acc
  %add13 = add i32 %add, %mul
  ret i32 %add13
}

attributes #0 = { mustprogress nofree norecurse nosync nounwind willreturn memory(none) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="generic-rv32" "target-features"="+32bit,+m,+relax,+xseal5testalucvabs16,+xseal5testalucvabs32,+xseal5testalucvabs8,+xseal5testalucvaddnrsi16,+xseal5testalucvaddnrsi32,+xseal5testalucvaddnrui16,+xseal5testalucvaddnrui32,+xseal5testalucvaddns,+xseal5testalucvaddnu,+xseal5testalucvaddrnrsi16,+xseal5testalucvaddrnrsi32,+xseal5testalucvaddrnrui16,+xseal5testalucvaddrnrui32,+xseal5testalucvaddrns,+xseal5testalucvaddrnu,+xseal5testalucvextbs,+xseal5testalucvextbz,+xseal5testalucvexths,+xseal5testalucvexthz,+xseal5testalucvmaxi1216,+xseal5testalucvmaxi1232,+xseal5testalucvmaxi516,+xseal5testalucvmaxi532,+xseal5testalucvmaxs16,+xseal5testalucvmaxs32,+xseal5testalucvmaxs8,+xseal5testalucvmaxu16,+xseal5testalucvmaxu32,+xseal5testalucvmaxu8,+xseal5testalucvmini1216,+xseal5testalucvmini1232,+xseal5testalucvmini516,+xseal5testalucvmini532,+xseal5testalucvmins16,+xseal5testalucvmins32,+xseal5testalucvmins8,+xseal5testalucvminu16,+xseal5testalucvminu32,+xseal5testalucvminu8,+xseal5testalucvsletsi16,+xseal5testalucvsletsi32,+xseal5testalucvsletui16,+xseal5testalucvsletui32,+xseal5testalucvsubnrsi16,+xseal5testalucvsubnrsi32,+xseal5testalucvsubnrui16,+xseal5testalucvsubnrui32,+xseal5testalucvsubns,+xseal5testalucvsubnu,+xseal5testalucvsubrnrsi16,+xseal5testalucvsubrnrsi32,+xseal5testalucvsubrnrui16,+xseal5testalucvsubrnrui32,+xseal5testalucvsubrns,+xseal5testalucvsubrnu,+xseal5testmaccvmachhns,+xseal5testmaccvmachhnu,+xseal5testmaccvmachhrns,+xseal5testmaccvmachhrnu,+xseal5testmaccvmacns,+xseal5testmaccvmacnu,+xseal5testmaccvmacrns,+xseal5testmaccvmacrnu,+xseal5testmaccvmacsi16,+xseal5testmaccvmacsi32,+xseal5testmaccvmacui16,+xseal5testmaccvmacui32,+xseal5testmaccvmsusi16,+xseal5testmaccvmsusi32,+xseal5testmaccvmsuui16,+xseal5testmaccvmsuui32,+xseal5testmaccvmulhhns,+xseal5testmaccvmulhhnu,+xseal5testmaccvmulhhrns,+xseal5testmaccvmulhhrnu,+xseal5testmaccvmulns,+xseal5testmaccvmulnu,+xseal5testmaccvmulrns,+xseal5testmaccvmulrnu,-a,-c,-d,-e,-experimental-zacas,-experimental-zcmop,-experimental-zfbfmin,-experimental-zicfilp,-experimental-zicfiss,-experimental-zimop,-experimental-ztso,-experimental-zvfbfmin,-experimental-zvfbfwma,-f,-h,-smaia,-smepmp,-ssaia,-svinval,-svnapot,-svpbmt,-v,-xcvalu,-xcvbi,-xcvbitmanip,-xcvelw,-xcvmac,-xcvmem,-xcvsimd,-xsfvcp,-xsfvfnrclipxfqf,-xsfvfwmaccqqq,-xsfvqmaccdod,-xsfvqmaccqoq,-xtheadba,-xtheadbb,-xtheadbs,-xtheadcmo,-xtheadcondmov,-xtheadfmemidx,-xtheadmac,-xtheadmemidx,-xtheadmempair,-xtheadsync,-xtheadvdot,-xventanacondops,-za128rs,-za64rs,-zawrs,-zba,-zbb,-zbc,-zbkb,-zbkc,-zbkx,-zbs,-zca,-zcb,-zcd,-zce,-zcf,-zcmp,-zcmt,-zdinx,-zfa,-zfh,-zfhmin,-zfinx,-zhinx,-zhinxmin,-zic64b,-zicbom,-zicbop,-zicboz,-ziccamoa,-ziccif,-zicclsm,-ziccrse,-zicntr,-zicond,-zicsr,-zifencei,-zihintntl,-zihintpause,-zihpm,-zk,-zkn,-zknd,-zkne,-zknh,-zkr,-zks,-zksed,-zksh,-zkt,-zmmul,-zvbb,-zvbc,-zve32f,-zve32x,-zve64d,-zve64f,-zve64x,-zvfh,-zvfhmin,-zvkb,-zvkg,-zvkn,-zvknc,-zvkned,-zvkng,-zvknha,-zvknhb,-zvks,-zvksc,-zvksed,-zvksg,-zvksh,-zvkt,-zvl1024b,-zvl128b,-zvl16384b,-zvl2048b,-zvl256b,-zvl32768b,-zvl32b,-zvl4096b,-zvl512b,-zvl64b,-zvl65536b,-zvl8192b" }

!llvm.module.flags = !{!0, !1, !2}
!llvm.ident = !{!3}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 1, !"target-abi", !"ilp32"}
!2 = !{i32 8, !"SmallDataLimit", i32 8}
!3 = !{!"clang version 18.1.0rc (https://github.com/llvm/llvm-project.git 1acc4e456481e76822c76c850bad3994d4e04b59)"}
Machine Outliner: Running on target-default functions
*** Populating mapper ***
MAPPING FUNCTION: test_macs32_v2i16
SKIP: Target does not want to outline from function by default
*** Discarding overlapping candidates *** 
Searching for overlaps in all repeated sequences...
*** Outlining ***
NUMBER OF POTENTIAL FUNCTIONS: 0
WALKING FUNCTION LIST
OutlinedSomething = 0
Stopped outlining at iteration 0 because no changes were found.
*** IR Dump After Machine Outliner (machine-outliner) ***
; ModuleID = 'cecil_test.c'
source_filename = "cecil_test.c"
target datalayout = "e-m:e-p:32:32-i64:64-n32-S128"
target triple = "riscv32-unknown-unknown"

; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none)
define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
entry:
  %sext = shl i32 %x, 16
  %conv1 = ashr exact i32 %sext, 16
  %sext18 = shl i32 %y, 16
  %conv4 = ashr exact i32 %sext18, 16
  %mul = mul nsw i32 %conv4, %conv1
  %conv7 = ashr i32 %x, 16
  %conv11 = ashr i32 %y, 16
  %mul12 = mul nsw i32 %conv11, %conv7
  %add = add i32 %mul12, %acc
  %add13 = add i32 %add, %mul
  ret i32 %add13
}

attributes #0 = { mustprogress nofree norecurse nosync nounwind willreturn memory(none) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="generic-rv32" "target-features"="+32bit,+m,+relax,+xseal5testalucvabs16,+xseal5testalucvabs32,+xseal5testalucvabs8,+xseal5testalucvaddnrsi16,+xseal5testalucvaddnrsi32,+xseal5testalucvaddnrui16,+xseal5testalucvaddnrui32,+xseal5testalucvaddns,+xseal5testalucvaddnu,+xseal5testalucvaddrnrsi16,+xseal5testalucvaddrnrsi32,+xseal5testalucvaddrnrui16,+xseal5testalucvaddrnrui32,+xseal5testalucvaddrns,+xseal5testalucvaddrnu,+xseal5testalucvextbs,+xseal5testalucvextbz,+xseal5testalucvexths,+xseal5testalucvexthz,+xseal5testalucvmaxi1216,+xseal5testalucvmaxi1232,+xseal5testalucvmaxi516,+xseal5testalucvmaxi532,+xseal5testalucvmaxs16,+xseal5testalucvmaxs32,+xseal5testalucvmaxs8,+xseal5testalucvmaxu16,+xseal5testalucvmaxu32,+xseal5testalucvmaxu8,+xseal5testalucvmini1216,+xseal5testalucvmini1232,+xseal5testalucvmini516,+xseal5testalucvmini532,+xseal5testalucvmins16,+xseal5testalucvmins32,+xseal5testalucvmins8,+xseal5testalucvminu16,+xseal5testalucvminu32,+xseal5testalucvminu8,+xseal5testalucvsletsi16,+xseal5testalucvsletsi32,+xseal5testalucvsletui16,+xseal5testalucvsletui32,+xseal5testalucvsubnrsi16,+xseal5testalucvsubnrsi32,+xseal5testalucvsubnrui16,+xseal5testalucvsubnrui32,+xseal5testalucvsubns,+xseal5testalucvsubnu,+xseal5testalucvsubrnrsi16,+xseal5testalucvsubrnrsi32,+xseal5testalucvsubrnrui16,+xseal5testalucvsubrnrui32,+xseal5testalucvsubrns,+xseal5testalucvsubrnu,+xseal5testmaccvmachhns,+xseal5testmaccvmachhnu,+xseal5testmaccvmachhrns,+xseal5testmaccvmachhrnu,+xseal5testmaccvmacns,+xseal5testmaccvmacnu,+xseal5testmaccvmacrns,+xseal5testmaccvmacrnu,+xseal5testmaccvmacsi16,+xseal5testmaccvmacsi32,+xseal5testmaccvmacui16,+xseal5testmaccvmacui32,+xseal5testmaccvmsusi16,+xseal5testmaccvmsusi32,+xseal5testmaccvmsuui16,+xseal5testmaccvmsuui32,+xseal5testmaccvmulhhns,+xseal5testmaccvmulhhnu,+xseal5testmaccvmulhhrns,+xseal5testmaccvmulhhrnu,+xseal5testmaccvmulns,+xseal5testmaccvmulnu,+xseal5testmaccvmulrns,+xseal5testmaccvmulrnu,-a,-c,-d,-e,-experimental-zacas,-experimental-zcmop,-experimental-zfbfmin,-experimental-zicfilp,-experimental-zicfiss,-experimental-zimop,-experimental-ztso,-experimental-zvfbfmin,-experimental-zvfbfwma,-f,-h,-smaia,-smepmp,-ssaia,-svinval,-svnapot,-svpbmt,-v,-xcvalu,-xcvbi,-xcvbitmanip,-xcvelw,-xcvmac,-xcvmem,-xcvsimd,-xsfvcp,-xsfvfnrclipxfqf,-xsfvfwmaccqqq,-xsfvqmaccdod,-xsfvqmaccqoq,-xtheadba,-xtheadbb,-xtheadbs,-xtheadcmo,-xtheadcondmov,-xtheadfmemidx,-xtheadmac,-xtheadmemidx,-xtheadmempair,-xtheadsync,-xtheadvdot,-xventanacondops,-za128rs,-za64rs,-zawrs,-zba,-zbb,-zbc,-zbkb,-zbkc,-zbkx,-zbs,-zca,-zcb,-zcd,-zce,-zcf,-zcmp,-zcmt,-zdinx,-zfa,-zfh,-zfhmin,-zfinx,-zhinx,-zhinxmin,-zic64b,-zicbom,-zicbop,-zicboz,-ziccamoa,-ziccif,-zicclsm,-ziccrse,-zicntr,-zicond,-zicsr,-zifencei,-zihintntl,-zihintpause,-zihpm,-zk,-zkn,-zknd,-zkne,-zknh,-zkr,-zks,-zksed,-zksh,-zkt,-zmmul,-zvbb,-zvbc,-zve32f,-zve32x,-zve64d,-zve64f,-zve64x,-zvfh,-zvfhmin,-zvkb,-zvkg,-zvkn,-zvknc,-zvkned,-zvkng,-zvknha,-zvknhb,-zvks,-zvksc,-zvksed,-zvksg,-zvksh,-zvkt,-zvl1024b,-zvl128b,-zvl16384b,-zvl2048b,-zvl256b,-zvl32768b,-zvl32b,-zvl4096b,-zvl512b,-zvl64b,-zvl65536b,-zvl8192b" }

!llvm.module.flags = !{!0, !1, !2}
!llvm.ident = !{!3}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 1, !"target-abi", !"ilp32"}
!2 = !{i32 8, !"SmallDataLimit", i32 8}
!3 = !{!"clang version 18.1.0rc (https://github.com/llvm/llvm-project.git 1acc4e456481e76822c76c850bad3994d4e04b59)"}
# *** IR Dump Before Stack Frame Layout Analysis (stack-frame-layout) ***:
# Machine code for function test_macs32_v2i16: NoPHIs, TracksLiveness, NoVRegs, Legalized, RegBankSelected, Selected, TiedOpsRewritten, TracksDebugUserValues
Function Live Ins: $x10, $x11, $x12

bb.0.entry:
  liveins: $x10, $x11, $x12
  renamable $x10 = cv_machhNs_ killed renamable $x10(tied-def 0), renamable $x11, renamable $x12, 0
  renamable $x10 = cv_macs_i16_ killed renamable $x10(tied-def 0), killed renamable $x11, killed renamable $x12
  PseudoRET implicit $x10

# End machine code for function test_macs32_v2i16.

# *** IR Dump After Stack Frame Layout Analysis (stack-frame-layout) ***:
# Machine code for function test_macs32_v2i16: NoPHIs, TracksLiveness, NoVRegs, Legalized, RegBankSelected, Selected, TiedOpsRewritten, TracksDebugUserValues
Function Live Ins: $x10, $x11, $x12

bb.0.entry:
  liveins: $x10, $x11, $x12
  renamable $x10 = cv_machhNs_ killed renamable $x10(tied-def 0), renamable $x11, renamable $x12, 0
  renamable $x10 = cv_macs_i16_ killed renamable $x10(tied-def 0), killed renamable $x11, killed renamable $x12
  PseudoRET implicit $x10

# End machine code for function test_macs32_v2i16.

# *** IR Dump Before RISC-V Zcmp move merging pass (riscv-move-merge) ***:
# Machine code for function test_macs32_v2i16: NoPHIs, TracksLiveness, NoVRegs, Legalized, RegBankSelected, Selected, TiedOpsRewritten, TracksDebugUserValues
Function Live Ins: $x10, $x11, $x12

bb.0.entry:
  liveins: $x10, $x11, $x12
  renamable $x10 = cv_machhNs_ killed renamable $x10(tied-def 0), renamable $x11, renamable $x12, 0
  renamable $x10 = cv_macs_i16_ killed renamable $x10(tied-def 0), killed renamable $x11, killed renamable $x12
  PseudoRET implicit $x10

# End machine code for function test_macs32_v2i16.

# *** IR Dump After RISC-V Zcmp move merging pass (riscv-move-merge) ***:
# Machine code for function test_macs32_v2i16: NoPHIs, TracksLiveness, NoVRegs, Legalized, RegBankSelected, Selected, TiedOpsRewritten, TracksDebugUserValues
Function Live Ins: $x10, $x11, $x12

bb.0.entry:
  liveins: $x10, $x11, $x12
  renamable $x10 = cv_machhNs_ killed renamable $x10(tied-def 0), renamable $x11, renamable $x12, 0
  renamable $x10 = cv_macs_i16_ killed renamable $x10(tied-def 0), killed renamable $x11, killed renamable $x12
  PseudoRET implicit $x10

# End machine code for function test_macs32_v2i16.

# *** IR Dump Before RISC-V Zcmp Push/Pop optimization pass (riscv-push-pop-opt) ***:
# Machine code for function test_macs32_v2i16: NoPHIs, TracksLiveness, NoVRegs, Legalized, RegBankSelected, Selected, TiedOpsRewritten, TracksDebugUserValues
Function Live Ins: $x10, $x11, $x12

bb.0.entry:
  liveins: $x10, $x11, $x12
  renamable $x10 = cv_machhNs_ killed renamable $x10(tied-def 0), renamable $x11, renamable $x12, 0
  renamable $x10 = cv_macs_i16_ killed renamable $x10(tied-def 0), killed renamable $x11, killed renamable $x12
  PseudoRET implicit $x10

# End machine code for function test_macs32_v2i16.

# *** IR Dump After RISC-V Zcmp Push/Pop optimization pass (riscv-push-pop-opt) ***:
# Machine code for function test_macs32_v2i16: NoPHIs, TracksLiveness, NoVRegs, Legalized, RegBankSelected, Selected, TiedOpsRewritten, TracksDebugUserValues
Function Live Ins: $x10, $x11, $x12

bb.0.entry:
  liveins: $x10, $x11, $x12
  renamable $x10 = cv_machhNs_ killed renamable $x10(tied-def 0), renamable $x11, renamable $x12, 0
  renamable $x10 = cv_macs_i16_ killed renamable $x10(tied-def 0), killed renamable $x11, killed renamable $x12
  PseudoRET implicit $x10

# End machine code for function test_macs32_v2i16.

# *** IR Dump Before RISC-V pseudo instruction expansion pass (riscv-expand-pseudo) ***:
# Machine code for function test_macs32_v2i16: NoPHIs, TracksLiveness, NoVRegs, Legalized, RegBankSelected, Selected, TiedOpsRewritten, TracksDebugUserValues
Function Live Ins: $x10, $x11, $x12

bb.0.entry:
  liveins: $x10, $x11, $x12
  renamable $x10 = cv_machhNs_ killed renamable $x10(tied-def 0), renamable $x11, renamable $x12, 0
  renamable $x10 = cv_macs_i16_ killed renamable $x10(tied-def 0), killed renamable $x11, killed renamable $x12
  PseudoRET implicit $x10

# End machine code for function test_macs32_v2i16.

# *** IR Dump After RISC-V pseudo instruction expansion pass (riscv-expand-pseudo) ***:
# Machine code for function test_macs32_v2i16: NoPHIs, TracksLiveness, NoVRegs, Legalized, RegBankSelected, Selected, TiedOpsRewritten, TracksDebugUserValues
Function Live Ins: $x10, $x11, $x12

bb.0.entry:
  liveins: $x10, $x11, $x12
  renamable $x10 = cv_machhNs_ killed renamable $x10(tied-def 0), renamable $x11, renamable $x12, 0
  renamable $x10 = cv_macs_i16_ killed renamable $x10(tied-def 0), killed renamable $x11, killed renamable $x12
  PseudoRET implicit $x10

# End machine code for function test_macs32_v2i16.

# *** IR Dump Before RISC-V atomic pseudo instruction expansion pass (riscv-expand-atomic-pseudo) ***:
# Machine code for function test_macs32_v2i16: NoPHIs, TracksLiveness, NoVRegs, Legalized, RegBankSelected, Selected, TiedOpsRewritten, TracksDebugUserValues
Function Live Ins: $x10, $x11, $x12

bb.0.entry:
  liveins: $x10, $x11, $x12
  renamable $x10 = cv_machhNs_ killed renamable $x10(tied-def 0), renamable $x11, renamable $x12, 0
  renamable $x10 = cv_macs_i16_ killed renamable $x10(tied-def 0), killed renamable $x11, killed renamable $x12
  PseudoRET implicit $x10

# End machine code for function test_macs32_v2i16.

# *** IR Dump After RISC-V atomic pseudo instruction expansion pass (riscv-expand-atomic-pseudo) ***:
# Machine code for function test_macs32_v2i16: NoPHIs, TracksLiveness, NoVRegs, Legalized, RegBankSelected, Selected, TiedOpsRewritten, TracksDebugUserValues
Function Live Ins: $x10, $x11, $x12

bb.0.entry:
  liveins: $x10, $x11, $x12
  renamable $x10 = cv_machhNs_ killed renamable $x10(tied-def 0), renamable $x11, renamable $x12, 0
  renamable $x10 = cv_macs_i16_ killed renamable $x10(tied-def 0), killed renamable $x11, killed renamable $x12
  PseudoRET implicit $x10

# End machine code for function test_macs32_v2i16.

# *** IR Dump Before Unpack machine instruction bundles (unpack-mi-bundles) ***:
# Machine code for function test_macs32_v2i16: NoPHIs, TracksLiveness, NoVRegs, Legalized, RegBankSelected, Selected, TiedOpsRewritten, TracksDebugUserValues
Function Live Ins: $x10, $x11, $x12

bb.0.entry:
  liveins: $x10, $x11, $x12
  renamable $x10 = cv_machhNs_ killed renamable $x10(tied-def 0), renamable $x11, renamable $x12, 0
  renamable $x10 = cv_macs_i16_ killed renamable $x10(tied-def 0), killed renamable $x11, killed renamable $x12
  PseudoRET implicit $x10

# End machine code for function test_macs32_v2i16.

# *** IR Dump After Unpack machine instruction bundles (unpack-mi-bundles) ***:
# Machine code for function test_macs32_v2i16: NoPHIs, TracksLiveness, NoVRegs, Legalized, RegBankSelected, Selected, TiedOpsRewritten, TracksDebugUserValues
Function Live Ins: $x10, $x11, $x12

bb.0.entry:
  liveins: $x10, $x11, $x12
  renamable $x10 = cv_machhNs_ killed renamable $x10(tied-def 0), renamable $x11, renamable $x12, 0
  renamable $x10 = cv_macs_i16_ killed renamable $x10(tied-def 0), killed renamable $x11, killed renamable $x12
  PseudoRET implicit $x10

# End machine code for function test_macs32_v2i16.

