Metadata-Version: 2.4
Name: hdltbgen
Version: 1.0.13
Summary: HDL Testbench Generator
Author-email: Janik Witzig <janik.witzig@ost.ch>, Lukas Leuenberger <lukas.leuenberger@ost.ch>
Project-URL: Homepage, https://hdltbgen.xibif.ch/
Project-URL: Repository, https://gitlab.com/xibif/hdltbgen
Project-URL: Issues, https://gitlab.com/xibif/hdltbgen/-/issues
Classifier: Programming Language :: Python :: 3
Requires-Python: >=3.9
Description-Content-Type: text/markdown
License-File: LICENSE
Requires-Dist: jinja2
Provides-Extra: excel
Requires-Dist: openpyxl; extra == "excel"
Requires-Dist: xlwings; extra == "excel"
Dynamic: license-file

# hdltbgen

HDL Testbench Generator – parses a VHDL entity and generates testbench artifacts.

## Installation

```bash
pip install hdltbgen
```

Excel support: `pip install "hdltbgen[excel]"`


## Functionality

- Parses a `.vhd` entity interface (generics and ports)
- Generates testbench artifacts: `vhdl`, `csv`, `excel`
- Supports automatic clock/reset detection (or explicit CLI override)
- Can generate VUnit-compatible output and an optional sim wrapper
- Supports interactive generic value entry via `--ask`
- Can generate multiple artifact types in one run by repeating `-t`

## Usage

```bash
hdltbgen -f my_design.vhd -t vhdl
```

| Argument | Short | Description |
|---|---|---|
| `--file` | `-f` | VHDL input file (required) |
| `--type` | `-t` | Output type: `vhdl`, `csv`, `excel` (repeatable, required) |
| `--output` | `-o` | Output directory (default: input file directory) |
| `--clock` | `-c` | Clock signal name(s) |
| `--reset-negative` | `-rn` | Active-low reset name(s) |
| `--reset-positive` | `-rp` | Active-high reset name(s) |
| `--vunit` | `-v` | VUnit-compatible testbench |
| `--simfile` | `-s` | Generate separate simulation wrapper |
| `--ask` | `-a` | Prompt for generic values |
